![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to dmp.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / demand|
Return to dmp.c CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / demand |
1.1 root 1: #include "definitions"
2:
3: asm(".data");
4:
5: /* clrl r5 : register mode */
6: #define I0 2
7: char CLRL0[] = { 0x4d,0x55 };
8:
9: /* clrl -(sp) : auto decrement */
10: #define I1 2
11: char CLRL1[] = { 0x4d,0x7e };
12:
13: /* clrl *(sp)+ : auto increment deferred */
14: #define I2 2
15: char CLRL2[] = { 0x4d,0x9e };
16:
17: /* clrl *12(r5)[r6] : longword displacement deferred indexed */
18: #define I3 7
19: char CLRL3[] = { 0x4d,0x46,0xf5,0x00,0x00,0x00,0x0c };
20:
21: /* clrl *loc[r6] : longword relative deferred indexed */
22: /* loc is 1 Page away from PC */
23: #define I4 7
24: char CLRL4[] = { 0x4d,0x46,0xff,0x00,0x00,0x03,0xfc };
25:
26: /* 4 Operands : emul *12(r3)[r4],r5,*12(r6)[r7],*12(r10)[r9] */
27: #define I5 20
28: char EMUL[] = { 0x2e,0x44,0xf3,0x00,0x00,0x00,0x0c,0x55,
29: 0x47,0xf6,0x00,0x00,0x00,0x0c,0x49,0xfa,0x00,0x00,0x00,
30: 0x0c };
31:
32: char KCALL[] = { 0xcf,0x50 }; /* kcall r0 */
33:
34: asm(".text");
35:
36: extern long iob2, iob3, u0p2pt, pcb0, savvec4, savvec5, savvec6, savvec7;
37: extern long ret_adr, saved_sp, saved_fp, *p_ptr;
38:
39:
40:
41: /* Demand paging with CALLS instruction
42: This test run virtual in P0 space with Kernel Privilege. Two entries in
43: P2PT are mapped to iob2 and iob3. USP is set to 2nd word of page iob3,
44: PTE of Page iob2 is then set to invalid. Program do
45: a REI to user code which will execute the "calls" instruction , FP get
46: push on the stack, FP is set to current SP, at this point SP is pointing
47: to the 1st longword of page 98 and as soon as processor try to push the
48: mask/arg on the the stack, SP point to last longword of the invalid page
49: then page fault occurs.
50: If USP is set point to a few longwords away from the top of page 98,then
51: page fault will occur when processor try to push PC or registers on the
52: stack.
53: */
54:
55: long exp_fp, act_sp, act_fp, act_pc, act_psl;
56:
57: dmp()
58: { long *lptr, t_pte0, t_pte1;
59:
60: asm("mfpr $SBR,_savvec4");
61: savvec4 |= (savvec4 | SADDR); /* Make it system address */
62: asm("mtpr _savvec4,$P0BR"); /* Double map P0PT to SPT */
63: asm("mfpr $SLR,_savvec4");
64: asm("mtpr _savvec4,$P0LR");
65:
66: asm("mtpr $6,$DCK");
67: asm("mtpr $0,$TBIA");
68: asm("mtpr $0,$PADC");
69: asm("mtpr $1,$MME"); /* Enable MME */
70: asm("jmp *$0f"); /* Go virtual */
71: asm("0:");
72: /* Set up P2 space */
73: lptr = &u0p2pt;
74: *lptr = (IOB2); /* 1st PTE map to IOB2 */
75: *(lptr+1) = (IOB3); /* 1st PTE map to IOB3 */
76: savvec4 = ((long)lptr) | SADDR;
77: savvec4 -= ((LAST_VPGNO-1) << 2);
78: asm("mtpr _savvec4,$P2BR");
79: asm("mtpr $0xffffd,$P2LR"); /* Use only 2 entries */
80:
81: asm("movab fpc1,_savvec4");
82: savvec4 = (savvec4 >> PGSHIFT) & PTE_PFN; /* Make test area */
83: fixpv_pte(P0BR,savvec4,&t_pte0,(PTE_V | PTE_UW)); /* User R/W */
84: fixpv_pte(P0BR,savvec4+1,&t_pte1,(PTE_V | PTE_UW));
85:
86: tst_call();
87: asm("mtpr $0,$MME"); /* Disable MME */
88: asm("mtpr $0,$P0LR");
89: }
90:
91:
92: tst_call()
93: { char *msg1, *msg2;
94: long saved_pte, saved_vec1, saved_vec2, dummy;
95: long reipc, exp_pc, exp_sp, exp_psl;
96:
97: /* Set up PCBB */
98: savvec4 = (long)&pcb0;
99: asm("mtpr _savvec4,$PCBB");
100:
101: fixpv_pte(P2BR,TST0_PTEP2,&saved_pte,(PTE_V|PTE_UW));
102: fixpv_pte(P2BR,TST1_PTEP2,&saved_pte,PTE_UW); /* Set V bit off */
103: asm("movab fpc1,_savvec4");
104: exp_pc = savvec4; /* Expected PC */
105: exp_sp = ((TST0_PTEP2 << PGSHIFT) | 8) | P2ADDR; /* Expected SP */
106: savvec4 = exp_sp;
107: asm("mtpr _savvec4,$USP"); /* Set USP point to valid page */
108: exp_fp = savvec4 + 4;
109: asm("movab (sp),_savvec4");
110: savvec4 -= 16; /* KSP is 4 words below IS */
111: asm("mtpr _savvec4,$KSP"); /* Set KSP */
112: asm("movab trans_flt,_savvec4"); /* New handler for TRANS_FLT */
113: set_handler(TRANS_VEC,&saved_vec1,savvec4);
114:
115:
116: exp_psl = PSL_USR; /* PSL : User mode */
117: savvec6 = exp_psl;
118: asm("pushl _savvec6"); /* Push PSL */
119: asm("movab fpc1,_savvec7");
120: asm("pushl _savvec7"); /* Push PC */
121:
122: asm("movl fp,_saved_fp"); /* save FP to return */
123: asm("movl _exp_fp,fp");
124: asm("mtpr $1,$PACC"); /* Purge all code cache */
125: asm("d1pc:");
126: asm("rei"); /* ISP is saved here */
127: asm("halt");
128: asm(".align 2");
129: asm("rtn_here:");
130: asm("movl _saved_fp,fp"); /* restore FP */
131: if (act_pc != exp_pc)
132: {
133: msg1="** PC pushed on the stack is not correct.";
134: d1err(msg1,act_pc,exp_pc,exp_pc,exp_sp);
135: }
136: if (exp_sp != act_sp)
137: {
138: msg1="** SP is not restored to original value after translation not valid fault";
139: d1err(msg1,act_sp,exp_sp,exp_pc,exp_sp);
140: }
141: if (exp_fp != act_fp)
142: {
143: msg2="** FP is not restored to original value after translation not valid fault";
144: d1err(msg1,act_fp,exp_fp,exp_pc,exp_sp);
145: }
146: /* set page at fault to valid and restart instruction at PC */
147: fixpv_pte(P2BR,TST1_PTEP2,&saved_pte,(PTE_V|PTE_UW));
148: set_handler(TRANS_VEC,&dummy,saved_vec1); /* restore handler */
149: asm("movab kcall_dmp,_savvec4"); /* New handler for KCALL */
150: set_handler(CHMK_VEC,&saved_vec1,savvec4);
151: asm("pushl _savvec6"); /* Push PSL */
152: asm("pushl _savvec7"); /* Push PC */
153: asm("rei");
154: asm("halt");
155: asm("good_rtn:");
156: asm("movl _saved_fp,fp"); /* restore FP */
157: set_handler(CHMK_VEC,&dummy,saved_vec1);
158: }
159:
160: T_AREA()
161: {
162: asm("fpc1:");
163: asm("calls $4,_proc"); /* should cause translation not valid fault */
164: asm("kcall $0"); /* return */
165: }
166:
167: /* Dummy procedure to test demand paging with CALLS instruction */
168: proc()
169: {
170: asm("ret");
171: }
172:
173:
174: ex_area()
175: {
176: asm(".align 2"); /* Longword align */
177: asm("trans_flt:");
178:
179: asm("mtpr $0x1f,$IPL");
180: asm("movl (sp)+,r12"); /* Pop 1st two paramters */
181: asm("movl (sp)+,r12");
182: asm("movl (sp)+,_act_pc"); /* Actual PC */
183: asm("movl (sp)+,_act_psl"); /* Actual PSL */
184: asm("movl fp,_act_fp"); /* Actual FP */
185: asm("mfpr $USP,_act_sp"); /* Actual SP */
186: asm("svpctx"); /* Switch back to IS */
187: asm("jmp rtn_here"); /* return */
188:
189: asm("kcall_dmp:");
190: asm("mtpr $0x1f,$IPL");
191: asm("svpctx"); /* Switch back to IS */
192: asm("jmp good_rtn"); /* return */
193: }
194:
195:
196: d1err(msg1,act,exp,pc,sp)
197: char *msg1;
198: long act, exp, pc, sp;
199: {
200: writes(msg1);
201: writes("\n** Actual : "); writeh(act);
202: writes("\n** Expect : "); writeh(exp);
203: writes("\n** PC (CALLS intruction) : "); writeh(pc);
204: writes("\n** SP (before CALLS) : "); writeh(sp);
205: writec('\n');
206: asm("halt");
207: }
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.