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1.1 root 1: #include "data.h"
2:
3: #include "definitions"
4:
5:
6: long exp_psl, exp_pc, act_pc, exp_result, act_result, exp_sp, act_sp;
7: long dummy, *opr_adr, *fault_vadr, saved_vec1, saved_vec2, saved_pte, temp_glb;
8: long d6pc;
9: extern long exp_fvadr, act_fvadr;
10: char *msg1, *msg2, *bptr;
11:
12:
13: extern long iob1, iob2, iob3, u0p2pt, pcb0, savvec4, savvec5, savvec6, savvec7;
14: extern long ret_adr, saved_sp, saved_fp, *p_ptr;
15:
16:
17:
18: /* Demand paging with longword relative deferred indexed
19: Boundery of virtual Page _iob0 and _iob1 are used in this test. Opcodes of
20: the "clrl *loc[r6]" instruction (loc is 1 page away from PC) is moved
21: to last byte in page _iob0 and operand specifiers are moved to 1st bytes
22: in page _iob1. PTE of Page _iob1 is then set to invalid.
23: */
24:
25:
26: dmp4()
27: {
28: asm("mfpr $SBR,_savvec4");
29: savvec4 |= (savvec4 | SADDR); /* Make it system address */
30: asm("mtpr _savvec4,$P0BR"); /* Double map P0PT to SPT */
31: asm("mfpr $SLR,_savvec4");
32: asm("mtpr _savvec4,$P0LR");
33:
34: asm("mtpr $6,$DCK");
35: asm("mtpr $0,$TBIA");
36: asm("mtpr $0,$PADC");
37: asm("mtpr $1,$MME"); /* Enable MME */
38: asm("jmp *$0f"); /* Go virtual */
39: asm("0:");
40: dpt4();
41: asm("mtpr $0,$MME");
42: asm("mtpr $0,$P0LR");
43: }
44:
45:
46: dpt4()
47: { char *byte_ptr;
48: long ix, byte_no;
49:
50: savvec4 = (long)&pcb0;
51: asm("mtpr _savvec4,$PCBB"); /* Set PCBB */
52: asm("movab act_opr,_savvec4"); /* Make test loc user R/W */
53: savvec4 = (savvec4 >> PGSHIFT) & 0xfffff;
54: fixpv_pte(P0BR,savvec4,&saved_pte,(PTE_V|PTE_UW));
55:
56: for(byte_no=1;byte_no<I4;byte_no++)
57: {
58: /* Move code to boundery of test page */
59: exp_pc = ((TEST_PG-1)<<PGSHIFT)|(NBPG-byte_no);
60: byte_ptr = (char *)exp_pc;
61: for(ix=0;ix<I4;ix++) *byte_ptr++ = CLRL4[ix];
62: bptr = byte_ptr - 1; /* Point to last byte : displacement */
63: *byte_ptr++ = KCALL[0]; /* move KCALL instruction */
64: *byte_ptr = KCALL[1];
65:
66: /* Compute address of operand */
67: opr_adr = (long *) (exp_pc + I4); /* PC after fetching instruction */
68: opr_adr = (long *)((long)opr_adr+NBPG-4); /* PC after add in displ. */
69:
70: /* Make data longword align */
71: switch ( ((long)opr_adr) & 0x3)
72: {
73: case 1 : { opr_adr = (long *)( (long)opr_adr + 3);
74: *bptr = 0xff; /* Modify displacement */
75: break; }
76: case 2 : { opr_adr = (long *)( (long)opr_adr + 2);
77: *bptr = 0xfe; /* Modify displacement */
78: break; }
79: case 3 : { opr_adr = (long *)( (long)opr_adr + 1);
80: *bptr = 0xfd; /* Modify displacement */
81: break; }
82: }
83: savvec6 = (long)opr_adr; /* Make base addr user READ/WRITE */
84: savvec6 = (savvec6 >> PGSHIFT) & 0xfffff;
85: fixpv_pte(P0BR,savvec6,&saved_pte,(PTE_V|PTE_UW));
86: fixpv_pte(P0BR,(savvec6+1),&saved_pte,(PTE_V|PTE_UW));
87:
88: asm("movab bopr_t4,_savvec4");
89: asm("movl _savvec4,*_opr_adr"); /* Set base addr of operand */
90: asm("movl $0xffffffff,act_opr"); /* Set dummy value in operand */
91:
92: fixpv_pte(P0BR,(TEST_PG-1),&saved_pte,(PTE_V|PTE_UW));
93:
94: /* Invalidate PTE of test page */
95: exp_fvadr = (TEST_PG<<PGSHIFT) & 0xfffffc00;
96: fixpv_pte(P0BR,TEST_PG,&saved_pte,PTE_UW);
97:
98: /* Set new exception handlers */
99: asm("movab trans_f4,_savvec4");
100: set_handler(TRANS_VEC,&saved_vec1,savvec4);
101:
102: asm("movab (sp),_savvec4");
103: savvec4 -= 16; /* KSP is 4 words below ISP */
104: asm("mtpr _savvec4,$KSP");
105:
106: asm("movl fp,_saved_fp"); /* save FP to return */
107: exp_result = 0;
108: exp_psl = PSL_USR; /* PSL : user mode */
109: asm("pushl _exp_psl"); /* Push PSL on stack */
110: asm("pushl _exp_pc"); /* Push PC on stack */
111:
112: /* Set up for CLRL *loc[r6] */
113: asm("movl $1,r6"); /* Set index value in r6 */
114: asm("mtpr $1,$PACC"); /* Purge all code cache */
115: asm("movab d6rei,_d6pc");
116: asm("d6rei:");
117: asm("rei");
118: asm("halt");
119:
120: asm(".align 2");
121: asm("rtn_t40:"); /* Return from error */
122: asm("movl _saved_fp,fp"); /* restore FP */
123: break;
124: asm("rtn_t41:");
125: asm("movl _saved_fp,fp"); /* restore FP */
126: asm("movl act_opr,_act_result"); /* Get actual result */
127: if (act_result != exp_result)
128: {
129: msg1 = "** Incorrect result after instruction is restarted.\n";
130: d2err(msg1,act_result,exp_result,exp_pc,d6pc,exp_fvadr);
131: }
132: set_handler(CHMK_VEC,&dummy,saved_vec2); /* Restore KCALL vector */
133: }
134: }
135:
136:
137:
138:
139: new_hdr4()
140: {
141:
142: asm(".align 2"); /* Longword align */
143: asm("trans_f4:");
144:
145: asm("mtpr $0x1f,$IPL");
146: asm("movl (sp)+,r12"); /* Ignore 1st parameter */
147: asm("movl (sp)+,_act_fvadr"); /* Actual VA at fault */
148: asm("movl (sp),_act_pc"); /* PC that caused fault */
149: asm("movab (sp),fp"); /* set new frame pointer */
150: if ( act_pc != exp_pc )
151: { /* Error in PC */
152: msg1="** PC pushed on the stack is not correct.\n";
153: d2err(msg1,act_pc,exp_pc,exp_pc,d6pc,exp_fvadr);
154: asm("svpctx"); /* Back to ISP */
155: asm("jmp rtn_t40"); /* return */
156: }
157: if ( (act_fvadr & 0xfffffc00) != (exp_fvadr & 0xfffffc00) )
158: { /* Error in PC */
159: msg1="** Fault virtual address pushed on the stack is not correct\n";
160: d2err(msg1,(act_fvadr&0xfffffc00),(exp_fvadr&0xfffffc00),exp_pc,d6pc,exp_fvadr);
161: asm("svpctx"); /* Back to ISP */
162: asm("jmp rtn_t40"); /* return */
163: }
164: else
165: {
166: /* Set V bit and restart instruction at PC */
167: fixpv_pte(P0BR,TEST_PG,&saved_pte,(PTE_V|PTE_UW));
168: asm("movab kcall4,_savvec4"); /* New handler for KCALL */
169: set_handler(CHMK_VEC,&saved_vec2,savvec4);
170: /* restore original vector of TRANSLATION fault */
171: set_handler(TRANS_VEC,&temp_glb,saved_vec1);
172: asm("movab d61rei,_d6pc");
173: asm("d61rei:");
174: asm("rei");
175: asm("halt");
176: }
177:
178: asm(".align 2");
179: asm("kcall4:");
180: asm("mtpr $0x1f,$IPL");
181: asm("svpctx"); /* Back to ISP */
182: asm("jmp rtn_t41");
183: }
184:
185: t_area4()
186: {
187: asm(".align 2");
188: asm("bopr_t4:");
189: asm(".long 0");
190: asm("act_opr:");
191: asm(".long 0"); /* Actual operand */
192: }
193:
194:
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