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1.1 root 1: #include "data.h"
2: #include "definitions"
3:
4: extern long savvec4, iob1, iob2, pcb0;
5:
6: /* Demand paging with longword displacement deferred indexed.
7: Intruction used for this test is CLRL *12(R5)[r6]. This test force
8: a translation fault at AG level (2nd). To compute the effective
9: address of operand, content of R5 is added by 12 bytes (displacement)
10: to give an indirect address which is then fetched and indexed by R6
11: to give the operand address. This test force a fault by setting the
12: PTE of the indirect address to invalid and then the fault handler
13: will valid this PTE (turn V_bit on) and restart the instruction.
14: */
15:
16: long dummy, exp_pc, act_pc, exp_psl, exp_val, act_val;
17: long d8pc, tst_pte, saved_vec1, saved_vec2, saved_pte1, saved_pte2, saved_pte3;
18: extern long exp_fvadr, act_fvadr;
19: char *msg1, *msg2;
20:
21:
22: dmp6()
23: {
24:
25: asm("mfpr $SBR,_savvec4");
26: savvec4 |= (savvec4 | SADDR); /* Make it system address */
27: asm("mtpr _savvec4,$P0BR"); /* Double map P0PT to SPT */
28: asm("mfpr $SLR,_savvec4");
29: asm("mtpr _savvec4,$P0LR");
30:
31: asm("mtpr $6,$DCK");
32: asm("mtpr $0,$TBIA");
33: asm("mtpr $0,$PADC");
34: asm("mtpr $1,$MME"); /* Enable MME */
35: asm("jmp *$0f"); /* Go virtual */
36: asm("0:");
37: tst_dmp6();
38: asm("mtpr $0,$MME"); /* Disable MME */
39: asm("mtpr $0,$P0LR");
40: }
41:
42:
43: tst_dmp6()
44: { char *byte_ptr, *msg1, *msg2;
45: long ix, hdr_adr, pc_err, byte_no;
46:
47: savvec4 = (long)&pcb0;
48: asm("mtpr _savvec4,$PCBB"); /* Initialize PCBB */
49:
50: /* Move code to boundery of page */
51: exp_pc = ((TEST_PG-1)<<PGSHIFT)|(NBPG-1);
52: byte_ptr = (char *)exp_pc;
53: for(ix=0;ix<I3;ix++) *byte_ptr++ = CLRL3[ix];
54: *byte_ptr++ = KCALL[0]; /* move KCALL instruction */
55: *byte_ptr = KCALL[1];
56: /* Make code area user accessible */
57: fixpv_pte(P0BR,(TEST_PG-1),&saved_pte1,(PTE_V|PTE_UW));
58: fixpv_pte(P0BR,TEST_PG,&saved_pte2,(PTE_V|PTE_UW));
59: /* Make operand user accessible */
60: asm("movab operd,_dummy");
61: dummy = (dummy >> PGSHIFT) & 0xfffff; /* Page no */
62: fixpv_pte(P0BR,dummy,&saved_pte3,(PTE_V|PTE_UW));
63:
64: /* Invalidate PTE of indirect address */
65: asm("movab indr_adr,_tst_pte");
66: exp_fvadr = tst_pte; /* Expected VA at fault */
67: tst_pte = (tst_pte >> PGSHIFT) & 0xfffff; /* Page no */
68: fixpv_pte(P0BR,tst_pte,&saved_pte3,PTE_UW); /* Set PTE_V off */
69:
70: /* Set new exception handlers */
71: asm("movab prot_f3,_savvec4");
72: set_handler(TRANS_VEC,&saved_vec1,savvec4);
73:
74: /* Set up to execute REI */
75: asm("movab (sp),_savvec4");
76: savvec4 -= 16; /* KSP is 4 words below ISP */
77: asm("mtpr _savvec4,$KSP");
78: asm("movl fp,_saved_fp"); /* save FP to return */
79: exp_psl = PSL_USR; /* PSL : user mode */
80: asm("pushl _exp_psl"); /* Push PSL on stack */
81: asm("pushl _exp_pc"); /* Push PC on stack */
82:
83: /* Set up for CLRL *12(r5)[r6] */
84: asm("movab r5_here,r5");
85: asm("movl $1,r6"); /* Set index value in r6 */
86: asm("movl $0xfffffff,operd");
87: exp_val = 0;
88:
89: /* Use REI to switch to user mode */
90: asm("mtpr $1,$PACC"); /* Purge all code cache */
91: asm("movab d8rei,_d8pc");
92: asm("d8rei:");
93: asm("rei");
94: asm("halt");
95: asm(".align 2");
96: asm("rtn_t30:"); /* Return here if error */
97: asm("movl _saved_fp,fp"); /* restore FP */
98: return(0); /* Stop test */
99: asm("rtn_t31:");
100: asm("movl _saved_fp,fp"); /* restore FP */
101: asm("movl operd,_act_val");
102: set_handler(CHMK_VEC,&dummy,saved_vec2); /* restore handler */
103: if (exp_val != act_val) /* Demand paging fail !! */
104: {
105: msg1="** Incorrect result after instruction is restarted.\n";
106: d2err(msg1,act_val,exp_val,exp_pc,d8pc,exp_fvadr);
107: }
108: }
109:
110:
111: prot_hdl6()
112: {
113: asm(".align 2");
114: asm("prot_f3:");
115: asm("mtpr $0x1f,$IPL");
116: asm("movl (sp)+,r12"); /* Ignore 1st parameter */
117: asm("movl (sp)+,_act_fvadr"); /* Actual VA at fault */
118:
119: asm("movl (sp),_act_pc"); /* Actual PC that caused fault */
120: asm("movab (sp),fp"); /* Set FP */
121:
122: /* Check fault parameters */
123: if (act_pc != exp_pc) /* Check PC pushed on SP */
124: {
125: msg1="** PC pushed on the stack is not correct.\n";
126: d2err(msg1,act_pc,exp_pc,exp_pc,d8pc,exp_fvadr);
127: asm("svpctx"); /* Switch to ISP */
128: asm("jmp rtn_t30"); /* Error return */
129: }
130: if (act_fvadr != exp_fvadr) /* Check fault VA pushed on SP */
131: {
132: msg1="** Fault virtual address pushed on the stack is not correct.\n";
133: d2err(msg1,act_fvadr,exp_fvadr,exp_pc,d8pc,exp_fvadr);
134: asm("svpctx"); /* Switch to ISP */
135: asm("jmp rtn_t30"); /* Error return */
136: }
137: /* Restore original Translation fault vector */
138: set_handler(TRANS_VEC,&dummy,saved_vec1);
139:
140: asm("movab kcall3,_savvec4"); /* New handler for KCALL */
141: set_handler(CHMK_VEC,&saved_vec2,savvec4);
142:
143: /* Validate PTE of indirect addr and restart instruction */
144: fixpv_pte(P0BR,tst_pte,&dummy,(PTE_V|PTE_UW));
145: asm("movab d81rei,_d8pc");
146: asm("d81rei:");
147: asm("rei");
148:
149:
150: asm(".align 2");
151: asm("kcall3:"); /* KCALL handler */
152: asm("mtpr $0x1f,$IPL");
153: asm("svpctx"); /* Switch to ISP */
154: asm("jmp rtn_t31"); /* Return */
155: }
156:
157:
158:
159: t6_space()
160: {
161: /* Operand of CLRL *12(r5)[r6] */
162: asm(".space 1024"); /* Make sure this area is in next page */
163: asm(".align 2");
164: asm("r5_here:");
165: asm(".space 12"); /* 12 bytes for displacement */
166: asm("indr_adr:");
167: asm(".long base_op");
168: asm(".space 1024"); /* Make sure nothing else is in this page */
169:
170: asm(".data"); /* This is in DATA area */
171: asm(".align 2");
172: asm("base_op:");
173: asm(".long 0xffff"); /* four bytes for index by r6 */
174: asm(".globl operd");
175: asm("operd:");
176: asm(".long 0xffffffff");
177: /* this loc will be clear when inst. is restarted */
178: asm(".text");
179:
180: }
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