![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to INCLUDE CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / dmp4|
Return to INCLUDE CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / dmp4 |
1.1 root 1:
2: /* privileged registers constants (addresses) */
3:
4:
5:
6: .set SBR,0 /*system base register */
7: .set SLR,1 /*system length reg */
8: .set P0BR,2 /*p0 base reg */
9: .set P0LR,3 /*p0 length reg */
10: .set P1BR,4 /*p1 base reg */
11: .set P1LR,5 /*p1 length reg */
12: .set P2BR,6 /*p2 base reg */
13: .set P2LR,7 /*p2 length reg */
14: .set IPL,8 /*int priority level reg */
15: .set MME,9 /*memory mgmt enable reg */
16: .set TBIA,10 /*trans buf invalidate all */
17: /*entries */
18: .set TBIS,11 /*trans buf invalidate single */
19: /*entry */
20: .set DCK,12 /*data cache key */
21: .set CCK,13 /*code cache key */
22: .set PCBB,14 /*process control block base */
23: .set ISP,15 /*interrupt stack pointer */
24: .set SIRR,16 /*software int request reg */
25: .set SISR,17 /*software int summary reg */
26: .set SCBB,18 /*system control block base reg */
27: .set KSP,19 /*kernel stack pointer reg */
28: .set USP,20 /*user stack pointer */
29: .set DCB,21 /*CPU2 DCB */
30: .set PACC,23 /*purge (invalidate) all pages */
31: /*of process in code cache */
32: .set P1DC,24 /*purge one page of data cache */
33: .set PADC,25 /*purge all the pages of */
34: /*process in data cache */
35: .set HISR,26 /* Hardware interrupt summary reg */
36: .set DCR,27 /* Diagnostic control register */
37: .set PDCS,28 /* Purge 1 data cache slot */
38:
39: #
40: #TAHOE program status longword
41: #
42:
43: .set PSL_C,0x00000001 /* carry bit */
44: .set PSL_V,0x00000002 /* overflow bit */
45: .set PSL_Z,0x00000004 /* zero bit */
46: .set Z,0x00000004
47: .set PSL_N,0x00000008 /* negative bit */
48: .set PSL_T,0x00000010 /* trace enable bit */
49: .set PSL_I,0x00000020 /* integer overflow enable bit */
50: .set PSL_EN_OVFL,0x20 /* integer overflow enable bit */
51: .set PSL_EN_UNDFL,0x40 /* floating underflow enable */
52: .set PSL_DBL,0x80 /* dbl precision Accumulator bit */
53: .set PSL_IPL,0x001f0000 /* interrupt priority level */
54: .set PSL_MOD,0x01000000 /* mode = 1 means user */
55: .set PSL_IS,0x04000000 /* interrupt stack */
56: .set PSL_TP,0x40000000 /* trace pending */
57:
58: #
59: # TAHOE page table entry
60: #/
61: .set PG_V,0x8000000
62: .set PG_PROT,0x78000000
63: .set PG_M,0x04000000
64: .set PG_USED,0x02000000
65: .set PG_NC,0x01000000
66: .set PG_PFNUM,0x003fffff
67:
68: .set PG_NOACC,0
69: .set PG_KR,0x40000000
70: .set PG_KW,0x60000000
71: .set PG_URKR,0x50000000
72: .set PG_URKW,0x70000000
73: .set PG_UW,0x78000000
74:
75: #* PCB offsets & diagnostic extension to pcb */
76: #* PCB is at pcb0 */
77:
78:
79: .set PCB_SIZE, 24
80: .set PCB_KSP, 0
81: .set PCB_USP, 4
82: .set PCB_R0, 8
83: .set PCB_R1, 12
84: .set PCB_R2, 16
85: .set PCB_R3, 20
86: .set PCB_R4, 24
87: .set PCB_R5, 28
88: .set PCB_R6, 32
89: .set PCB_R7, 36
90: .set PCB_R8, 40
91: .set PCB_R9, 44
92: .set PCB_R10, 48
93: .set PCB_R11, 52
94: .set PCB_R12, 56
95: .set PCB_R13, 60
96: .set PCB_PC, 64
97: .set PCB_PSL, 68
98: .set PCB_P0BR, 72
99: .set PCB_P0LR, 76
100: .set PCB_P1BR, 80
101: .set PCB_P1LR, 84
102: .set PCB_P2BR, 88
103: .set PCB_P2LR, 92
104: .set PCB_ACCM, 96
105: .set PCB_ACCL, 100
106: #*
107: # Diagnostic pcb extension
108: #/
109: .set PCB_STAT, 104 /*process status,statistics,id,etc*/
110:
111:
112:
113: #* fundamental constants */
114:
115: #*
116: # fundamental constants of the implementation--
117: # cannot be changed easily.
118: #/
119:
120: .set NBPG,1024
121: .set PGOFSET,(NBPG-1) /* byte offset into page */
122: .set PGSHIFT,10 /* LOG2(NBPG) */
123: .set HIGH,0x1f
124:
125:
126: #* SCB offsets */
127: #* SCB is at scb */
128:
129: .set PFVEC,1*4 /*power fail */
130: .set PRVEC,2*4 /*power restore */
131: .set CLOCKVEC,7*4 /*hard clock vector */
132: .set CRVEC,0xa*4 /*console receive */
133: .set CXVEC,44 /*console transmit */
134: .set SIVEC1,0x1e*4 /*software int vec #1 */
135: /*for 2,3,..15, sub 4,8,.. 56 */
136: /*from SIVEC1 */
137: .set BEVEC,0x20*4 /*bus error */
138: .set SYSVEC,0x2b*4 /*system call (kcall) */
139: .set PINSTVEC,0x2c*4 /*privileged instruction fault */
140: .set PRIVSVEC,0x2c*4 /*privileged instruction fault */
141: .set ROVEC,0x2d*4 /*reserved operand fault */
142: .set RAVEC,0x2e*4 /*reserved addressing fault */
143: .set PROTVEC,0x2f*4 /*access control violation */
144: .set TRANS,0x30 /*translation fault vector */
145: .set TRANSVEC,0x30*4 /*translation fault vector */
146: .set KSPVEC,0x31*4 /*kernel stack not valid vector */
147: .set TRACEVEC,0x32*4 /*trace vector */
148: .set BPTVEC,0x33*4 /*break point fault */
149: .set ARITHVEC,0x34*4 /*arithmetic trap */
150: .set ALIGNVEC,0x35*4 /*alignment vector */
151: .set FPMVEC,0x37*4 /*fpp emulation vector */
152: .set IO14VEC,256 /*io vector, ipl #14 */
153: .set IO15VEC,320 /*io vector, ipl #15 */
154: .set IO16VEC,384 /*io vector, ipl #16 */
155: .set IO17VEC,448 /*io vector, ipl #17 */
156:
157: #* SPT (system page table) offsets */
158: #* SPT is at Sysmap */
159:
160: .set SCBPTE,8 /*system control block pte offset*/
161: .set BUFPTE,12 /*buffer pte offset */
162: .set ISPTE,16 /*interrupt stack page 0 */
163: .set IS1PTE,20 /*interrupt stack page 1 */
164: .set SPTPTE,20 /*system page table page 1 */
165: .set SPT1PTE,20 /*system page table page 2 */
166: .set IOMAPPTE,24 /*io map */
167: .set PCBPTE,28 /*process control blocks pte */
168: .set U0P0PTE,32 /*U0 p0pt pte */
169: .set U0P1PTE,36 /*U0 p1pt pte */
170: .set U0P2PTE,40 /*U0 p2pt pte */
171: .set U1P0PTE,44
172: .set U1P1PTE,48
173: .set U1P2PTE,52
174: .set U2P0PTE,56
175: .set U2P1PTE,60
176: .set U2P2PTE,64
177: .set U3P0PTE,68
178: .set U3P1PTE,72
179: .set U3P2PTE,76
180: .set U4P0PTE,80
181: .set U4P1PTE,84
182: .set U4P2PTE,88
183: .set U5P0PTE,92
184: .set U5P1PTE,96
185: .set U5P2PTE,100
186: .set U6P0PTE,104
187: .set U6P1PTE,108
188: .set U6P2PTE,112
189: .set U7P0PTE,116 /*U7 p0pt pte */
190: .set U7P1PTE,120 /*U7 p1pt pte */
191: .set U7P2PTE,124 /*U7 p2pt pte */
192: .set IOB0PTE,128 /*io buffer 0 pte */
193: .set IOB1PTE,132
194: .set IOB2PTE,136
195: .set IOB3PTE,140
196: .set IOB4PTE,144
197: .set IOB5PTE,148
198: .set IOB6PTE,152
199: .set IOB7PTE,156 /*io buffer 7 pte */
200:
201:
202: #* trap.h 4.6 81/03/03 */
203:
204: #*
205: #* Trap type values
206: #/
207:
208: .set RESADFLT,0 /* reserved addressing fault */
209: .set PRIVINFLT,1 /* privileged instruction fault */
210: .set RESOPFLT,2 /* reserved operand fault */
211: .set BPTFLT,3 /* bpt instruction fault */
212: .set ALIGNFLT,4 /* alignment fault */
213: .set SYSCALL,5 /* kcall instruction (syscall trap) */
214: .set ARITHTRAP,6 /* arithmetic trap */
215: .set PROTFLT,7 /* protection fault */
216: .set TRCTRAP,8 /* trace trap */
217: .set TRANSFLT,9 /* translation not valid fault */
218: .set DONE,255
219:
220: #
221: # Event codes
222: #
223: .set RTCLOCK_CODE,7 /* real time clock event */
224: .set RESOP_CODE,0x2d /* reserved operand fault */
225: .set RESAD_CODE,0x2e /* reserved address fault */
226: .set ARITH_CODE,0x34 /* arithmetic fault */
227: .set FPM_CODE,0x37 /* fpp emulation trap */
228: .set INTEGER_OVERFLOW,1 /* code for arith. fault */
229:
230: #
231: # Arithmetic Event types
232: #
233: .set INT_OVFL_CODE,1 /* integer overflow */
234: .set INT_0_DIV_CODE,2 /* integer divide by 0 */
235: .set FLT_0_DIV_CODE,3 /* floating divide by 0 */
236: .set FLT_OVFL_CODE,4 /* floating overflow */
237: .set FLT_UNDFL_CODE,5 /* floating underflow */
238:
239: #
240: # Floating Point Instruction Op-Codes
241: #
242: .set LDF_OP_CODE,0x06 /* sgl load acc. instr */
243: .set LDD_OP_CODE,0x07 /* dbl load acc. instr */
244: .set LNF_OP_CODE,0x16 /* sgl load-neg acc. instr */
245: .set LND_OP_CODE,0x17 /* dbl load-neg acc. instr */
246: .set STF_OP_CODE,0x26 /* sgl store acc. instr */
247: .set STD_OP_CODE,0x27 /* dbl store acc. instr */
248: .set CMPF_OP_CODE,0x36 /* sgl compare instr */
249: .set CMPD_OP_CODE,0x37 /* dbl compare instr */
250: .set CMPF2_OP_CODE,0x46 /* sgl compare 2 instr */
251: .set CMPD2_OP_CODE,0x47 /* dbl compare 2 instr */
252: .set TSTF_OP_CODE,0x56 /* sgl test acc. instr */
253: .set TSTD_OP_CODE,0x57 /* dbl test acc. instr */
254: .set PUSHD_OP_CODE,0x67 /* dbl push acc. instr */
255: .set CVLF_OP_CODE,0x76 /* convert int to sgl instr */
256: .set CVLD_OP_CODE,0x77 /* convert int to dbl instr */
257: .set CVFL_OP_CODE,0x86 /* convert sgl to int instr */
258: .set CVDL_OP_CODE,0x87 /* convert dbl to int instr */
259: .set LDFD_OP_CODE,0x97 /* load sgl to dbl instr */
260: .set CVDF_OP_CODE,0xa6 /* convert dbl to sgl instr */
261: .set NEGF_OP_CODE,0xb6 /* negate sgl acc. instr */
262: .set NEGD_OP_CODE,0xb7 /* negate dbl acc. instr */
263: .set ADDF_OP_CODE,0xc6 /* sgl add instr */
264: .set ADDD_OP_CODE,0xc7 /* dbl add instr */
265: .set SUBF_OP_CODE,0xd6 /* sgl subtract instr */
266: .set SUBD_OP_CODE,0xd7 /* dbl subtract instr */
267: .set MULF_OP_CODE,0xe6 /* sgl multiply instr */
268: .set MULD_OP_CODE,0xe7 /* dbl multiply instr */
269: .set DIVF_OP_CODE,0xf6 /* sgl divide instr */
270: .set DIVD_OP_CODE,0xf7 /* dbl divide instr */
271: .set SINF_OP_CODE,0x05 /* sgl sine instr */
272: .set COSF_OP_CODE,0x15 /* sgl cosine instr */
273: .set ATANF_OP_CODE,0x25 /* sgl arc-tangent instr */
274: .set LOGF_OP_CODE,0x35 /* sgl natural log instr */
275: .set SQRTF_OP_CODE,0x45 /* sgl square root instr */
276: .set EXPF_OP_CODE,0x55 /* sgl "e to the x" instr */
277: .set MULL2_OP_CODE,0x4c /* integer multiply - 2 ops */
278: .set MULL3_OP_CODE,0x5c /* integer multiply - 3 ops */
279:
280:
281: #
282: # Addressing test constants - These must agree with "fpp_defs.h"
283: #
284: .set ADR_ABSOLUTE,1 /* absolute address */
285: .set ADR_LITERAL,2 /* literal -short immediate byte */
286: .set ADR_IM_B,3 /* immediate byte */
287: .set ADR_IM_W,4 /* immediate word */
288: .set ADR_IM_L,5 /* immediate long-word */
289: .set ADR_B_DSP,6 /* byte displ relative */
290: .set ADR_W_DSP,7 /* word displ relative */
291: .set ADR_L_DSP,8 /* long-word displ relative */
292: .set ADR_B_DSP_DEF,9 /* byte displ relative deferred */
293: .set ADR_W_DSP_DEF,10 /* word displ relative deferred */
294: .set ADR_L_DSP_DEF,11 /* L-word displ relative deferred */
295: .set ADR_REG,12 /* direct register */
296: .set ADR_REG_DEF,13 /* register deferred */
297: .set ADR_FP_DEF,14 /* FP deferred */
298: .set ADR_SP_DEF,15 /* SP deferred */
299: .set ADR_PUSH,16 /* auto-decrement SP */
300: .set ADR_POP,17 /* auto-increment SP */
301: .set ADR_POP_DEF,18 /* auto-increment SP deferred */
302: .set ADR_REG_B,19 /* register + byte displ */
303: .set ADR_REG_W,20 /* register + word displ */
304: .set ADR_REG_L,21 /* register + long-word displ */
305: .set ADR_REG_B_DEF,22 /* register + byte displ deferred */
306: .set ADR_REG_W_DEF,23 /* register + word displ deferred */
307: .set ADR_REG_L_DEF,24 /* register + L-word displ deferred */
308: .set ADR_I_FP_DEF,25 /* indexed (frame pointer deferred) */
309: .set ADR_I_L,26 /* indexed (longword displacement) */
310:
311:
312: #*************************************************************************
313: #
314: # Stuff for the Demand Paging , Events, & Addressing Tests
315: #
316: #************************************************************************/
317: .set SGL,1 /* sgl precision data */
318: .set DBL,2 /* dbl precision data */
319: .set ENABLE_EVENTS,0x60 /* enable ovfl & undfl events */
320: .set NONE,0 /* no operand flag */
321: .set LOAD,1 /* read-the-operand flag */
322: .set STORE,2 /* store-the-operand flag */
323:
324: .set NO_EVT_HLT,1 /* halt code: did not Get event */
325: .set EVT_MSK_HLT,2 /* halt code: got masked event */
326: .set BAD_PSL_HLT,3 /* halt code: wrong PSL value */
327: .set PUSH_CNT_HLT,4 /* halt code: wrong # ops on stk */
328: .set PUSH_PSL_HLT,5 /* halt code: bad PSL on stack */
329: .set PUSH_PC_HLT,6 /* halt code: bad PC on stack */
330: .set BAD_REG_HLT,7 /* halt code: bad final register */
331: .set BAD_ACC_HLT,8 /* halt code: bad final Acc. */
332:
333: #
334: # set DMP_PG_0 to the 1st empty page
335: #
336: .set DMP_PG_0,0x36000
337: .set DMP_PG_1,DMP_PG_0+0x400
338: .set DMP_PG_2,DMP_PG_1+0x400
339: .set DMP_PG_3,DMP_PG_2+0x400
340: .set DMP_PG_4,DMP_PG_3+0x400
341: .set DMP_PG_5,DMP_PG_4+0x400
342: .set DMP_PG_6,DMP_PG_5+0x400
343: .set DMP_PG_7,DMP_PG_6+0x400
344: .set DMP_PG_8,DMP_PG_7+0x400
345: .set DMP_PG_9,DMP_PG_8+0x400
346: .set DMP_PG_10,DMP_PG_9+0x400
347: .set DMP_PG_11,DMP_PG_10+0x400
348: .set DMP_PG_12,DMP_PG_11+0x400
349: .set DMP_PG_13,DMP_PG_12+0x400
350:
351: #
352: # test code space for the address / demand page tests
353: #
354: .set START_OF_CODE,DMP_PG_1-20 /* 1st addr of test-code space */
355: .set CODE_BUF_SIZE,40 /* # bytes in test-code space */
356: .set END_OF_CODE,START_OF_CODE+CODE_BUF_SIZE
357:
358: #
359: # data locations used by the event and demand page tests
360: #
361: .set _dmp_byte_op_1,DMP_PG_1+0x30 /* 'byte offset' data */
362: .set _dmp_byte_op_2,DMP_PG_1+0x50 /* 'byte offset' data */
363: .set _dmp_byte_op_3,DMP_PG_1+0x70 /* 'byte offset' data */
364: .set _dmp_op_1,DMP_PG_3-4 /* 1st data word */
365: .set _dmp_op_1_ptr,DMP_PG_4+0x30 /* ptr to 1st data wd */
366: .set _dmp_op_2_ptr,DMP_PG_5+0x30 /* ptr to 2nd data wd */
367: .set _dmp_op_2,DMP_PG_7-4 /* 2nd data word */
368: .set _dmp_op_3,DMP_PG_8 /* 3rd data word */
369: .set _dmp_op_3_ptr,DMP_PG_9+0x30 /* ptr to 3rd data wd */
370: .set _dmp_op_4,DMP_PG_10 /* 4th data (for pipes) */
371: .set _dmp_op_5,DMP_PG_11 /* 5th data (for pipes) */
372: .set _sp_minus,DMP_PG_13-4 /* SP for POPs */
373: .set _sp_page,DMP_PG_13 /* SP page boundary */
374: .set _sp_plus,DMP_PG_13+4 /* SP for PUSHs */
375:
376:
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.