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1.1 ! root 1: ! 2: #include "dmp_defs.h" ! 3: ! 4: ! 5: /*********************************************************************** ! 6: * ! 7: * Verify double precision accumulator value ! 8: * ! 9: * This code will verify the final accumulator value. The assumption is ! 10: * made that the PSL will not be modified by the instruction (with the ! 11: * exception of the accumulator size bit with CVDF instructions). ! 12: * The convert DBL to SGL instruction will be tested here because it's ! 13: * easier, when an error occurrs, to do the printing here. ! 14: * The operand, if any will, be in dbl_value_1. ! 15: * ! 16: * The "no-fpp" firmware will not clear "bad 0" accumulators. ! 17: ***********************************************************************/ ! 18: chk_dbl_acc() ! 19: { ! 20: exp_psl = init_psl; /* get the initial PSL */ ! 21: exp_psl |= PSL_DBL; /* set PSL's DBL AC bit */ ! 22: if( op_code == PUSHD_OP_CODE ) { ! 23: exp_psl &= 0xfffffff1; /* strip off the flag bits */ ! 24: if( dbl_expected.m & 0x80000000 ) ! 25: exp_psl |= PSL_N; /* set the NEGATIVE bit */ ! 26: else if( !dbl_expected.m ) ! 27: exp_psl |= PSL_Z; /* set the ZERO bit */ ! 28: } ! 29: if( op_code == CVDF_OP_CODE ) { ! 30: dbl_st_acc.l = dbl_expected.l; ! 31: exp_psl &= 0xffffff7f; /* strip off PSL size bit */ ! 32: psl_val &= 0xffffff7f; ! 33: } ! 34: if( (dbl_st_acc.m != dbl_expected.m) || ! 35: (dbl_st_acc.l != dbl_expected.l) ) { /* check for bad result */ ! 36: errcnt++; ! 37: if( prt_error ) ! 38: prt_d_acc_e( bad_result_msg ); ! 39: if( halt_flg ) ! 40: hlt_d_acc_e( 1 ); /* error code 1 */ ! 41: if( loop_on_err ) ! 42: force_loop = TRUE; /* set loop flag */ ! 43: } ! 44: else if( psl_val != exp_psl ) { /* check for bad PSL */ ! 45: errcnt++; ! 46: if( prt_error ) ! 47: prt_d_acc_e( bad_psl_msg ); ! 48: if( halt_flg ) ! 49: hlt_d_acc_e( 2 ); /* error code 2 */ ! 50: if( loop_on_err ) ! 51: force_loop = TRUE; /* set loop flag */ ! 52: } ! 53: else if( no_page_faults != exp_page_faults ) { /* check # pg faults */ ! 54: errcnt++; ! 55: if( prt_error ) ! 56: prt_d_acc_e( trans_flt_cnt_msg ); ! 57: if( halt_flg ) ! 58: hlt_d_acc_e( 3 ); /* error code 3 */ ! 59: if( loop_on_err ) ! 60: force_loop = TRUE; /* set loop flag */ ! 61: } else { ! 62: reg_no = 0; ! 63: regs_ok = TRUE; ! 64: while( (reg_no <= 13) && (regs_ok) ) /* check 1st 13 regs */ ! 65: if( store_regs[ reg_no ] == exp_regs[ reg_no ] ) ! 66: reg_no++; ! 67: else ! 68: regs_ok = FALSE; ! 69: if( !regs_ok ) { /* check register values */ ! 70: errcnt++; ! 71: if( prt_error ) ! 72: prt_d_acc_e( reg_modified_msg ); ! 73: if( halt_flg ) ! 74: hlt_d_acc_e( 4 ); /* error code 4 */ ! 75: if( loop_on_err ) ! 76: force_loop = TRUE; /* set loop flag */ ! 77: } ! 78: } ! 79: } ! 80: ! 81: ! 82: /************************************************************************ ! 83: * PRINT AN ERROR MESSAGE OF THE FORM ! 84: * ! 85: * cycle: xx. DMP test xx. <inst>. <error message>, index = xx ! 86: * addressing mode: <addressing mode description> ! 87: * inst buf= xx xx xx xx xx xx xx xx xx xx xx -page faults on byte(s) 0, x ! 88: * init Acc = xxxxxxxx xxxxxxxx, final Acc = xxxxxxxx xxxxxxxx, xx pg faults ! 89: * operand = xxxxxxxx xxxxxxxx, expected = xxxxxxxx xxxxxxxx, xx expected ! 90: * initial PSL = xxxxxxxx, final PSL = xxxxxxxx, expected PSL = xxxxxxxx ! 91: ************************************************************************/ ! 92: prt_d_acc_e( message ) ! 93: char *message; ! 94: { ! 95: int sgl_operand; ! 96: if( (op_code == LDFD_OP_CODE) || (op_code == CVLD_OP_CODE) ) ! 97: sgl_operand = TRUE; ! 98: else ! 99: sgl_operand = FALSE; ! 100: prt_dmp_er_msg( message ); /* print the error header */ ! 101: writes("init Acc = "); ! 102: write32h( dbl_ld_acc.m ); /* print Acc. loaded data */ ! 103: writec(' '); ! 104: write32h( dbl_ld_acc.l ); ! 105: writes(", final Acc = "); ! 106: write32h( dbl_st_acc.m ); /* print Acc. stored data */ ! 107: if( op_code == CVDF_OP_CODE ) { ! 108: writes(", "); ! 109: } else { ! 110: writec(' '); ! 111: write32h( dbl_st_acc.l ); /* print the LS stored */ ! 112: writes(", "); ! 113: } ! 114: writed( no_page_faults ); /* print page fault data */ ! 115: writes(" pg faults\n"); ! 116: if( no_ops ) ! 117: { ! 118: writes(" operand = "); ! 119: write32h( dbl_value_1.m ); /* print MS part of operand */ ! 120: writec(' '); ! 121: if( sgl_operand ) ! 122: writes(" "); ! 123: else ! 124: write32h( dbl_value_1.l ); /* print LS part of operand */ ! 125: writec(','); ! 126: } ! 127: else ! 128: writes(" "); ! 129: writes(" expected = "); ! 130: write32h( dbl_expected.m ); ! 131: if( op_code == CVDF_OP_CODE ) { ! 132: writes(", "); ! 133: } else { ! 134: writec(' '); ! 135: write32h( dbl_expected.l ); ! 136: writes(", "); ! 137: } ! 138: writed( exp_page_faults ); ! 139: writes(" expected\n"); ! 140: if( message == bad_psl_msg ) { /* PSL was wrong */ ! 141: writes("initial PSL = "); ! 142: write32h( init_psl ); ! 143: writes(", final PSL = "); ! 144: write32h( psl_val ); ! 145: writes(", expected PSL = "); ! 146: write32h( exp_psl ); ! 147: writec('\n'); ! 148: } ! 149: if( message == reg_modified_msg ) /* print modified register */ ! 150: prt_reg_data(); /* print bad register */ ! 151: } ! 152: ! 153: ! 154: ! 155: /************************************************************************** ! 156: * Set up the registers and halt ! 157: **************************************************************************/ ! 158: hlt_d_acc_e( code ) ! 159: int code; ! 160: { ! 161: sgl_dummy1 = code; ! 162: asm("movl _test_no,r0"); /* r0 = test number */ ! 163: asm("movl _addr_code,r1"); /* r1 = addr mode code */ ! 164: asm("movl _sgl_dummy1,r2"); /* r2 = error code */ ! 165: asm("movl _cycle,r3"); /* r3 = cycle count */ ! 166: sgl_dummy1 = dbl_ld_acc.m; ! 167: sgl_dummy2 = dbl_ld_acc.l; ! 168: asm("movl _sgl_dummy1,r4"); /* r4 = initial Acc. */ ! 169: asm("movl _sgl_dummy2,r5"); ! 170: sgl_dummy1 = dbl_st_acc.m; ! 171: sgl_dummy2 = dbl_st_acc.l; ! 172: asm("movl _sgl_dummy1,r6"); /* r6 = final Accumulator */ ! 173: asm("movl _sgl_dummy2,r7"); ! 174: if( no_ops ) { ! 175: sgl_dummy1 = dbl_value_1.m; ! 176: sgl_dummy2 = dbl_value_1.l; ! 177: asm("movl _sgl_dummy1,r8"); /* r8 = operand */ ! 178: asm("movl _sgl_dummy2,r9");; ! 179: } else { ! 180: asm("clrl r8"); /* r8 = 0 */ ! 181: asm("clrl r9"); ! 182: } ! 183: if( code == 1 ) { /* data error */ ! 184: sgl_dummy1 = dbl_expected.m; ! 185: sgl_dummy2 = dbl_expected.l; ! 186: asm("movl _sgl_dummy1,r10"); /* r10 = expected results */ ! 187: asm("movl _sgl_dummy2,r11");; ! 188: } ! 189: else if( code == 2 ) { /* PSL error */ ! 190: asm("movl _init_psl,r10"); /* r10 = initial psl */ ! 191: asm("movl _psl_val,r11");; /* r11 = final psl value */ ! 192: asm("movl _init_psl,r12"); /* r12 = expected psl */ ! 193: } ! 194: else if( code == 3 ) { /* # faults error */ ! 195: asm("movl _no_page_faults,r10"); /* r10 = # page faults */ ! 196: asm("movl _exp_page_faults,r11");; /* r11 = # faults expected */ ! 197: } ! 198: else if( code == 4 ) { /* register error */ ! 199: asm("movl _reg_no,r10"); /* r10 = bad register # */ ! 200: asm("movl _store_regs[r10],r11"); /* r11 = final (bad) value */ ! 201: asm("movl _exp_regs[r10],r12");; /* r12 = expected value */ ! 202: } ! 203: asm(".globl _hlt_dbl_acc"); ! 204: asm("_hlt_dbl_acc:"); ! 205: asm("halt"); ! 206: } ! 207: ! 208:
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