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1.1 root 1:
2: #include "dmp_defs.h"
3:
4:
5: /***********************************************************************
6: *
7: * Verify results after a double precision TSTD or CMPD(2) instruction
8: *
9: * The final PSL value is compared to the expected value. Also, the
10: * final accumulator and the registers are checked to make sure that
11: * they weren't modified.
12: * The "no-fpp" firmware will not clear "bad 0" double precision accumulators.
13: ***********************************************************************/
14: chk_dbl_psl()
15: {
16: if( (dbl_ld_acc.m & 0x7f800000) || /* get the exp'd Acc */
17: (no_fpp_wcs) ) {
18: sgl_value_1 = dbl_ld_acc.m;
19: sgl_value_2 = dbl_ld_acc.l;
20: } else { /* zero accumulator */
21: sgl_value_1 = 0; /* clear any bad 0's */
22: sgl_value_2 = 0;
23: } /* end of "0" accumulator */
24: exp_psl = init_psl; /* get the initial PSL */
25: exp_psl &= 0xfffffff1; /* clear the flag bits */
26: exp_psl |= PSL_DBL; /* set the DBL Acc. bit */
27: exp_psl |= PSL_C; /* set the CARRY bit */
28: if( dbl_expected.m == ZERO )
29: exp_psl |= PSL_Z; /* expect the ZERO bit set */
30: if( dbl_expected.m == NEGATIVE )
31: exp_psl |= PSL_N; /* expect the NEG bit set */
32: if( psl_val != exp_psl ) {
33: errcnt++;
34: if( prt_error )
35: prt_d_psl_e( bad_psl_msg );
36: if( halt_flg )
37: hlt_d_psl_e( 2 ); /* error code 2 */
38: if( loop_on_err )
39: force_loop = TRUE; /* set loop flag */
40: }
41: else if( no_page_faults != exp_page_faults ) {
42: errcnt++;
43: if( prt_error )
44: prt_d_psl_e( trans_flt_cnt_msg );
45: if( halt_flg )
46: hlt_d_psl_e( 3 ); /* error code 3 */
47: if( loop_on_err )
48: force_loop = TRUE; /* set loop flag */
49: }
50: else if( (dbl_st_acc.m != sgl_value_1) || /* check final Acc. */
51: (dbl_st_acc.l != sgl_value_2) ) {
52: errcnt++;
53: if( prt_error )
54: prt_d_psl_e( acc_modified_msg );
55: if( halt_flg )
56: hlt_d_psl_e( 5 ); /* error code 5 */
57: if( loop_on_err )
58: force_loop = TRUE; /* set loop flag */
59: }
60: else {
61: reg_no = 0;
62: regs_ok = TRUE;
63: while( (reg_no <= 13) && (regs_ok) ) /* check 1st 13 regs */
64: if( store_regs[ reg_no ] == exp_regs[ reg_no ] )
65: reg_no++;
66: else
67: regs_ok = FALSE;
68: if( !regs_ok )
69: {
70: errcnt++;
71: if( prt_error )
72: prt_d_psl_e( reg_modified_msg );
73: if( halt_flg )
74: hlt_d_psl_e( 4 ); /* error code 4 */
75: if( loop_on_err )
76: force_loop = TRUE; /* set loop flag */
77: }
78: }
79: }
80:
81:
82:
83: /************************************************************************
84: * PRINT AN ERROR MESSAGE OF THE FORM
85: *
86: * cycle: xx. DMP test xx. <inst>. <error message>, index = xx
87: * addressing mode: <addressing mode description>
88: * inst buf= xx xx xx xx xx xx xx xx xx xx xx -page faults on byte(s) 0, x
89: * initial Acc = xxxxxxxx xxxxxxxx, operand1 = xxxxxxxx xxxxxxxx, xx pg faults
90: * final Acc = xxxxxxxx xxxxxxxx, operand2 = xxxxxxxx xxxxxxxx, xx expected
91: * initial PSL = xxxxxxxx, final PSL = xxxxxxxx, expected PSL = xxxxxxxx
92: ************************************************************************/
93: prt_d_psl_e( message )
94: char *message;
95: {
96: prt_dmp_er_msg( message ); /* print the error header */
97: writes("initial Acc = ");
98: write32h( dbl_ld_acc.m ); /* print Acc loaded */
99: writec(' ');
100: write32h( dbl_ld_acc.l );
101: if( no_ops ) {
102: writes(", operand1 = ");
103: write32h( dbl_value_1.m ); /* write op 1 data */
104: writec(' ');
105: write32h( dbl_value_1.l );
106: }
107: writes(", ");
108: writed( no_page_faults );
109: writes(" pg faults\n");
110: writes(" final Acc = "); /* write final ACC data */
111: write32h( dbl_st_acc.m );
112: writec(' ');
113: write32h( dbl_st_acc.l );
114: if( no_ops == 2 ) {
115: writes(", operand2 = ");
116: write32h( dbl_value_2.m ); /* write op 2 data */
117: writec(' ');
118: write32h( dbl_value_2.l );
119: }
120: if( no_ops )
121: writes(", ");
122: else
123: writes(", ");
124: writed( exp_page_faults );
125: writes(" expected\n");
126: writes("\ninitial PSL = "); /* print PSL data */
127: write32h( init_psl );
128: writes(", final PSL = ");
129: write32h( psl_val );
130: writes(", expected PSL = ");
131: write32h( exp_psl );
132: writec('\n');
133: if( message == reg_modified_msg ) /* print modified register */
134: prt_reg_data(); /* print bad register */
135: }
136:
137:
138:
139: /**************************************************************************
140: * Set up the registers and halt
141: **************************************************************************/
142: hlt_d_psl_e( code )
143: int code;
144: {
145: sgl_dummy1 = code;
146: asm("movl _test_no,r0"); /* r0 = test number */
147: asm("movl _addr_code,r1"); /* r1 = addressing mode */
148: asm("movl _sgl_dummy1,r2"); /* r2 = error code */
149: asm("movl _cycle,r3"); /* r3 = cycle count */
150: sgl_dummy1 = dbl_ld_acc.m;
151: sgl_dummy2 = dbl_ld_acc.l;
152: asm("movl _sgl_dummy1,r4"); /* r4 = MS of initial Acc */
153: asm("movl _sgl_dummy2,r5"); /* r5 = LS of initial Acc */
154: if( no_ops ) {
155: sgl_dummy1 = dbl_value_1.m;
156: sgl_dummy2 = dbl_value_1.m;
157: asm("movl _sgl_dummy1,r6"); /* r6 = MS of operand 1 */
158: asm("movl _sgl_dummy2,r7"); /* r7 = LS of operand 1 */
159: } else {
160: asm("clrl r6"); /* r6, r7 = 0 for TSTD */
161: asm("clrl r7");;
162: }
163: if( no_ops == 2 ) {
164: sgl_dummy1 = dbl_value_2.m;
165: sgl_dummy2 = dbl_value_2.m;
166: asm("movl _sgl_dummy1,r8"); /* r8 = MS of operand 2 */
167: asm("movl _sgl_dummy2,r9"); /* r9 = LS of operand 2 */
168: } else {
169: asm("clrl r8"); /* r8, r9 = 0 for TSTD,CMPD */
170: asm("clrl r9");;
171: }
172: if( code == 2 ) { /* wrong PSL */
173: asm("movl _init_psl,r10"); /* r10 = initial psl */
174: asm("movl _psl_val,r11"); /* r11 = final psl */
175: asm("movl _exp_psl,r12"); /* r12 = expected psl */
176: asm("movl _index,r13"); /* r13 = data index */
177: }
178: else if( code == 3 ) { /* wrong # page faults */
179: asm("movl _no_page_faults,r10"); /* r10 = # page faults */
180: asm("movl _exp_page_faults,r11"); /* r11 = # faults expected */
181: }
182: else if( code == 5 ) { /* corrupted accumulator */
183: sgl_dummy1 = dbl_st_acc.m;
184: sgl_dummy2 = dbl_st_acc.l;
185: asm("movl _sgl_dummy1,r10"); /* r10 = MS of final Acc. */
186: asm("movl _sgl_dummy2,r11"); /* r11 = LS of final Acc. */
187: }
188: else { /* corrupted register */
189: asm("movl _reg_no,r10"); /* r10 = bad register # */
190: asm("movl _store_regs[r9],r11"); /* r11 = final (bad) value */
191: asm("movl _exp_regs[r9],r12"); /* r12 = expected value */
192: }
193: asm(".globl _hlt_dbl_psl");
194: asm("_hlt_dbl_psl:");
195: asm("halt");
196: }
197:
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