Return to chk_dbl_psl.c CVS log

Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / dmp4

Power 6/32 Unix version 1.21

#include "dmp_defs.h"


/***********************************************************************
*
*   Verify results after a double precision TSTD or CMPD(2) instruction
*
*  The final PSL value is compared to the expected value. Also, the
*  final accumulator and the registers are checked to make sure that 
*  they weren't modified.
*  The "no-fpp" firmware will not clear "bad 0" double precision accumulators.
***********************************************************************/
chk_dbl_psl()
{
	if( (dbl_ld_acc.m & 0x7f800000) ||	/* get the exp'd Acc */
	    (no_fpp_wcs) ) {
	     sgl_value_1 = dbl_ld_acc.m;
	     sgl_value_2 = dbl_ld_acc.l;
	} else {				/* zero accumulator */
	     sgl_value_1 = 0;		/* clear any bad 0's */
	     sgl_value_2 = 0;
	}  /* end of "0" accumulator */
	exp_psl = init_psl;			/* get the initial PSL      */
	exp_psl &= 0xfffffff1;			/* clear the flag bits      */
	exp_psl |= PSL_DBL;			/* set the DBL Acc. bit     */
	exp_psl |= PSL_C;			/* set the CARRY bit        */
	if( dbl_expected.m == ZERO )
	    exp_psl |= PSL_Z;			/* expect the ZERO bit set  */
	if( dbl_expected.m == NEGATIVE )
	    exp_psl |= PSL_N;			/* expect the NEG bit set   */
	if( psl_val != exp_psl ) {
	    errcnt++;
	    if( prt_error )
		 prt_d_psl_e( bad_psl_msg );
	    if( halt_flg )
		 hlt_d_psl_e( 2 );		/* error code 2 */
	    if( loop_on_err )
		 force_loop = TRUE;		/* set loop flag */
	}
	 else if( no_page_faults != exp_page_faults ) {
	    errcnt++;
	    if( prt_error )
		 prt_d_psl_e( trans_flt_cnt_msg );
	    if( halt_flg )
		 hlt_d_psl_e( 3 );		/* error code 3 */
	    if( loop_on_err )
		 force_loop = TRUE;		/* set loop flag */
	}
	 else if( (dbl_st_acc.m != sgl_value_1) ||  /* check final Acc. */
	          (dbl_st_acc.l != sgl_value_2) ) {
	    errcnt++;
	    if( prt_error )
		 prt_d_psl_e( acc_modified_msg );
	    if( halt_flg )
		 hlt_d_psl_e( 5 );		/* error code 5 */
	    if( loop_on_err )
		 force_loop = TRUE;		/* set loop flag */
	}
	 else {
	    reg_no = 0;
	    regs_ok = TRUE;
	    while( (reg_no <= 13) && (regs_ok) )  /* check 1st 13 regs */
		if( store_regs[ reg_no ] == exp_regs[ reg_no ] )
		    reg_no++;
		else
		    regs_ok = FALSE;
	    if( !regs_ok )
	    {
	        errcnt++;
	        if( prt_error )
		     prt_d_psl_e( reg_modified_msg );
	        if( halt_flg )
		     hlt_d_psl_e( 4 );		/* error code 4 */
	        if( loop_on_err )
		     force_loop = TRUE;		/* set loop flag */
	    }
	} 
}



/************************************************************************
*		PRINT AN ERROR MESSAGE OF THE FORM
*
* cycle: xx. DMP test xx. <inst>. <error message>, index = xx
* addressing mode: <addressing mode description>
* inst buf= xx xx xx xx xx xx xx xx xx xx xx -page faults on byte(s) 0, x 
* initial Acc = xxxxxxxx xxxxxxxx,  operand1 = xxxxxxxx xxxxxxxx,  xx pg faults
*   final Acc = xxxxxxxx xxxxxxxx,  operand2 = xxxxxxxx xxxxxxxx,  xx expected
* initial PSL = xxxxxxxx,   final PSL = xxxxxxxx,  expected PSL = xxxxxxxx
************************************************************************/
prt_d_psl_e( message )
char *message;
{
	prt_dmp_er_msg( message );		/* print the error header */
	writes("initial Acc = ");
	write32h( dbl_ld_acc.m );		/* print Acc loaded */
	writec(' ');
	write32h( dbl_ld_acc.l );
	if( no_ops ) {
	    writes(",  operand1 = ");
	    write32h( dbl_value_1.m );		/* write op 1 data */
	    writec(' ');
	    write32h( dbl_value_1.l );
	}
	writes(",  ");
	writed( no_page_faults );
	writes(" pg faults\n");
	writes("  final Acc = ");		/* write final ACC data */
	write32h( dbl_st_acc.m );
	writec(' ');
	write32h( dbl_st_acc.l );
	if( no_ops == 2 ) {
	    writes(",  operand2 = ");
	    write32h( dbl_value_2.m );		/* write op 2 data */
	    writec(' ');
	    write32h( dbl_value_2.l );
	}
	if( no_ops )
	    writes(",                                 ");
	else
	    writes(",  ");
	writed( exp_page_faults );
	writes(" expected\n");
	writes("\ninitial PSL = ");		/* print PSL data */
	write32h( init_psl );
	writes(",   final PSL = ");
	write32h( psl_val );
	writes(",  expected PSL = ");
	write32h( exp_psl );
	writec('\n');
	if( message == reg_modified_msg )	/* print modified register */
	    prt_reg_data();			/* print bad register      */
}



/**************************************************************************
*	Set up the registers and halt
**************************************************************************/
hlt_d_psl_e( code )
int code;
{
	sgl_dummy1 = code;
	asm("movl _test_no,r0");		/* r0  = test number       */
	asm("movl _addr_code,r1");		/* r1  = addressing mode   */
	asm("movl _sgl_dummy1,r2");		/* r2  = error code        */
	asm("movl _cycle,r3");			/* r3  = cycle count       */
	sgl_dummy1 = dbl_ld_acc.m;
	sgl_dummy2 = dbl_ld_acc.l;
	asm("movl _sgl_dummy1,r4");		/* r4  = MS of initial Acc */
	asm("movl _sgl_dummy2,r5");		/* r5  = LS of initial Acc */
	if( no_ops ) {
	    sgl_dummy1 = dbl_value_1.m;
	    sgl_dummy2 = dbl_value_1.m;
	    asm("movl _sgl_dummy1,r6");		/* r6  = MS of operand 1   */
	    asm("movl _sgl_dummy2,r7");		/* r7  = LS of operand 1   */
	} else {
	    asm("clrl r6");			/* r6, r7 = 0 for TSTD     */
	    asm("clrl r7");;
	}
	if( no_ops ==  2 ) {
	    sgl_dummy1 = dbl_value_2.m;
	    sgl_dummy2 = dbl_value_2.m;
	    asm("movl _sgl_dummy1,r8");		/* r8  = MS of operand 2   */
	    asm("movl _sgl_dummy2,r9");		/* r9  = LS of operand 2   */
	} else {
	    asm("clrl r8");			/* r8, r9 = 0 for TSTD,CMPD */
	    asm("clrl r9");;
	}
	if( code == 2 ) {  /* wrong PSL */
	    asm("movl _init_psl,r10");		/* r10 = initial psl       */
	    asm("movl _psl_val,r11");		/* r11 = final psl         */
	    asm("movl _exp_psl,r12");		/* r12 = expected psl      */
	    asm("movl _index,r13");		/* r13 = data index        */
	}
	 else if( code == 3 ) {  /* wrong # page faults */
	    asm("movl _no_page_faults,r10");	/* r10 = # page faults     */
	    asm("movl _exp_page_faults,r11");	/* r11 = # faults expected */
	}
	 else if( code == 5 ) {	/* corrupted accumulator */
	    sgl_dummy1 = dbl_st_acc.m;
	    sgl_dummy2 = dbl_st_acc.l;
	    asm("movl _sgl_dummy1,r10");	/* r10 = MS of final Acc.  */
	    asm("movl _sgl_dummy2,r11");	/* r11 = LS of final Acc.  */
	}
	else  {			/* corrupted register */
	    asm("movl _reg_no,r10");		/* r10 = bad register #    */
	    asm("movl _store_regs[r9],r11");	/* r11 = final (bad) value */
	    asm("movl _exp_regs[r9],r12");	/* r12 = expected value    */
	}
	asm(".globl _hlt_dbl_psl");
	asm("_hlt_dbl_psl:");
	asm("halt");
}

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