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1.1 ! root 1: ! 2: #include "dmp_defs.h" ! 3: ! 4: /*********************************************************************** ! 5: * ! 6: * Verify double precision results for a store type operation ! 7: * ! 8: * The operand is in dbl_value_3. This test assumes that the flag bits ! 9: * of the PSL will be set by the operation. This test also assumes that ! 10: * the accumulator shouldn't be changed by the operation. ! 11: * The "no-fpp" firmware will not clear double precison "bad 0" accumulators. ! 12: ***********************************************************************/ ! 13: chk_dbl_s() ! 14: { ! 15: if( (dbl_ld_acc.m & 0x7f800000) || (no_fpp_wcs) ) { ! 16: sgl_value_1 = dbl_ld_acc.m; ! 17: sgl_value_2 = dbl_ld_acc.l; ! 18: } else { /* zero accumulator */ ! 19: sgl_value_1 = 0; ! 20: sgl_value_2 = 0; ! 21: } ! 22: if( op_code == CVDL_OP_CODE ) ! 23: dbl_value_3.l = dbl_expected.l; /* correct for sgl store */ ! 24: exp_psl = init_psl & 0xfffffff1; /* clear PSL flag bits */ ! 25: exp_psl |= PSL_DBL; /* set the DBL Acc. bit */ ! 26: exp_psl |= PSL_C; /* set the CARRY bit */ ! 27: if( dbl_expected.m & 0x80000000 ) ! 28: exp_psl |= PSL_N; /* set the NEGATIVE bit */ ! 29: else if( !dbl_expected.m ) ! 30: exp_psl |= PSL_Z; /* set the ZERO bit */ ! 31: /* */ ! 32: if( (dbl_value_3.m != dbl_expected.m) || /* check the stored value */ ! 33: (dbl_value_3.l != dbl_expected.l) ) ! 34: { ! 35: errcnt++; ! 36: if( prt_error ) ! 37: prt_d_st_e( bad_result_msg ); ! 38: if( halt_flg ) ! 39: hlt_d_st_e( 1 ); /* error code 1 */ ! 40: if( loop_on_err ) ! 41: force_loop = TRUE; /* set loop flag */ ! 42: } ! 43: else if( (psl_val != exp_psl) && (!no_fpp_wcs) ) { ! 44: errcnt++; ! 45: if( prt_error ) ! 46: prt_d_st_e( bad_psl_msg ); ! 47: if( halt_flg ) ! 48: hlt_d_st_e( 2 ); /* error code 2 */ ! 49: if( loop_on_err ) ! 50: force_loop = TRUE; /* set loop flag */ ! 51: } ! 52: else if( no_page_faults != exp_page_faults ) { ! 53: errcnt++; ! 54: if( prt_error ) ! 55: prt_d_st_e( trans_flt_cnt_msg ); ! 56: if( halt_flg ) ! 57: hlt_d_st_e( 3 ); /* error code 3 */ ! 58: if( loop_on_err ) ! 59: force_loop = TRUE; /* set loop flag */ ! 60: } ! 61: else if( (dbl_st_acc.m != sgl_value_1) || ! 62: (dbl_st_acc.l != sgl_value_2) ) { ! 63: errcnt++; ! 64: if( prt_error ) ! 65: prt_d_st_e( acc_modified_msg ); ! 66: if( halt_flg ) ! 67: hlt_d_st_e( 5 ); /* error code 5 */ ! 68: if( loop_on_err ) ! 69: force_loop = TRUE; /* set loop flag */ ! 70: } ! 71: else { ! 72: reg_no = 0; ! 73: regs_ok = TRUE; ! 74: while( (reg_no <= 13) && (regs_ok) ) /* check 1st 13 regs */ ! 75: if( store_regs[ reg_no ] == exp_regs[ reg_no ] ) ! 76: reg_no++; ! 77: else ! 78: regs_ok = FALSE; ! 79: if( !regs_ok ) { ! 80: errcnt++; ! 81: if( prt_error ) ! 82: prt_d_st_e( reg_modified_msg ); ! 83: if( halt_flg ) ! 84: hlt_d_st_e( 4 ); /* error code 4 */ ! 85: if( loop_on_err ) ! 86: force_loop = TRUE; /* set loop flag */ ! 87: } ! 88: } ! 89: } ! 90: ! 91: ! 92: ! 93: /************************************************************************ ! 94: * PRINT AN ERROR MESSAGE OF THE FORM ! 95: * ! 96: * cycle: xx. DMP test xx. <inst>. <error message>, index = xx ! 97: * addressing mode: <addressing mode description> ! 98: * inst buf= xx xx xx xx xx xx xx xx xx xx xx -page faults on byte(s) 0, x ! 99: * initial Acc = xxxxxxxx xxxxxxxx, stored = xxxxxxxx xxxxxxxx, xx pg faults ! 100: * final Acc = xxxxxxxx xxxxxxxx, expected = xxxxxxxx xxxxxxxx, xx expected ! 101: * expected Acc = xxxxxxxx xxxxxxxx ! 102: ************************************************************************/ ! 103: prt_d_st_e( message ) ! 104: char *message; ! 105: { ! 106: prt_dmp_er_msg( message ); /* print the error header */ ! 107: writes(" initial Acc = "); ! 108: write32h( dbl_ld_acc.m ); /* print accumulator data */ ! 109: writec(' '); ! 110: write32h( dbl_ld_acc.l ); ! 111: writes(", stored = "); ! 112: write32h( dbl_value_3.m ); /* print the final result */ ! 113: if( op_code == CVDL_OP_CODE ) ! 114: writes(", "); ! 115: else { ! 116: writec(' '); ! 117: write32h( dbl_value_3.l ); /* print LS stored */ ! 118: writes(", "); ! 119: } ! 120: writed( no_page_faults ); /* print page fault data */ ! 121: writes(" pg faults\n"); ! 122: writes(" final Acc = "); /* print final Acc value */ ! 123: write32h( dbl_st_acc.m ); ! 124: writec(' '); ! 125: write32h( dbl_st_acc.l ); ! 126: writes(", expected = "); /* print expected result */ ! 127: write32h( dbl_expected.m ); ! 128: if( op_code == CVDL_OP_CODE ) ! 129: writes(", "); /* longword store only */ ! 130: else { ! 131: writec(' '); /* print LS of the */ ! 132: write32h( dbl_expected.l ); /* quadword store */ ! 133: writes(", "); ! 134: } ! 135: writed( exp_page_faults ); /* print exp # page faults */ ! 136: writes(" expected\n"); ! 137: if( message == acc_modified_msg ) { /* print acc expected */ ! 138: writes("expected Acc = "); ! 139: write32h( sgl_value_1 ); /* print the expected Acc */ ! 140: writec(' '); ! 141: write32h( sgl_value_2 ); ! 142: } ! 143: if( message == bad_psl_msg ) { /* print PSL data */ ! 144: writes("initial PSL = "); ! 145: write32h( init_psl ); ! 146: writes(", final PSL = "); ! 147: write32h( psl_val ); ! 148: writes(", expected PSL = "); ! 149: write32h( exp_psl ); ! 150: } ! 151: writec('\n'); ! 152: if( message == reg_modified_msg ) /* print modified register */ ! 153: prt_reg_data(); /* print bad register */ ! 154: } ! 155: ! 156: ! 157: ! 158: /************************************************************************** ! 159: * Set up the registers and halt ! 160: **************************************************************************/ ! 161: hlt_d_st_e( code ) ! 162: int code; ! 163: { ! 164: int dbl_operand; ! 165: if( op_code == CVDL_OP_CODE ) ! 166: dbl_operand = FALSE; ! 167: else ! 168: dbl_operand = TRUE; ! 169: sgl_dummy1 = code; ! 170: asm("movl _test_no,r0"); /* r0 = test number */ ! 171: asm("movl _addr_code,r1"); /* r1 = addressing mode */ ! 172: asm("movl _sgl_dummy1,r2"); /* r2 = error code */ ! 173: asm("movl _cycle,r3"); /* r3 = cycle count */ ! 174: sgl_dummy1 = dbl_ld_acc.m; ! 175: sgl_dummy2 = dbl_ld_acc.l; ! 176: asm("movl _sgl_dummy1,r4"); /* r4 = MS of initial Acc */ ! 177: asm("movl _sgl_dummy2,r5"); /* r5 = LS of initial Acc */ ! 178: sgl_dummy1 = dbl_value_3.m; ! 179: sgl_dummy2 = dbl_value_3.l; ! 180: asm("movl _sgl_dummy1,r6"); /* r4 = MS of stored data */ ! 181: if( dbl_operand ) ! 182: asm("movl _sgl_dummy2,r7"); /* r7 = LS of stored data */ ! 183: else ! 184: asm("clrl r7");; ! 185: if( code == 1 ) { /* bad data stored */ ! 186: sgl_dummy1 = dbl_expected.m; ! 187: sgl_dummy2 = dbl_expected.l; ! 188: asm("movl _sgl_dummy1,r8"); /* r8 = MS of expected */ ! 189: asm("movl _sgl_dummy2,r9"); /* r9 = LS of expected */ ! 190: } ! 191: else if( code == 2 ) { /* bad final PSL */ ! 192: asm("movl _init_psl,r8"); /* r8 = initial psl */ ! 193: asm("movl _psl_val,r9"); /* r9 = final psl */ ! 194: asm("movl _exp_psl,r10"); /* r10 = expected psl */ ! 195: } ! 196: else if( code == 3 ) { /* wrong # page faults */ ! 197: asm("movl _no_page_faults,r8"); /* r8 = # page faults */ ! 198: asm("movl _exp_page_faults,r9"); /* r9 = # faults expected */ ! 199: } ! 200: else if( code == 4 ) { /* corrupted accumulator */ ! 201: asm("movl _dbl_expected,r8"); /* r8 = MS expected Acc */ ! 202: asm("movl _dbl_expected+4,r9"); /* r9 = LS expected Acc */ ! 203: } ! 204: else { /* register corrupted */ ! 205: asm("movl _reg_no,r8"); /* r8 = bad register # */ ! 206: asm("movl _store_regs[r8],r9"); /* r9 = final (bad) value */ ! 207: asm("movl _exp_regs[r8],r10"); /* r10 = expected value */ ! 208: } ! 209: asm(".globl _hlt_dbl_st"); ! 210: asm("_hlt_dbl_st:"); ! 211: asm("halt"); ! 212: } ! 213:
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