Return to chk_dbl_store.c CVS log

Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / dmp4

Power 6/32 Unix version 1.21

#include "dmp_defs.h"

/***********************************************************************
*
*	Verify double precision results for a store type operation
*
*  The operand is in dbl_value_3. This test assumes that the flag bits
*  of the PSL will be set by the operation. This test also assumes that
*  the accumulator shouldn't be changed by the operation.
*  The "no-fpp" firmware will not clear double precison "bad 0" accumulators.
***********************************************************************/
chk_dbl_s()
{
	if( (dbl_ld_acc.m & 0x7f800000) || (no_fpp_wcs) ) {	
	     sgl_value_1 = dbl_ld_acc.m;
	     sgl_value_2 = dbl_ld_acc.l;
	} else {				/* zero accumulator */
	     sgl_value_1 = 0;
	     sgl_value_2 = 0;
	}
	if( op_code == CVDL_OP_CODE )
	     dbl_value_3.l = dbl_expected.l;	/* correct for sgl store */
	exp_psl = init_psl & 0xfffffff1;	/* clear PSL flag bits   */
	exp_psl |= PSL_DBL;			/* set the DBL Acc. bit  */
	exp_psl |= PSL_C;			/* set the CARRY bit     */
	if( dbl_expected.m & 0x80000000 )
	     exp_psl |= PSL_N;			/* set the NEGATIVE bit  */
	else if( !dbl_expected.m )
	     exp_psl |= PSL_Z;			/* set the ZERO bit      */
/* */
	if( (dbl_value_3.m != dbl_expected.m) || /* check the stored value */
	    (dbl_value_3.l != dbl_expected.l) )
	{
	    errcnt++;
	    if( prt_error )
		 prt_d_st_e( bad_result_msg );
	    if( halt_flg )
		 hlt_d_st_e( 1 );		/* error code 1 */
	    if( loop_on_err )
		 force_loop = TRUE;		/* set loop flag */
	}
	 else if( (psl_val != exp_psl) && (!no_fpp_wcs) ) {
	    errcnt++;
	    if( prt_error )
		 prt_d_st_e( bad_psl_msg );
	    if( halt_flg )
		 hlt_d_st_e( 2 );		/* error code 2 */
	    if( loop_on_err )
		 force_loop = TRUE;		/* set loop flag */
	}
	 else if( no_page_faults != exp_page_faults ) {
	    errcnt++;
	    if( prt_error )
		 prt_d_st_e( trans_flt_cnt_msg );
	    if( halt_flg )
		 hlt_d_st_e( 3 );		/* error code 3 */
	    if( loop_on_err )
		 force_loop = TRUE;		/* set loop flag */
	}
	 else if( (dbl_st_acc.m != sgl_value_1) ||
	          (dbl_st_acc.l != sgl_value_2) ) {
	    errcnt++;
	    if( prt_error )
		 prt_d_st_e( acc_modified_msg );
	    if( halt_flg )
		 hlt_d_st_e( 5 );		/* error code 5 */
	    if( loop_on_err )
		 force_loop = TRUE;		/* set loop flag */
	}
	 else {
	    reg_no = 0;
	    regs_ok = TRUE;
	    while( (reg_no <= 13) && (regs_ok) )  /* check 1st 13 regs */
		if( store_regs[ reg_no ] == exp_regs[ reg_no ] )
		    reg_no++;
		else
		    regs_ok = FALSE;
	    if( !regs_ok ) {
	        errcnt++;
	        if( prt_error )
		     prt_d_st_e( reg_modified_msg );
	        if( halt_flg )
		     hlt_d_st_e( 4 );		/* error code 4 */
	        if( loop_on_err )
		     force_loop = TRUE;		/* set loop flag */
	    }
	} 
}



/************************************************************************
*		PRINT AN ERROR MESSAGE OF THE FORM
*
* cycle: xx. DMP test xx. <inst>. <error message>, index = xx
* addressing mode: <addressing mode description>
* inst buf= xx xx xx xx xx xx xx xx xx xx xx -page faults on byte(s) 0, x 
*  initial Acc = xxxxxxxx xxxxxxxx,   stored = xxxxxxxx xxxxxxxx,   xx pg faults
*    final Acc = xxxxxxxx xxxxxxxx, expected = xxxxxxxx xxxxxxxx,   xx expected
* expected Acc = xxxxxxxx xxxxxxxx
************************************************************************/
prt_d_st_e( message )
char *message;
{
	prt_dmp_er_msg( message );		/* print the error header */
	writes(" initial Acc = ");
	write32h( dbl_ld_acc.m );		/* print accumulator data */
	writec(' ');
	write32h( dbl_ld_acc.l );
	writes(",    stored = ");
	write32h( dbl_value_3.m );		/* print the final result */
	if( op_code == CVDL_OP_CODE )
	     writes(",            ");
	 else {
	     writec(' ');
	     write32h( dbl_value_3.l );		/* print LS stored */
	     writes(",   ");
	}
	writed( no_page_faults );		/* print page fault data */
	writes(" pg faults\n");
	writes("   final Acc = ");		/* print final Acc value */
	write32h( dbl_st_acc.m );
	writec(' ');
	write32h( dbl_st_acc.l );
	writes(",  expected = ");		/* print expected result */
	write32h( dbl_expected.m );
	if( op_code == CVDL_OP_CODE ) 
	     writes(",            ");		/* longword store only */
	else {
	     writec(' ');			/* print LS of the  */
	     write32h( dbl_expected.l );	/*   quadword store */
	     writes(",   ");
	}
	writed( exp_page_faults );		/* print exp # page faults */
	writes(" expected\n");
	if( message == acc_modified_msg ) {	/* print acc expected */
	     writes("expected Acc = ");
	     write32h( sgl_value_1 );		/* print the expected Acc */
	     writec(' ');
	     write32h( sgl_value_2 );
	}
	if( message == bad_psl_msg ) {		/* print PSL data */
	     writes("initial PSL = ");
	     write32h( init_psl );
	     writes(",   final PSL = ");
	     write32h( psl_val );
	     writes(",   expected PSL = ");
	     write32h( exp_psl );
	}
	writec('\n');
	if( message == reg_modified_msg )	/* print modified register */
	    prt_reg_data();			/* print bad register      */
}



/**************************************************************************
*	Set up the registers and halt
**************************************************************************/
hlt_d_st_e( code )
int code;
{
int dbl_operand;
	if( op_code == CVDL_OP_CODE )
	     dbl_operand = FALSE;
	else
	     dbl_operand = TRUE;
	sgl_dummy1 = code;
	asm("movl _test_no,r0");		/* r0  = test number       */
	asm("movl _addr_code,r1");		/* r1  = addressing mode   */
	asm("movl _sgl_dummy1,r2");		/* r2  = error code        */
	asm("movl _cycle,r3");			/* r3  = cycle count       */
	sgl_dummy1 = dbl_ld_acc.m;
	sgl_dummy2 = dbl_ld_acc.l;
	asm("movl _sgl_dummy1,r4");		/* r4  = MS of initial Acc */
	asm("movl _sgl_dummy2,r5");		/* r5  = LS of initial Acc */
	sgl_dummy1 = dbl_value_3.m;
	sgl_dummy2 = dbl_value_3.l;
	asm("movl _sgl_dummy1,r6");		/* r4  = MS of stored data */
	if( dbl_operand )
	     asm("movl _sgl_dummy2,r7");	/* r7  = LS of stored data */
	else
	     asm("clrl r7");;
	if( code == 1 ) {	/* bad data stored */
	     sgl_dummy1 = dbl_expected.m;
	     sgl_dummy2 = dbl_expected.l;
	     asm("movl _sgl_dummy1,r8");	/* r8  = MS of expected    */
	     asm("movl _sgl_dummy2,r9");	/* r9  = LS of expected    */
	}
	 else if( code == 2 ) {	/* bad final PSL */
	    asm("movl _init_psl,r8");		/* r8  = initial psl       */
	    asm("movl _psl_val,r9");		/* r9  = final psl         */
	    asm("movl _exp_psl,r10");		/* r10 = expected psl      */
	}
	 else if( code == 3 ) {	/* wrong # page faults */
	    asm("movl _no_page_faults,r8");	/* r8  = # page faults     */
	    asm("movl _exp_page_faults,r9");	/* r9  = # faults expected */
	}
	 else if( code == 4 ) {	/* corrupted accumulator */
	    asm("movl _dbl_expected,r8");	/* r8  = MS expected Acc   */
	    asm("movl _dbl_expected+4,r9");	/* r9  = LS expected Acc   */
	}
	else {			/* register corrupted */
	    asm("movl _reg_no,r8");		/* r8  = bad register #    */
	    asm("movl _store_regs[r8],r9");	/* r9  = final (bad) value */
	    asm("movl _exp_regs[r8],r10");	/* r10 = expected value    */
	}
	asm(".globl _hlt_dbl_st");
	asm("_hlt_dbl_st:");
	asm("halt");
}

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