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Return to chk_fpm_trap.c CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / dmp4 |
1.1 root 1:
2: #include "dmp_defs.h"
3:
4: /**********************************************************************
5: *
6: * Check the results of an FPP Emulation Trap (FPM)
7: *
8: * This code will verify:
9: * - the data pushed onto the stack by the trap
10: * - the PSL saved after the event
11: * - the number of page faults
12: * - the final accumulator value
13: * - the register values
14: *
15: **********************************************************************/
16: chk_fpm_trap()
17: {
18: error = FALSE;
19: if( !fpm_trap_occurred ) { /* Did we get an FPM trap? */
20: error = TRUE;
21: errcnt++;
22: if( prt_error )
23: prt_no_fpm_trap(); /* print an error message */
24: if( halt_flg )
25: fpm_halt( 7 ); /* halt with code = 7 */
26: if( loop_on_err )
27: force_loop = TRUE;
28: }
29: else { /* got trap -check the results */
30: chk_fpm_data(); /* check data pushed on stack */
31: if( !error )
32: chk_fpm_faults(); /* check # of page faults */
33: if( !error )
34: chk_final_acc(); /* check final Acc value */
35: if( !error )
36: chk_fpm_regs(); /* check final REG values */
37: }
38: }
39:
40:
41:
42: /****************************************************************************
43: *
44: * Check the results of an FPP Emulation Trap.
45: *
46: * Check the stack data, the final accumulator, and the registers. The data
47: * was saved by the FPM trap handler.
48: * The stack data is:
49: * - the PSL
50: * - the PC of the next instruction
51: * - the op-code
52: * - the operand's LS longword { for double precision instructions }
53: * - the operand's MS longword
54: *
55: ****************************************************************************/
56: chk_fpm_data()
57: {
58: exp_pc = code_addr + inst_size; /* expected PC on stack */
59: /*
60: * check the FPM variables pushed onto the stack
61: */
62: if( !no_ops ) {
63: dbl_value_1.m = fpm_ms_op; /* accept anything for the */
64: dbl_value_1.l = fpm_ls_op; /* operand if no operands */
65: }
66: if( (fpm_ms_op != dbl_value_1.m) ||
67: ((fpm_ls_op != dbl_value_1.l) && (precision == DBL) && (!s_to_d)) ||
68: (fpm_op_code != op_code) ||
69: (fpm_pc != exp_pc) ||
70: (fpm_psl != init_psl) ) {
71: error = TRUE;
72: errcnt++;
73: if( prt_error )
74: prt_fpm_stack_er();
75: if( halt_flg )
76: fpm_halt( 8 ); /* halt on the error */
77: if( loop_on_err )
78: force_loop = TRUE; /* set loop flag */
79: }
80: }
81:
82:
83: /****************************************************************************
84: *
85: * Check the number of page faults that were generated
86: *
87: ****************************************************************************/
88: chk_fpm_faults()
89: {
90: if( no_page_faults != exp_page_faults ) {
91: error = TRUE;
92: errcnt++;
93: if( prt_error ) {
94: prt_dmp_er_msg( trans_flt_cnt_msg );
95: writed( no_page_faults);
96: writes(" occurred\n");
97: writed( exp_page_faults);
98: writes(" were expected\n");
99: prt_reg_data(); /* print the bad register */
100: }
101: if( halt_flg )
102: fpm_halt( 3 ); /* halt on the error */
103: if( loop_on_err )
104: force_loop = TRUE; /* set loop flag */
105: }
106: }
107:
108:
109:
110: /****************************************************************************
111: *
112: * Check the final Accumulator value
113: *
114: * The "no-fpp" firmware will not clear "bad 0" accumulators if the
115: * MS of the operand loaded has any bits set. The LS will be cleared if
116: * the MS is already all 0's.
117: *
118: ****************************************************************************/
119: chk_final_acc()
120: {
121: if( dbl_ld_acc.m & 0x7f800000 ) { /* get final ACC expected */
122: dbl_expected.m = dbl_ld_acc.m; /* non-zero accumulator */
123: dbl_expected.l = dbl_ld_acc.l;
124: } else { /* zero accumulator */
125: if( (no_fpp_wcs) && (dbl_ld_acc.m) ) {
126: dbl_expected.m = dbl_ld_acc.m; /* don't clear the bad 0 */
127: dbl_expected.l = dbl_ld_acc.l;
128: } else {
129: dbl_expected.m = 0; /* clear any bad 0's */
130: dbl_expected.l = 0;
131: }
132: } /* end of "0" accumulator */
133: if( ( dbl_expected.m != dbl_st_acc.m ) ||
134: ( (precision == DBL) && (dbl_expected.l != dbl_st_acc.l) ) ) {
135: error = TRUE;
136: errcnt++;
137: if( prt_error )
138: prt_fpm_acc_er();
139: if( halt_flg )
140: fpm_halt( 5 ); /* halt on the error */
141: if( loop_on_err )
142: force_loop = TRUE; /* set loop flag */
143: }
144: }
145:
146:
147:
148:
149:
150: /****************************************************************************
151: *
152: * Check the final register values
153: *
154: ****************************************************************************/
155: chk_fpm_regs()
156: {
157: reg_no = 0; /* check regs 0 - 12 */
158: regs_ok = TRUE;
159: while( (reg_no < 13) && (regs_ok) )
160: if( store_regs[ reg_no ] == exp_regs[ reg_no ] )
161: reg_no++;
162: else
163: regs_ok = FALSE;
164: if( !regs_ok ) {
165: error = TRUE;
166: errcnt++;
167: if( prt_error ) {
168: prt_dmp_er_msg( reg_modified_msg );
169: prt_reg_data(); /* print the bad register */
170: }
171: if( halt_flg )
172: fpm_halt( 4 ); /* halt on the error */
173: if( loop_on_err )
174: force_loop = TRUE; /* set loop flag */
175: }
176: }
177:
178:
179:
180:
181:
182: /****************************************************************************
183: *
184: * print a "no FPM trap occurred" error message
185: *
186: ****************************************************************************/
187: prt_no_fpm_trap()
188: {
189: prt_dmp_er_msg( " - EXPECTED FPM TRAP DID NOT OCCUR" );
190: writes("initial Acc = ");
191: write32h( dbl_ld_acc.m );
192: if( precision == DBL ) {
193: writec(' ');
194: write32h( dbl_ld_acc.l );
195: }
196: writes(", ");
197: writed( no_page_faults );
198: writes(" page faults occurred\n");
199: writes(" operand = ");
200: write32h( dbl_value_1.m );
201: if( precision == DBL ) {
202: writec(' ');
203: write32h( dbl_value_1.l );
204: }
205: writes(", ");
206: writed( exp_page_faults );
207: writes(" page faults occurred\n");
208: }
209:
210:
211:
212:
213: /****************************************************************************
214: *
215: * print a "bad data on the stack after an fpm event" message
216: *
217: ****************************************************************************/
218: prt_fpm_stack_er()
219: {
220: prt_dmp_er_msg( bad_fpm_stack_msg );
221: writes("initial Acc = ");
222: write32h( dbl_ld_acc.m );
223: if( precision == DBL ) {
224: writec(' ');
225: write32h( dbl_ld_acc.l );
226: }
227: writes(", ");
228: writed( no_page_faults );
229: writes(" page faults occurred\n");
230: writes(" final Acc = ");
231: write32h( dbl_st_acc.m );
232: if( precision == DBL ) {
233: writec(' ');
234: write32h( dbl_st_acc.l );
235: }
236: writes(", ");
237: writed( exp_page_faults );
238: writes(" page faults occurred\n");
239: writes(" data on the stack expected\n");
240: writes(" MS operand = ");
241: write32h( fpm_ms_op ); /* MS operand */
242: writes(", ");
243: write32h( dbl_value_1.m );
244: writes("\n LS operand = ");
245: write32h( fpm_ls_op ); /* LS operand */
246: writes(", ");
247: write32h( dbl_value_1.l );
248: writes("\n op-code = ");
249: write32h( fpm_op_code ); /* op-code */
250: writes(", ");
251: write32h( op_code );
252: writes("\n PC = ");
253: write32h( fpm_pc ); /* PC */
254: writes(", ");
255: write32h( exp_pc );
256: writes("\n PSL = ");
257: write32h( fpm_psl ); /* PSL */
258: writes(", ");
259: write32h( init_psl );
260: writec('\n');
261: }
262:
263:
264:
265: /****************************************************************************
266: *
267: * print a "bad Accumulator after an fpm event" message
268: *
269: ****************************************************************************/
270: prt_fpm_acc_er()
271: {
272: prt_dmp_er_msg( bad_fpm_acc_msg );
273: writes(" initial Acc = ");
274: write32h( dbl_ld_acc.m );
275: if( precision == DBL ) {
276: writec(' ');
277: write32h( dbl_ld_acc.l );
278: }
279: writes(", ");
280: writed( no_page_faults );
281: writes(" page faults occurred\n");
282: writes(" final Acc = ");
283: write32h( dbl_st_acc.m );
284: if( precision == DBL ) {
285: writec(' ');
286: write32h( dbl_st_acc.l );
287: }
288: writes(", ");
289: writed( exp_page_faults );
290: writes(" page faults occurred\n");
291: writes("expected Acc = ");
292: write32h( dbl_expected.m );
293: if( precision == DBL ) {
294: writec(' ');
295: write32h( dbl_expected.l );
296: }
297: writec('\n');
298: }
299:
300:
301:
302:
303: /****************************************************************************
304: *
305: * Halt on an error
306: *
307: ****************************************************************************/
308: fpm_halt( code )
309: int code; /* error code to halt with */
310: {
311: sgl_dummy1 = code;
312: asm("movl _test_no,r0"); /* r0 = test number */
313: asm("movl _addr_code,r1"); /* r1 = addr mode code */
314: asm("movl _sgl_dummy1,r2"); /* r2 = error code */
315: asm("movl _cycle,r3"); /* r3 = cycle count */
316: if( code == 7 ) { /* no FPM trap */
317: sgl_value_1 = dbl_ld_acc.l;
318: sgl_value_2 = dbl_st_acc.l;
319: if( precision == DBL )
320: sgl_value_3 = dbl_value_1.l; /* LS of the operand */
321: else
322: sgl_value_4 = 0; /* there is no LS op */
323: asm("movl _dbl_ld_acc,r4"); /* r4 = MS of initial Acc */
324: asm("movl _sgl_value_1,r5"); /* r5 = LS of initial Acc */
325: asm("movl _dbl_st_acc,r6"); /* r6 = MS of final Acc */
326: asm("movl _sgl_value_2,r7"); /* r7 = LS of final Acc */
327: asm("movl _no_page_faults,r8"); /* r8 = # page faults */
328: asm("movl _exp_page_faults,r9"); /* r9 = exp # page faults */
329: asm("movl _dbl_value_1,r10"); /* r10 = MS operand 1 */
330: asm("movl _sgl_value_3,r11"); /* r11 = LS operand 1 */
331: asm("movl _index,r12"); /* r12 = data index */
332: } else { /* got an FPM trap */
333: asm("movl _fpm_psl,r4"); /* r4 = PSL on the stack */
334: asm("movl _fpm_pc,r5"); /* r5 = PC on the stack */
335: asm("movl _fpm_op_code,r6"); /* r6 = OP-CODE on stack */
336: asm("movl _fpm_ls_op,r7"); /* r7 = LS op. on stack */
337: asm("movl _fpm_ms_op,r8"); /* r8 = MS op. on stack */
338: }
339: if( code == 8 ) { /* bad stack */
340: sgl_value_1 = dbl_value_1.l;
341: asm("movl _exp_psl,r9"); /* r9 = PSL expected */
342: asm("movl _exp_pc,r10"); /* r10 = PC expected */
343: asm("movl _op_code,r11"); /* r11 = OP-CODE expected */
344: asm("movl _sgl_value_1,r12"); /* r12 = LS op. expected */
345: asm("movl _dbl_value_1,r13"); /* r13 = MS op. expected */
346: asm("movl _no_page_faults,r14"); /* r14 = # page faults */
347: }
348: else if( code == 5 ) { /* bad final Acc */
349: sgl_value_1 = dbl_st_acc.l;
350: sgl_value_2 = dbl_expected.l;
351: asm("movl _dbl_st_acc,r9"); /* r9 = MS final Acc. */
352: asm("movl _sgl_value_1,r10"); /* r10 = LS final Acc. */
353: asm("movl _dbl_expected,r11"); /* r11 = MS expected Acc. */
354: asm("movl _sgl_value_2,r12"); /* r12 = LS expected Acc. */
355: asm("movl _index,r13"); /* r13 = data index */
356: asm("movl _no_page_faults,r14"); /* r14 = # page faults */
357: }
358: else if( code == 5 ) { /* bad final Acc */
359: asm("movl _reg_no,r9"); /* r9 = bad register # */
360: asm("movl _store_regs[r9],r10"); /* r10 = final (bad) value */
361: asm("movl _exp_regs[r9],r11"); /* r11 = expected value */
362: asm("movl _no_page_faults,r12"); /* r12 = # page faults */
363: asm("movl _index,r13"); /* r13 = data index */
364: }
365: else if( code == 3 ) { /* wrong # page faults */
366: asm("movl _no_page_faults,r9"); /* r9 = # page faults */
367: asm("movl _exp_page_faults,r10"); /* r10 = exp # page faults */
368: asm("movl _index,r11"); /* r11 = data index */
369: };
370: asm("halt");
371: }
372:
373:
374:
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