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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / dmp4

Power 6/32 Unix version 1.21

#include "dmp_defs.h"

/**********************************************************************
*
*	Check the results of an FPP Emulation Trap (FPM)
*
* This code will verify:
*   - the data pushed onto the stack by the trap 
*   - the PSL saved after the event
*   - the number of page faults
*   - the final accumulator value
*   - the register values 
*
**********************************************************************/
chk_fpm_trap()
{
	error = FALSE;
	if( !fpm_trap_occurred ) {	/* Did we get an FPM trap?  */
	     error = TRUE;
	     errcnt++;
	     if( prt_error ) 
		  prt_no_fpm_trap();	/* print an error message */
	     if( halt_flg ) 
		  fpm_halt( 7 );	/* halt with code = 7 */
	     if( loop_on_err )
		  force_loop = TRUE;
	}
	 else {				/* got trap -check the results */
	     chk_fpm_data();		/* check data pushed on stack  */
	     if( !error ) 
	          chk_fpm_faults();	/* check # of page faults      */
	     if( !error )
	          chk_final_acc();	/* check final Acc value       */
	     if( !error )
	          chk_fpm_regs();	/* check final REG values      */
	} 
} 



/****************************************************************************
*
*	Check the results of an FPP Emulation Trap.
*
*  Check the stack data, the final accumulator, and the registers. The data
*  was saved by the FPM trap handler.
*  The stack data is:
*   - the PSL
*   - the PC of the next instruction
*   - the op-code
*   - the operand's LS longword  { for double precision instructions }
*   - the operand's MS longword
*
****************************************************************************/
chk_fpm_data()
{
	exp_pc = code_addr + inst_size;		/* expected PC on stack */
/*
 * check the FPM variables pushed onto the stack
*/
	if( !no_ops ) {
	    dbl_value_1.m = fpm_ms_op;		/* accept anything for the */
	    dbl_value_1.l = fpm_ls_op;		/* operand if no operands  */
	}
	if( (fpm_ms_op != dbl_value_1.m) ||
	    ((fpm_ls_op != dbl_value_1.l) && (precision == DBL) && (!s_to_d)) ||
	    (fpm_op_code != op_code) ||
	    (fpm_pc != exp_pc) ||
	    (fpm_psl != init_psl) ) {
	     error = TRUE;
	     errcnt++;
	     if( prt_error ) 
		  prt_fpm_stack_er();
	     if( halt_flg ) 
		  fpm_halt( 8 );		/* halt on the error */
	     if( loop_on_err )
		  force_loop = TRUE;		/* set loop flag */
	}
}


/****************************************************************************
*
*	Check the number of page faults that were generated
*
****************************************************************************/
chk_fpm_faults()
{
	if( no_page_faults != exp_page_faults ) {
	     error = TRUE;
	     errcnt++;
	     if( prt_error ) {
		  prt_dmp_er_msg( trans_flt_cnt_msg );
		  writed( no_page_faults);
		  writes(" occurred\n");
		  writed( exp_page_faults);
		  writes(" were expected\n");
		  prt_reg_data();		/* print the bad register */
	     }
	     if( halt_flg ) 
		       fpm_halt( 3 );		/* halt on the error */
	     if( loop_on_err )
		  force_loop = TRUE;		/* set loop flag */
	} 
}



/****************************************************************************
*
*	Check the final Accumulator value
*
*  The "no-fpp" firmware will not clear "bad 0" accumulators if the
*  MS of the operand loaded has any bits set. The LS will be cleared if
*  the MS is already all 0's.
*
****************************************************************************/
chk_final_acc()
{
	if( dbl_ld_acc.m & 0x7f800000 )	{	/* get final ACC expected */
	     dbl_expected.m = dbl_ld_acc.m;	/* non-zero accumulator */
	     dbl_expected.l = dbl_ld_acc.l;
	} else {				/* zero accumulator */
	     if( (no_fpp_wcs) && (dbl_ld_acc.m) ) {
	         dbl_expected.m = dbl_ld_acc.m;	/* don't clear the bad 0 */
	         dbl_expected.l = dbl_ld_acc.l;
	     } else {
	         dbl_expected.m = 0;		/* clear any bad 0's */
	         dbl_expected.l = 0;
	     }
	}  /* end of "0" accumulator */
	if( ( dbl_expected.m != dbl_st_acc.m ) ||
	    ( (precision == DBL) && (dbl_expected.l != dbl_st_acc.l) ) ) {
	     error = TRUE;
	     errcnt++;
	     if( prt_error ) 
		  prt_fpm_acc_er();
	     if( halt_flg ) 
		       fpm_halt( 5 );		/* halt on the error */
	     if( loop_on_err )
		  force_loop = TRUE;			/* set loop flag */
	} 
}





/****************************************************************************
*
*	Check the final register values
*
****************************************************************************/
chk_fpm_regs()
{
	 reg_no = 0;			/* check regs 0 - 12 */
	 regs_ok = TRUE;
	 while( (reg_no < 13) && (regs_ok) )  
	      if( store_regs[ reg_no ] == exp_regs[ reg_no ] )
		   reg_no++;
	      else
		   regs_ok = FALSE;
	 if( !regs_ok ) {
	      error = TRUE;
	      errcnt++;
	      if( prt_error ) {
		   prt_dmp_er_msg( reg_modified_msg );
		   prt_reg_data();		/* print the bad register */
	      }
	      if( halt_flg )
		   fpm_halt( 4 );		/* halt on the error */
	      if( loop_on_err )
		   force_loop = TRUE;		/* set loop flag */
	}
}





/****************************************************************************
*
*	print a "no FPM trap occurred" error message
*
****************************************************************************/
prt_no_fpm_trap()
{
	prt_dmp_er_msg( " - EXPECTED FPM TRAP DID NOT OCCUR" );
	writes("initial Acc = ");
	write32h( dbl_ld_acc.m );
	if( precision == DBL ) {
	     writec(' ');
	     write32h( dbl_ld_acc.l );
	}
	writes(",    ");
	writed( no_page_faults );
	writes(" page faults occurred\n");
	writes("    operand = ");
	write32h( dbl_value_1.m );
	if( precision == DBL ) {
	     writec(' ');
	     write32h( dbl_value_1.l );
	}
	writes(",    ");
	writed( exp_page_faults );
	writes(" page faults occurred\n");
}




/****************************************************************************
*
*	print a "bad data on the stack after an fpm event" message
*
****************************************************************************/
prt_fpm_stack_er()
{
	prt_dmp_er_msg( bad_fpm_stack_msg );
	writes("initial Acc = ");
	write32h( dbl_ld_acc.m );
	if( precision == DBL ) {
	     writec(' ');
	     write32h( dbl_ld_acc.l );
	}
	writes(",    ");
	writed( no_page_faults );
	writes(" page faults occurred\n");
	writes("  final Acc = ");
	write32h( dbl_st_acc.m );
	if( precision == DBL ) {
	     writec(' ');
	     write32h( dbl_st_acc.l );
	}
	writes(",    ");
	writed( exp_page_faults );
	writes(" page faults occurred\n");
	writes("  data on the stack      expected\n");
	writes(" MS operand = ");
	write32h( fpm_ms_op );			/* MS operand */
	writes(",  ");
	write32h( dbl_value_1.m );
	writes("\n LS operand = ");
	write32h( fpm_ls_op );			/* LS operand */
	writes(",  ");
	write32h( dbl_value_1.l );
	writes("\n    op-code = ");
	write32h( fpm_op_code );		/* op-code */
	writes(",  ");
	write32h( op_code );
	writes("\n        PC  = ");
	write32h( fpm_pc );			/* PC */
	writes(",  ");
	write32h( exp_pc );
	writes("\n        PSL = ");
	write32h( fpm_psl );			/* PSL */
	writes(",  ");
	write32h( init_psl );
	writec('\n');
}



/****************************************************************************
*
*	print a "bad Accumulator after an fpm event" message
*
****************************************************************************/
prt_fpm_acc_er()
{
	prt_dmp_er_msg( bad_fpm_acc_msg );
	writes(" initial Acc = ");
	write32h( dbl_ld_acc.m );
	if( precision == DBL ) {
	     writec(' ');
	     write32h( dbl_ld_acc.l );
	}
	writes(",    ");
	writed( no_page_faults );
	writes(" page faults occurred\n");
	writes("   final Acc = ");
	write32h( dbl_st_acc.m );
	if( precision == DBL ) {
	     writec(' ');
	     write32h( dbl_st_acc.l );
	}
	writes(",    ");
	writed( exp_page_faults );
	writes(" page faults occurred\n");
	writes("expected Acc = ");
	write32h( dbl_expected.m );
	if( precision == DBL ) {
	     writec(' ');
	     write32h( dbl_expected.l );
	}
	writec('\n');
}




/****************************************************************************
*
*	Halt on an error
*
****************************************************************************/
fpm_halt( code )
int code;				/* error code to halt with */
{
	sgl_dummy1 = code;
	asm("movl _test_no,r0");		/* r0  = test number       */
	asm("movl _addr_code,r1");		/* r1  = addr mode code    */
	asm("movl _sgl_dummy1,r2");		/* r2  = error code        */
	asm("movl _cycle,r3");			/* r3  = cycle count       */
	if( code == 7 ) {	/* no FPM trap */
	     sgl_value_1 = dbl_ld_acc.l;
	     sgl_value_2 = dbl_st_acc.l;
	     if( precision == DBL )
	          sgl_value_3 = dbl_value_1.l;	  /* LS of the operand */  
	     else
	          sgl_value_4 = 0;		  /* there is no LS op */  
	     asm("movl _dbl_ld_acc,r4");	/* r4  = MS of initial Acc */
	     asm("movl _sgl_value_1,r5");	/* r5  = LS of initial Acc */
	     asm("movl _dbl_st_acc,r6");	/* r6  = MS of final Acc   */
	     asm("movl _sgl_value_2,r7");	/* r7  = LS of final Acc   */
	     asm("movl _no_page_faults,r8");	/* r8  = # page faults     */
	     asm("movl _exp_page_faults,r9");	/* r9  = exp # page faults */
	     asm("movl _dbl_value_1,r10");	/* r10 = MS operand 1      */
	     asm("movl _sgl_value_3,r11");	/* r11 = LS operand 1      */
	     asm("movl _index,r12");		/* r12 = data index        */
	} else {		/* got an FPM trap */
	     asm("movl _fpm_psl,r4");		/* r4  = PSL on the stack  */
	     asm("movl _fpm_pc,r5");		/* r5  = PC on the stack   */
	     asm("movl _fpm_op_code,r6");	/* r6  = OP-CODE on stack  */
	     asm("movl _fpm_ls_op,r7");		/* r7  = LS op. on stack   */
	     asm("movl _fpm_ms_op,r8");		/* r8  = MS op. on stack   */
	}
	if( code == 8 ) {	/* bad stack */
	     sgl_value_1 = dbl_value_1.l;
	     asm("movl _exp_psl,r9");		/* r9  = PSL expected      */
	     asm("movl _exp_pc,r10");		/* r10 = PC expected       */
	     asm("movl _op_code,r11");		/* r11 = OP-CODE expected  */
	     asm("movl _sgl_value_1,r12");	/* r12 = LS op. expected   */
	     asm("movl _dbl_value_1,r13");	/* r13 = MS op. expected   */
	     asm("movl _no_page_faults,r14");	/* r14 = # page faults     */
	} 
	 else if( code == 5 ) {	/* bad final Acc */
	     sgl_value_1 = dbl_st_acc.l;
	     sgl_value_2 = dbl_expected.l;
	     asm("movl _dbl_st_acc,r9");	/* r9  = MS final Acc.     */
	     asm("movl _sgl_value_1,r10");	/* r10 = LS final Acc.     */
	     asm("movl _dbl_expected,r11");	/* r11 = MS expected Acc.  */
	     asm("movl _sgl_value_2,r12");	/* r12 = LS expected Acc.  */
	     asm("movl _index,r13");		/* r13 = data index        */
	     asm("movl _no_page_faults,r14");	/* r14 = # page faults     */
	}
	 else if( code == 5 ) {	/* bad final Acc */
	     asm("movl _reg_no,r9");		/* r9  = bad register #    */
	     asm("movl _store_regs[r9],r10");	/* r10 = final (bad) value */
	     asm("movl _exp_regs[r9],r11");	/* r11 = expected value    */
	     asm("movl _no_page_faults,r12");	/* r12 = # page faults     */
	     asm("movl _index,r13");		/* r13 = data index        */
	}
	 else if( code == 3 ) {	/* wrong # page faults */
	     asm("movl _no_page_faults,r9");	/* r9  = # page faults     */
	     asm("movl _exp_page_faults,r10");	/* r10 = exp # page faults */
	     asm("movl _index,r11");		/* r11 = data index        */
	};
	asm("halt");
}

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