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1.1 root 1:
2: #include "dmp_defs.h"
3:
4: /***********************************************************************
5: *
6: * Verify results after a single precision TSTF or CMPF(2) instruction
7: *
8: * The final PSL value is compared to the expected value. Also, the
9: * final accumulator and the registers are checked to make sure that
10: * they weren't modified.
11: ***********************************************************************/
12: chk_sgl_psl()
13: {
14: sgl_ld_acc = dbl_ld_acc.m; /* move the data to */
15: sgl_st_acc = dbl_st_acc.m; /* the sgl data */
16: sgl_expected = dbl_expected.m; /* operands */
17: sgl_value_1 = dbl_value_1.m;
18: sgl_value_2 = dbl_value_2.m;
19: if( sgl_ld_acc & 0x7f800000 ) /* get final ACC expected */
20: sgl_value_5 = sgl_ld_acc;
21: else
22: sgl_value_5 = 0;
23: exp_psl = init_psl; /* get the initial PSL */
24: exp_psl &= 0xffffff71; /* clear DBL & flag bits */
25: exp_psl |= PSL_C; /* set the CARRY bit */
26: if( sgl_expected == ZERO )
27: exp_psl |= PSL_Z; /* expect the ZERO bit set */
28: if( sgl_expected == NEGATIVE )
29: exp_psl |= PSL_N; /* expect the NEG bit set */
30: if( psl_val != exp_psl )
31: {
32: errcnt++;
33: if( prt_error )
34: prt_s_psl_e( bad_psl_msg );
35: if( halt_flg )
36: hlt_s_psl_e( 1 ); /* error code 1 */
37: if( loop_on_err )
38: force_loop = TRUE; /* set loop flag */
39: }
40: else if( no_page_faults != exp_page_faults ) {
41: errcnt++;
42: if( prt_error )
43: prt_s_psl_e( trans_flt_cnt_msg );
44: if( halt_flg )
45: hlt_s_psl_e( 2 ); /* error code 2 */
46: if( loop_on_err )
47: force_loop = TRUE; /* set loop flag */
48: }
49: else if( sgl_st_acc != sgl_value_5 ) {
50: errcnt++;
51: if( prt_error )
52: prt_s_psl_e( acc_modified_msg );
53: if( halt_flg )
54: hlt_s_psl_e( 3 ); /* error code 3 */
55: if( loop_on_err )
56: force_loop = TRUE; /* set loop flag */
57: }
58: else {
59: reg_no = 0;
60: regs_ok = TRUE;
61: while( (reg_no <= 13) && (regs_ok) ) /* check 1st 13 regs */
62: if( store_regs[ reg_no ] == exp_regs[ reg_no ] )
63: reg_no++;
64: else
65: regs_ok = FALSE;
66: if( !regs_ok )
67: {
68: errcnt++;
69: if( prt_error )
70: prt_s_psl_e( reg_modified_msg );
71: if( halt_flg )
72: hlt_s_psl_e( 4 ); /* error code 4 */
73: if( loop_on_err )
74: force_loop = TRUE; /* set loop flag */
75: }
76: }
77: }
78:
79:
80:
81:
82: /************************************************************************
83: * CHK_SGL_PSL
84: *
85: * cycle: xx. DMP test xx. <inst>. <error message>, index = xx
86: * addressing mode: <addressing mode description>
87: * inst buf= xx xx xx xx xx xx xx xx xx xx xx -page faults on byte(s) 0, x
88: * initial Acc = xxxxxxxx, operand 1 = xxxxxxxx, xx page faults occurred
89: * final Acc = xxxxxxxx, operand 2 = xxxxxxxx, xx page faults expected
90: * initial PSL = xxxxxxxx, final PSL = xxxxxxxx, expected PSL = xxxxxxxx
91: ************************************************************************/
92: prt_s_psl_e( message )
93: char *message;
94: {
95: prt_dmp_er_msg( message ); /* print the error header */
96: writes("initial Acc = ");
97: write32h( sgl_ld_acc ); /* print Acc loaded */
98: if( no_ops ) {
99: writes(", operand 1 = ");
100: write32h( sgl_value_1 ); /* write op 1 data */
101: }
102: writes(", ");
103: writed( no_page_faults ); /* print # page faults */
104: writes(" page faults occurred\n");
105: writes(" final Acc = "); /* print final Acc data */
106: write32h( sgl_st_acc );
107: if( no_ops == 2 ) {
108: writes(", operand 2 = ");
109: write32h( sgl_value_2 ); /* write op 2 data */
110: writec(',');
111: } else if( no_ops == 1 )
112: writes(", "); /* (only 1 operand) */
113: else
114: writec(','); /* (there were no operands) */
115: writes(" ");
116: writed( exp_page_faults ); /* print # page faults */
117: writes(" page faults expected\n");
118: writes("initial PSL = "); /* print PSL data */
119: write32h( init_psl );
120: writes(", final PSL = ");
121: write32h( psl_val );
122: writes(", expected PSL = ");
123: write32h( exp_psl );
124: writec('\n');
125: if( message == reg_modified_msg ) /* print modified register */
126: prt_reg_data(); /* print bad register */
127: }
128:
129:
130:
131: /**************************************************************************
132: * Set up the registers and halt
133: **************************************************************************/
134: hlt_s_psl_e( code )
135: int code;
136: {
137: sgl_dummy1 = code;
138: asm("movl _test_no,r0"); /* r0 = test number */
139: asm("movl _addr_code,r1"); /* r1 = addressing mode */
140: asm("movl _sgl_dummy1,r2"); /* r2 = error code */
141: asm("movl _cycle,r3"); /* r3 = cycle count */
142: asm("movl _sgl_ld_acc,r4"); /* r4 = initial Acc. */
143: if( no_ops )
144: asm("movl _sgl_value_1,r5"); /* r5 = operand 1 */
145: else
146: asm("clrl r5");;
147: if( no_ops == 2 )
148: asm("movl _sgl_value_2,r6"); /* r6 = operand 2 */
149: else
150: asm("clrl r6");;
151: asm("movl _init_psl,r7"); /* r7 = initial psl */
152: asm("movl _psl_val,r8"); /* r8 = final psl */
153: asm("movl _exp_psl,r9"); /* r9 = expected psl */
154: if( code == 2 ) {
155: asm("movl _no_page_faults,r10"); /* r10 = # page faults */
156: asm("movl _exp_page_faults,r11"); /* r11 = # faults expected */
157: }
158: else if( code == 3 ) /* or */
159: asm("movl _sgl_st_acc,r10"); /* r10 = final Acc. */
160: else /* or */
161: {
162: asm("movl _reg_no,r10"); /* r10 = bad register # */
163: asm("movl _store_regs[r10],r11"); /* r11 = final (bad) value */
164: asm("movl _exp_regs[r10],r12"); /* r12 = expected value */
165: }
166: asm(".globl _hlt_sgl_psl");
167: asm("_hlt_sgl_psl:");
168: asm("halt");
169: }
170:
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