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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / dmp4

Power 6/32 Unix version 1.21

#include "dmp_defs.h"

/***********************************************************************
*
*   Verify results after a single precision TSTF or CMPF(2) instruction
*
*  The final PSL value is compared to the expected value. Also, the
*  final accumulator and the registers are checked to make sure that 
*  they weren't modified.
***********************************************************************/
chk_sgl_psl()
{
	sgl_ld_acc   = dbl_ld_acc.m;		/* move the data to */
	sgl_st_acc   = dbl_st_acc.m;		/*   the sgl data   */
	sgl_expected = dbl_expected.m;		/*      operands  */
	sgl_value_1 = dbl_value_1.m;
	sgl_value_2 = dbl_value_2.m;
	if( sgl_ld_acc & 0x7f800000 )		/* get final ACC expected */
	     sgl_value_5 = sgl_ld_acc;
	 else
	     sgl_value_5 = 0;
	exp_psl = init_psl;			/* get the initial PSL      */
	exp_psl &= 0xffffff71;			/* clear DBL & flag bits    */
	exp_psl |= PSL_C;			/* set the CARRY bit        */
	if( sgl_expected == ZERO )
	    exp_psl |= PSL_Z;			/* expect the ZERO bit set  */
	if( sgl_expected == NEGATIVE )
	    exp_psl |= PSL_N;			/* expect the NEG bit set   */
	if( psl_val != exp_psl )
	{
	    errcnt++;
	    if( prt_error )
		 prt_s_psl_e( bad_psl_msg );
	    if( halt_flg )
		 hlt_s_psl_e( 1 );		/* error code 1 */
	    if( loop_on_err )
		 force_loop = TRUE;		/* set loop flag */
	}
	 else if( no_page_faults != exp_page_faults ) {
	    errcnt++;
	    if( prt_error )
		 prt_s_psl_e( trans_flt_cnt_msg );
	    if( halt_flg )
		 hlt_s_psl_e( 2 );		/* error code 2 */
	    if( loop_on_err )
		 force_loop = TRUE;		/* set loop flag */
	}
	 else if( sgl_st_acc != sgl_value_5 ) {
	    errcnt++;
	    if( prt_error )
		 prt_s_psl_e( acc_modified_msg );
	    if( halt_flg )
		 hlt_s_psl_e( 3 );		/* error code 3 */
	    if( loop_on_err )
		 force_loop = TRUE;		/* set loop flag */
	}
	 else {
	    reg_no = 0;
	    regs_ok = TRUE;
	    while( (reg_no <= 13) && (regs_ok) )  /* check 1st 13 regs */
		if( store_regs[ reg_no ] == exp_regs[ reg_no ] )
		    reg_no++;
		else
		    regs_ok = FALSE;
	    if( !regs_ok )
	    {
	        errcnt++;
	        if( prt_error )
		     prt_s_psl_e( reg_modified_msg );
	        if( halt_flg )
		     hlt_s_psl_e( 4 );		/* error code 4 */
	        if( loop_on_err )
		     force_loop = TRUE;		/* set loop flag */
	    }
	} 
}




/************************************************************************
*		CHK_SGL_PSL
*
* cycle: xx. DMP test xx. <inst>. <error message>, index = xx
* addressing mode: <addressing mode description>
* inst buf= xx xx xx xx xx xx xx xx xx xx xx -page faults on byte(s) 0, x 
* initial Acc = xxxxxxxx,  operand 1 = xxxxxxxx,   xx page faults occurred
*   final Acc = xxxxxxxx,  operand 2 = xxxxxxxx,   xx page faults expected
* initial PSL = xxxxxxxx,   final PSL = xxxxxxxx,  expected PSL = xxxxxxxx
************************************************************************/
prt_s_psl_e( message )
char *message;
{
	prt_dmp_er_msg( message );		/* print the error header */
	writes("initial Acc = ");
	write32h( sgl_ld_acc );			/* print Acc loaded */
	if( no_ops ) {
	    writes(",  operand 1 = ");
	    write32h( sgl_value_1 );		/* write op 1 data */
	}
	writes(",   ");
	writed( no_page_faults );		/* print # page faults */
	writes(" page faults occurred\n");
	writes("  final Acc = ");		/* print final Acc data */
	write32h( sgl_st_acc );
	if( no_ops == 2 ) {
	    writes(",  operand 2 = ");
	    write32h( sgl_value_2 );		/* write op 2 data */
	    writec(',');
	} else if( no_ops == 1 )
	    writes(",                       ");	/* (only 1 operand)  */
	else
	    writec(',');			/* (there were no operands) */
	writes("   ");
	writed( exp_page_faults );		/* print # page faults */
	writes(" page faults expected\n");
	writes("initial PSL = ");			/* print PSL data */
	write32h( init_psl );
	writes(",   final PSL = ");
	write32h( psl_val );
	writes(",  expected PSL = ");
	write32h( exp_psl );
	writec('\n');
	if( message == reg_modified_msg )	/* print modified register */
	    prt_reg_data();			/* print bad register      */
}



/**************************************************************************
*	Set up the registers and halt
**************************************************************************/
hlt_s_psl_e( code )
int code;
{
	sgl_dummy1 = code;
	asm("movl _test_no,r0");		/* r0  = test number       */
	asm("movl _addr_code,r1");		/* r1  = addressing mode   */
	asm("movl _sgl_dummy1,r2");		/* r2  = error code        */
	asm("movl _cycle,r3");			/* r3  = cycle count       */
	asm("movl _sgl_ld_acc,r4");		/* r4  = initial Acc.      */
	if( no_ops )
	    asm("movl _sgl_value_1,r5");	/* r5  = operand 1         */
	else
	    asm("clrl r5");;
	if( no_ops == 2 )
	    asm("movl _sgl_value_2,r6");	/* r6  = operand 2         */
	else
	    asm("clrl r6");;
	asm("movl _init_psl,r7");		/* r7  = initial psl       */
	asm("movl _psl_val,r8");		/* r8  = final psl         */
	asm("movl _exp_psl,r9");		/* r9  = expected psl      */
	if( code == 2 ) {
	    asm("movl _no_page_faults,r10");	/* r10 = # page faults     */
	    asm("movl _exp_page_faults,r11");	/* r11 = # faults expected */
	}
	 else if( code == 3 )			/*  or  */
	    asm("movl _sgl_st_acc,r10");	/* r10 = final Acc.        */
	 else					/*  or  */
	{
	    asm("movl _reg_no,r10");		/* r10 = bad register #    */
	    asm("movl _store_regs[r10],r11");	/* r11 = final (bad) value */
	    asm("movl _exp_regs[r10],r12");	/* r12 = expected value    */
	}
	asm(".globl _hlt_sgl_psl");
	asm("_hlt_sgl_psl:");
	asm("halt");
}

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