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Power 6/32 Unix version 1.21
/**************************************************************************
*
* FLOATING POINT PROCESSOR DIAGNOSTIC DEFINITIONS
*
* 10-Dec-84 : added "enable_data_cache" option flag
* 26-Jun-85 : added MULL2 and MULL3
**************************************************************************/
#define TRUE 1
#define FALSE 0
/*
* some tests are accessed via tables of pointers to the test functions
*/
typedef int (*func_ptr_array[20])(); /* array of pointers to functions */
/*
* Precisions used
*/
#define SGL 1
#define DBL 2
/*
* Operand types
*/
#define NONE 0 /* no operand */
#define LOAD 1 /* operand is a data address */
#define STORE 2 /* operand is a STORE address */
/*
* Priveleged Register contents
*/
#define SBR 0 /*system base register */
#define SLR 1 /*system length reg */
#define P0BR 2 /*p0 base reg */
#define P0LR 3 /*p0 length reg */
#define P1BR 4 /*p1 base reg */
#define P1LR 5 /*p1 length reg */
#define P2BR 6 /*p2 base reg */
#define P2LR 7 /*p2 length reg */
#define IPL 8 /*int priority level reg */
#define MME 9 /*memory mgmt enable reg */
#define TBIA 10 /*trans buf invalidate all */
/*entries */
#define TBIS 11 /*trans buf invalidate single */
/*entry */
#define DCK 12 /*data cache key */
#define CCK 13 /*code cache key */
#define PCBB 14 /*process control block base */
#define ISP 15 /*interrupt stack pointer */
#define SIRR 16 /*software int request reg */
#define SISR 17 /*software int summary reg */
#define SCBB 18 /*system control block base reg */
#define KSP 19 /*kernel stack pointer reg */
#define USP 20 /*user stack pointer */
#define DCB 21 /*CPU2 DCB */
#define PACC 23 /*purge (invalidate) all pages */
/*of process in code cache */
#define P1DC 24 /*purge one page of data cache */
#define PADC 25 /*purge all the pages of */
/*process in data cache */
#define HISR 26 /* Hardware interrupt summary reg */
#define DCR 27 /* Diagnostic control register */
#define PDCS 28 /* Purge 1 data cache slot */
/*
* PSL bit definitions
*/
#define PSL_C 0x1 /* bit(00) CARRY bit */
#define PSL_V 0x2 /* bit(01) OVERFLOW bit */
#define PSL_Z 0x4 /* bit(02) ZERO bit */
#define PSL_N 0x8 /* bit(03) NEGATIVE bit */
#define PSL_EN_T 0x10 /* bit(04) Enable TRACE bit */
#define PSL_EN_OVFL 0x20 /* bit(05) Enable OVERFLOW bit*/
#define PSL_EN_UNDFL 0x40 /* bit(06) Enable UNDERFLOW */
#define PSL_DBL 0x80 /* bit(07) DBL Precision acc. */
#define ENABLE_EVENTS 0x60 /* enable INT OVFL & UNDFL */
/*
* Event Codes
*/
#define SW_IPL1_CODE 0x1e /* s/w interrupt (IPL = 1) */
#define BUS_ER_CODE 0x20 /* buss error interrupt */
#define RESINST_CODE 0x2c /* priveleged/reserved instr. */
#define RESOP_CODE 0x2d /* reserved operand fault */
#define RESAD_CODE 0x2e /* reserved address fault */
#define TRACE_CODE 0x33 /* trace trap */
#define ARITH_CODE 0x34 /* arithmetic fault */
#define ALIGN_CODE 0x35 /* alignment fault */
#define SFE_CODE 0x36 /* system forced exception */
#define FPM_CODE 0x37 /* fpp emulation trap */
/*
* Arithmetic Event Types
*/
#define INT_OVFL_CODE 1 /* integer overflow fault */
#define INT_0_DIV_CODE 2 /* integer divide by 0 fault */
#define FLT_0_DIV_CODE 3 /* floating divide by 0 fault */
#define FLT_OVFL_CODE 4 /* floating overflow fault */
#define FLT_UNDFL_CODE 5 /* floating underflow fault */
/*
* jump condition flag definitions
*/
#define POSITIVE 2 /* positive flag bit */
#define ZERO 4 /* zero flag bit */
#define NEGATIVE 8 /* negative flag bit */
/*
* OP-CODEs for the FPP instruction set
*/
#define LDF_OP_CODE 0x06 /* sgl load acc. instr */
#define LDD_OP_CODE 0x07 /* dbl load acc. instr */
#define LNF_OP_CODE 0x16 /* sgl load-neg acc. instr */
#define LND_OP_CODE 0x17 /* dbl load-neg acc. instr */
#define STF_OP_CODE 0x26 /* sgl store acc. instr */
#define STD_OP_CODE 0x27 /* dbl store acc. instr */
#define CMPF_OP_CODE 0x36 /* sgl compare instr */
#define CMPD_OP_CODE 0x37 /* dbl compare instr */
#define CMPF2_OP_CODE 0x46 /* sgl compare 2 instr */
#define CMPD2_OP_CODE 0x47 /* dbl compare 2 instr */
#define TSTF_OP_CODE 0x56 /* sgl test acc. instr */
#define TSTD_OP_CODE 0x57 /* dbl test acc. instr */
#define PUSHD_OP_CODE 0x67 /* dbl push acc. instr */
#define CVLF_OP_CODE 0x76 /* convert int to sgl instr */
#define CVLD_OP_CODE 0x77 /* convert int to dbl instr */
#define CVFL_OP_CODE 0x86 /* convert sgl to int instr */
#define CVDL_OP_CODE 0x87 /* convert dbl to int instr */
#define LDFD_OP_CODE 0x97 /* load sgl to dbl instr */
#define CVDF_OP_CODE 0xa6 /* convert dbl to sgl instr */
#define NEGF_OP_CODE 0xb6 /* negate sgl acc. instr */
#define NEGD_OP_CODE 0xb7 /* negate dbl acc. instr */
#define ADDF_OP_CODE 0xc6 /* sgl add instr */
#define ADDD_OP_CODE 0xc7 /* dbl add instr */
#define SUBF_OP_CODE 0xd6 /* sgl subtract instr */
#define SUBD_OP_CODE 0xd7 /* dbl subtract instr */
#define MULF_OP_CODE 0xe6 /* sgl multiply instr */
#define MULD_OP_CODE 0xe7 /* dbl multiply instr */
#define DIVF_OP_CODE 0xf6 /* sgl divide instr */
#define DIVD_OP_CODE 0xf7 /* dbl divide instr */
#define SINF_OP_CODE 0x05 /* sgl sine instr */
#define COSF_OP_CODE 0x15 /* sgl cosine instr */
#define ATANF_OP_CODE 0x25 /* sgl arc-tangent instr */
#define LOGF_OP_CODE 0x35 /* sgl natural log instr */
#define SQRTF_OP_CODE 0x45 /* sgl square root instr */
#define EXPF_OP_CODE 0x55 /* sgl "e to the x" instr */
#define MULL2_OP_CODE 0x4c /* multiply integer 2 instr */
#define MULL3_OP_CODE 0x5c /* multiply integer 3 instr */
#define NO_INSTRUCTIONS 37 /* 37 fpp instructions */
/*
* definitions for addressing mode tests
*/
#define ADR_ABSOLUTE 1 /* absolute address */
#define ADR_LITERAL 2 /* literal -short immediate byte */
#define ADR_IM_B 3 /* immediate byte */
#define ADR_IM_W 4 /* immediate word */
#define ADR_IM_L 5 /* immediate long-word */
#define ADR_B_DSP 6 /* byte displ relative */
#define ADR_W_DSP 7 /* word displ relative */
#define ADR_L_DSP 8 /* long-word displ relative */
#define ADR_B_DSP_DEF 9 /* byte displ relative deferred */
#define ADR_W_DSP_DEF 10 /* word displ relative deferred */
#define ADR_L_DSP_DEF 11 /* long-word displ relative deferred */
#define ADR_REG 12 /* direct register */
#define ADR_REG_DEF 13 /* register deferred */
#define ADR_FP_DEF 14 /* FP deferred */
#define ADR_SP_DEF 15 /* SP deferred */
#define ADR_PUSH 16 /* auto-decrement SP */
#define ADR_POP 17 /* auto-increment SP */
#define ADR_POP_DEF 18 /* auto-increment SP deferred */
#define ADR_REG_B 19 /* register + byte displ */
#define ADR_REG_W 20 /* register + word displ */
#define ADR_REG_L 21 /* register + long-word displ */
#define ADR_REG_B_DEF 22 /* register + byte displ deferred */
#define ADR_REG_W_DEF 23 /* register + word displ deferred */
#define ADR_REG_L_DEF 24 /* register + long-word displ deferred */
#define ADR_I_FP_DEF 25 /* indexed (frame pointer deferred) */
#define ADR_I_L 26 /* indexed (longword displacement) */
#define ADR_I_REG_DEF 27 /* indexed (register deferred) */
#define ADR_I_L_DEF 28 /* indexed (longword displacement deferred) */
#define SIZ_ADDR_MODE_TABLE 29 /* allow for 29 addressing types ( w/ '0' ) */
/*
* Define the halt codes for the tests
*/
#define UNEXP_EVT_HLT 0 /* unexpected event */
#define BAD_ACC_HLT 1 /* bad final Acc. */
#define BAD_REG_HLT 2 /* bad final register */
#define BAD_PSL_HLT 3 /* wrong PSL value */
#define NO_EVT_HLT 4 /* did not Get event */
#define EVT_MSK_HLT 5 /* got masked event */
#define PUSH_PSL_HLT 6 /* bad PSL on stack */
#define BAD_FPM_STK_HLT 7 /* stack error w/ FPM */
#define PUSH_CNT_HLT 8 /* wrong # ops on stack */
#define BAD_STORE_HLT 9 /* bad data stored */
/*****************************************************************************
*
* These are the global variables
*
*****************************************************************************/
/*
* These are the run option flags
*/
extern int halt_flg; /* halt on error flag */
extern int loop_on_err; /* loop on error flag */
extern int prt_error; /* print error message flag */
extern int prt_hdrs; /* print main header flag */
extern int prt_sbtsts; /* outdated -print subtest headers*/
extern int en_data_cache; /* enable the data chache flag */
/*
* These are used by the tests as control flags
*/
extern int no_fpp_wcs; /* "NO-FPP WCS" loaded flag */
extern int valid_test; /* a valid test was requested */
extern int test_no; /* fpp test number */
extern int run_all; /* all subtests run flag */
extern int count; /* cycle count to run */
extern int nonstop; /* run forever flag n */
extern int run_list; /* test # (or 0) to test */
extern int subtest; /* fpp subtest number */
extern int cycle; /* current test cycle */
extern int force_loop; /* loop on error signal */
extern int errcnt; /* error count */
extern int err_code; /* error code (for subtests) */
extern int zero; /* a known '0' data word */
extern int nop_cnt; /* # of NOPs between instr's */
extern int i_cache_hit; /* flag -test instr. in cache */
extern int event_type; /* actual event type */
extern int event_code; /* actual arith. fault type */
extern int test_event; /* event type under test */
extern int exp_event; /* expected event type (or 0) */
extern int exp_code; /* expected event code */
extern int event_return; /* return addr. after event */
extern int unexp_event_ret; /* return if event unexpected */
extern int fpm_trap_occurred; /* flag -got an FPM trap */
extern int monitor_fp; /* monitor's frame pointer */
extern int monitor_sp; /* monitor's stack pointer */
extern int run_code_psl; /* "run_code"'s entry PSL */
extern int pre_event_sp; /* stack pointer before event */
extern int post_event_sp; /* stack pointer after event */
extern int pre_event_fp; /* frame pointer before event */
extern int post_event_fp; /* frame pointer after event */
extern int post_event_psl; /* PSL after an (FPM) event */
extern int event_pc; /* PC on stack from an event */
extern int event_psl; /* PSL on stack from an event */
extern int pointer_data; /* location to set SP / FP to */
extern int pointer_data_2; /* LSW data for SP / FP addrs */
extern int address_fault_expected; /* fault expected or not */
extern int loop_addr; /* address to loop on error */
extern int next_addr; /* start of "next addr. test" */
extern int addr_mode; /* addressing type under test */
extern int addr_code; /* code for addressing op. #1 */
extern int addr_code2; /* code for addressing op. #2 */
extern int addr_code3; /* code for addressing op. #3 */
extern int addr_codeB; /* 2nd addr code for indexing */
extern int test_index; /* index to a specific test */
extern int inst_index; /* index to a specific instr. */
extern int index; /* test data index */
extern int index2; /* test data index # 2 */
extern int error; /* an error exists flag */
extern int clock_event; /* diagnostic flag -rtc event */
extern int status_index; /* index to status array */
extern int status_array[]; /* holds (+), (-), (0) words */
extern char *subtest_message; /* description of subtest */
extern char *error_message; /* description of error */
extern char *event_msg; /* description of event */
extern char *addressing_modes[SIZ_ADDR_MODE_TABLE];
/*
* These are the canned error messages
*/
extern char *k_mode_msg; /* Kernal Mode message */
extern char *u_mode_msg; /* User Mode message */
extern char *i_cache_hit_msg; /* instr. cache hit message */
extern char *i_cache_miss_msg; /* instr. cache miss message */
extern char *bad_result_msg; /* incorrect result error */
extern char *acc_modified_msg; /* Accumulator modified msg. */
extern char *bad_acc_msg; /* incorrect ACC message */
extern char *psl_modified_msg; /* PSL modified message */
extern char *bad_psl_msg; /* incorrect PSL message */
extern char *reg_modified_msg; /* register modified message */
extern char *trans_flt_cnt_msg; /* wrong # of page faults */
extern char *no_evt_msg; /* expected event didn't occur*/
extern char *disbl_evt_msg; /* a disabled event occurred */
extern char *push_cnt_msg; /* wrong # ops. pushed w/ evt.*/
extern char *psl_pushed_msg; /* wrong PSL pushed w/ event */
extern char *pc_pushed_msg; /* wrong PC pushed w/ event */
extern char *trans_acc_er_msg; /* Acc wrong after pg fault */
extern char *bad_fpm_stack_msg; /* stack wrong after FPM trap */
extern char *bad_fpm_acc_msg; /* Acc wrong after FPM trap */
/*
* These values are used for alternating data patterns in error looping
*/
extern int old_indx; /* previous test data index */
extern int loop_val_1a; /* MSW of 1st data op in loop */
extern int loop_val_1b; /* MSW of 1st data op in loop */
extern int loop_val_1c; /* LSW of 1st data op in loop */
extern int loop_val_1d; /* LSW of 1st data op in loop */
extern int loop_val_2a; /* MSW of 2nd data op in loop */
extern int loop_val_2b; /* MSW of 2nd data op in loop */
extern int loop_val_2c; /* LSW of 2nd data op in loop */
extern int loop_val_2d; /* LSW of 2nd data op in loop */
/*
* data structure definitions
*/
struct u64 { /* 64 bit (dbl) integer */
unsigned m; /* -most significant bits */
unsigned l; /* -least significant bits */
};
struct cmpd_data_t { /* compare 2 dbl opderands */
struct u64 one; /* -1st compare value */
struct u64 two; /* -2nd compare value */
int flag; /* -expected condition flg */
};
struct cmpf_data_t { /* compare 2 sgl operands */
int one; /* -1st compare value */
int two; /* -2nd compare value */
int flag; /* -expected condition flg */
};
struct cvds_data_t { /* convert dbl op to sgl */
struct u64 ld; /* -data to load */
unsigned exp; /* -converted result */
};
struct cvfl_data_t { /* convert sgl to integer */
unsigned ld; /* -data to load */
unsigned exp; /* -converted result */
};
struct ldd_data_t { /* load / store doubles */
struct u64 ld; /* -data to load */
struct u64 exp; /* -expected results */
};
struct ldf_data_t { /* load / store singles */
unsigned ld; /* -data to load */
unsigned exp; /* -expected results */
};
struct ldfd_data_t { /* load sgl convert to dbl */
unsigned ld; /* -sgl data to load */
struct u64 exp; /* -dbl data expected */
};
struct addf_data_t { /* sgl precision +, -, *, / */
unsigned op_1; /* -operand 1 ( in ACC. ) */
unsigned op_2; /* -operand 2 */
unsigned exp; /* -expected result */
};
struct addd_data_t { /* dbl precision +, -, *, / */
struct u64 op_1; /* -operand 1 ( in ACC. ) */
struct u64 op_2; /* -operand 2 */
struct u64 exp; /* -expected result */
};
struct addd_ovflw_t { /* dbl reserved operands */
struct u64 op_1; /* -operand 1 ( in ACC. ) */
struct u64 op_2; /* -operand 2 ( RESOP ) */
};
struct addf_ovflw_t { /* sgl reserved operands */
unsigned op_1; /* -operand 1 ( in ACC. ) */
unsigned op_2; /* -operand 2 ( RESOP ) */
};
/*
* data variables used by the tests (must be declared someplace)
*/
extern struct ldf_data_t ldf_1_data[]; /* LDF data pattern array */
extern int max_ldf_1_index; /* (# data patterns) -1 */
extern struct ldf_data_t lnf_1_data[]; /* LNF */
extern int max_lnf_1_index;
extern struct addf_data_t addf_1_data[]; /* ADDF */
extern int max_addf_1_index;
extern struct addf_data_t subf_1_data[]; /* SUBF */
extern int max_subf_1_index;
extern struct addf_data_t mulf_1_data[]; /* MULF */
extern int max_mulf_1_index;
extern struct addf_data_t divf_1_data[]; /* DIVF */
extern int max_divf_1_index;
extern struct cvfl_data_t cvlf_1_data[]; /* CVLF */
extern int max_cvlf_1_index;
extern struct cmpd_data_t cmpd_1_data[]; /* CMPD */
extern int max_cmpd_1_index;
extern struct cmpd_data_t cmpd2_1_data[]; /* CMPD2 */
extern int max_cmpd2_1_index;
extern struct cmpf_data_t cmpf_1_data[]; /* CMPF */
extern int max_cmpf_1_index;
extern struct cmpf_data_t cmpf2_1_data[]; /* CMPF2 */
extern int max_cmpf2_1_index;
extern struct cvds_data_t cvdf_1_data[]; /* CVDF */
extern int max_cvdf_1_index;
extern struct cvds_data_t cvdl_1_data[]; /* CVDL */
extern int max_cvdl_1_index;
extern struct cvfl_data_t cvfl_1_data[]; /* CVFL */
extern int max_cvfl_1_index;
extern struct ldfd_data_t cvld_1_data[]; /* CVLD */
extern int max_cvld_1_index;
extern struct ldd_data_t ldd_1_data[]; /* LDD */
extern int max_ldd_1_index;
extern struct ldfd_data_t ldfd_1_data[]; /* LDFD */
extern int max_ldfd_1_index;
extern struct ldd_data_t lnd_1_data[]; /* LND */
extern int max_lnd_1_index;
extern struct addd_data_t addd_1_data[]; /* ADDD */
extern int max_addd_1_index;
extern struct addd_data_t subd_1_data[]; /* SUBD */
extern int max_subd_1_index;
extern struct addd_data_t muld_1_data[]; /* MULD */
extern int max_muld_1_index;
extern struct addd_data_t divd_1_data[]; /* DIVD */
extern int max_divd_1_index;
extern struct ldd_data_t pushd_1_data[]; /* PUSHD */
extern int max_pushd_1_index;
extern struct cvds_data_t tstd_1_data[]; /* TSTD */
extern int max_tstd_1_index;
extern struct cvfl_data_t tstf_1_data[]; /* TSTF */
extern int max_tstf_1_index;
extern struct ldf_data_t sinf_1_data[]; /* SINF */
extern int max_sinf_1_index;
extern struct ldf_data_t cosf_1_data[]; /* COSF */
extern int max_cosf_1_index;
extern struct ldf_data_t atanf_1_data[]; /* ATANF */
extern int max_atanf_1_index;
extern struct ldf_data_t expf_1_data[]; /* EXPF */
extern int max_expf_1_index;
extern struct ldf_data_t logf_1_data[]; /* LOGF */
extern int max_logf_1_index;
extern struct ldf_data_t sqrtf_1_data[]; /* SQRTF */
extern int max_sqrtf_1_index;
extern struct ldf_data_t mull_1_data[]; /* MULL2 / MULL3 */
extern int max_mull_1_index;
/*
* global data variables
*/
extern struct u64 dbl_value_1; /* 1st dbl test value */
extern struct u64 dbl_value_2; /* 2nd dbl test value */
extern struct u64 dbl_value_3; /* 3rd dbl test value */
extern struct u64 dbl_expected; /* expected dbl data */
extern struct u64 dbl_ld_acc; /* load dbl acc. from here */
extern struct u64 dbl_st_acc; /* stored dbl accumulator */
extern struct u64 dbl_dummy1; /* dummy quad word */
extern struct u64 dbl_dummy2; /* ditto */
extern int sgl_ld_acc; /* load sgl acc. from here */
extern int sgl_st_acc; /* stored sgl acc. */
extern int sgl_expected; /* expected sgl data */
extern int sgl_value_1; /* 1st sgl data value */
extern int sgl_value_2; /* 2nd sgl data value */
extern int sgl_value_3; /* 3rd sgl data value */
extern int sgl_value_4; /* 4th sgl data value */
extern int sgl_value_5; /* 5th sgl data value */
extern int sgl_value_6; /* 6th sgl data value */
extern int sgl_value_7; /* 7th sgl data value */
extern int sgl_value_8; /* 8th sgl data value */
extern int sgl_value_9; /* 9th sgl data value */
extern int sgl_value_10; /* 10th sgl data value */
extern int sgl_dummy1; /* a dummy variable */
extern int sgl_dummy2; /* a dummy variable, too */
extern int psl_val; /* PSL value */
extern int init_psl; /* initial PSL value */
extern int exp_psl; /* expected PSL value */
extern int test_flags; /* condition flags seen */
extern int flg_expected; /* condition flags expected*/
extern int reg_no; /* register being validated */
extern int regs_ok; /* flag - no reg. miscompare*/
extern int exp_reg; /* expected reg. value */
extern int act_reg; /* actual register value */
extern int load_regs[14]; /* load registers from here */
extern int store_regs[14]; /* store registers here */
extern int exp_regs[14]; /* expected registers data */
extern int exp_pc; /* expected PC */
extern int act_pc; /* actual PC */
/*
* stack variables
*/
extern int pop_val_1; /* 1st popped stack data */
extern int pop_val_2; /* 2nd popped stack data */
extern int pop_val_3; /* 3rd popped stack data */
extern int pop_val_4; /* 4th popped stack data */
extern int pop_val_5; /* 5th popped stack data */
extern int pop_val_6; /* 6th popped stack data */
extern int fpm_ms_op; /* MS operand w/ FPM trap */
extern int fpm_ls_op; /* LS operand w/ FPM trap */
extern int fpm_op_code; /* op-code w/ FPM trap */
extern int fpm_pc; /* PC w/ FPM trap */
extern int fpm_psl; /* PSL w/ FPM trap */
/*
* variables used in the exaustive data tests
*/
extern int not_done; /* "keep testing" flag */
extern int fudgeing_ok; /* +/- 1 result is acceptable */
extern int use_BELL_data; /* use Bell Labs type fractions */
extern int max_BELL_index; /* # of Bell Labs type fractions */
extern int fraction_array[]; /* Bell Labs type fraction array */
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