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1.1 ! root 1: #include "dmp_defs.h" ! 2: ! 3: /************************************************************************** ! 4: * ! 5: * Test the current instruction ! 6: * ! 7: * If the current instruction accesses any operands, then test it with ! 8: * all major applicable addressing modes. ! 9: **************************************************************************/ ! 10: test_inst() ! 11: { ! 12: /* ! 13: * Set the values for the indirect pointers ! 14: */ ! 15: asm("movl _adr_op1,*_adr_op1_ptr"); /* word offset ptr #1 */ ! 16: asm("movl _adr_op2,*_adr_op2_ptr"); /* word offset ptr #2 */ ! 17: if( !no_ops ) ! 18: test_0_ops(); /* test inst w/ no operands */ ! 19: else ! 20: { ! 21: tst_abs(); /* absolute addressing */ ! 22: if( s_to_d || ! 23: ( (precision == SGL) && (op_type == LOAD) ) ) ! 24: tst_i_l(); /* immediate longword */ ! 25: tst_b(); /* byte displacement relative */ ! 26: tst_w(); /* word displacement relative */ ! 27: tst_l(); /* longword displacement relative */ ! 28: tst_b_d(); /* byte disp. relative deferred */ ! 29: tst_w_d(); /* word disp. relative deferred */ ! 30: tst_l_d(); /* longword disp. rel. deferred */ ! 31: tst_r(); /* direct register */ ! 32: tst_r_d(); /* register deferred */ ! 33: /* if( d_to_s || ( (precision == SGL) && (op_type == STORE) ) ) ! 34: /* tst_push(); /* PUSH ( auto-decremented SP ) */ ! 35: /* if( s_to_d || ( (precision == SGL) && (op_type == LOAD) ) ) ! 36: /* tst_pop(); /* POP ( auto-incremented SP ) */ ! 37: /* tst_pop_d(); /* auto-incremented SP deferred */ ! 38: tst_r_b(); /* register + byte displacement */ ! 39: tst_r_w(); /* register + word displacement */ ! 40: tst_r_l(); /* register _ longword disp. */ ! 41: tst_r_bd(); /* reg. + byte disp. deferred */ ! 42: tst_r_wd(); /* reg. + word disp. deferred */ ! 43: tst_r_ld(); /* reg. _ longword disp. deferred */ ! 44: tst_x_fpd(); /* FP deferred + longword index */ ! 45: tst_x_l(); /* longword disp. + longword index */ ! 46: } ! 47: } ! 48: ! 49: ! 50: ! 51: ! 52: ! 53: /******************************************************************* ! 54: * ABSOLUTE ADDRESSING: ! 55: * instruction = <op-code> <9f> <&dmp_op_1> {<9f> <&dmp_op_2>} ! 56: *******************************************************************/ ! 57: tst_abs() ! 58: { ! 59: fill_reg_buf( load_regs ); /* set data for registers */ ! 60: fill_reg_buf( exp_regs ); /* set data for registers */ ! 61: addr_mode = ADR_ABSOLUTE; ! 62: addr_code = 0x9f; ! 63: addr_code2 = 0x9f; ! 64: addr_size = 4; /* longword (4 byte) ops. */ ! 65: addr_1 = DMP_OP_1; /* abs. address of data */ ! 66: addr_2 = DMP_OP_2; ! 67: if( no_ops == 2 ) ! 68: min_shift = 6; ! 69: else ! 70: min_shift = 11; ! 71: index = 0; ! 72: for( shift_count = 15; shift_count >= min_shift; shift_count-- ) ! 73: { ! 74: get_current_data(); ! 75: *adr_op1 = dbl_value_1.m; /* set the 1st operand */ ! 76: *adr_op1_lsw = dbl_value_1.l; ! 77: *adr_op2 = dbl_value_2.m; /* set the 2nd operand */ ! 78: *adr_op2_lsw = dbl_value_2.l; ! 79: get_exp_faults( 3, 4, 4, 6 ); /* set exp fault cnt */ ! 80: pack_inst(); /* pack the instr. code */ ! 81: run_code(); /* execute the instruction */ ! 82: dbl_value_3.m = *adr_op1; /* get the final operand */ ! 83: dbl_value_3.l = *adr_op1_lsw; ! 84: (*test_ptr)(); /* verify the results */ ! 85: if( force_loop ) ! 86: run_code(); /* start the error loop */ ! 87: index++; /* bump the data index */ ! 88: } ! 89: } ! 90: ! 91: ! 92: ! 93: ! 94: ! 95: /******************************************************************* ! 96: * IMMEDIATE LONGWORD ADDRESSING: ( sgl and sgl_to_dbl only ) ! 97: * instruction = <op-code> <8f> <data> ! 98: *******************************************************************/ ! 99: tst_i_l() ! 100: { ! 101: fill_reg_buf( load_regs ); /* set data for registers */ ! 102: fill_reg_buf( exp_regs ); /* set data for registers */ ! 103: addr_mode = ADR_IM_L; ! 104: addr_code = addr_code2 = 0x8f; /* immediate lword = 0x8f */ ! 105: addr_size = 4; /* longword (4 byte) data */ ! 106: exp_page_faults = 2; /* 2 pages used */ ! 107: index = 0; ! 108: for( shift_count = 15; shift_count >= 11; shift_count-- ) ! 109: { ! 110: get_current_data(); ! 111: addr_1 = dbl_value_1.m; /* set the 1st operand */ ! 112: addr_2 = dbl_value_2.m; /* set the 2nd operand */ ! 113: pack_inst(); /* pack the instr. code */ ! 114: run_code(); /* execute the instruction */ ! 115: (*test_ptr)(); /* verify the results */ ! 116: if( force_loop ) ! 117: run_code(); /* start the error loop */ ! 118: index++; /* bump the data index */ ! 119: } ! 120: } ! 121: ! 122: ! 123: ! 124: /******************************************************************* ! 125: * BYTE DISPLACEMENT RELATIVE ADDRESSING: ! 126: * instruction = <op-code> <af> <offset to dmp_byte_op_1> ! 127: * { <af> <offset to dmp_byte_op_2> } ! 128: *******************************************************************/ ! 129: tst_b() ! 130: { ! 131: fill_reg_buf( load_regs ); /* set data for registers */ ! 132: fill_reg_buf( exp_regs ); /* set data for registers */ ! 133: addr_mode = ADR_B_DSP; ! 134: addr_code = addr_code2 = 0xaf; ! 135: addr_size = 1; /* 1 byte operand */ ! 136: exp_page_faults = 2; /* 2 pages used */ ! 137: if( no_ops == 2 ) ! 138: min_shift = 11; ! 139: else ! 140: min_shift = 13; ! 141: index = 0; ! 142: for( shift_count = 15; shift_count >= min_shift; shift_count-- ) ! 143: { ! 144: get_current_data(); ! 145: *adr_b_op1 = dbl_value_1.m; /* set the operand */ ! 146: *adr_bop1_lsw = dbl_value_1.l; ! 147: *adr_b_op2 = dbl_value_2.m; /* set the operand */ ! 148: *adr_bop2_lsw = dbl_value_2.l; ! 149: addr_1 = os_b_op1 + 13 - shift_count; /* data's offset */ ! 150: addr_2 = os_b_op2 + 11 - shift_count; ! 151: pack_inst(); /* pack the instr. code */ ! 152: run_code(); /* execute the instruction */ ! 153: dbl_value_3.m = *adr_b_op1; /* get the final operand */ ! 154: dbl_value_3.l = *adr_bop1_lsw; ! 155: (*test_ptr)(); /* verify the results */ ! 156: if( force_loop ) ! 157: run_code(); /* start the error loop */ ! 158: index++; /* bump the data index */ ! 159: } ! 160: } ! 161: ! 162: ! 163: ! 164: /******************************************************************* ! 165: * WORD DISPLACEMENT RELATIVE ADDRESSING: ! 166: * instruction = <op-code> <cf> <offset to dmp_op_1> ! 167: * { <cf> <offset to dmp_op_2> } ! 168: *******************************************************************/ ! 169: tst_w() ! 170: { ! 171: fill_reg_buf( load_regs ); /* set data for registers */ ! 172: fill_reg_buf( exp_regs ); /* set data for registers */ ! 173: addr_mode = ADR_W_DSP; ! 174: addr_code = addr_code2 = 0xcf; ! 175: addr_size = 2; /* word (2 byte) operand */ ! 176: if( no_ops == 2 ) ! 177: min_shift = 10; ! 178: else ! 179: min_shift = 13; ! 180: index = 0; ! 181: for( shift_count = 15; shift_count >= min_shift; shift_count-- ) ! 182: { ! 183: get_current_data(); ! 184: *adr_op1 = dbl_value_1.m; /* set the operand */ ! 185: *adr_op1_lsw = dbl_value_1.l; ! 186: *adr_op2 = dbl_value_2.m; ! 187: *adr_op2_lsw = dbl_value_2.l; ! 188: addr_1 = os_op1 + 12 - shift_count; /* data's offset */ ! 189: addr_2 = os_op2 + 9 - shift_count; ! 190: get_exp_faults( 3, 4, 4, 6 ); /* set exp fault cnt */ ! 191: pack_inst(); /* pack the instr. code */ ! 192: run_code(); /* execute the instruction */ ! 193: dbl_value_3.m = *adr_op1; /* get the final operand */ ! 194: dbl_value_3.l = *adr_op1_lsw; ! 195: (*test_ptr)(); /* verify the results */ ! 196: if( force_loop ) ! 197: run_code(); /* start the error loop */ ! 198: index++; /* bump the data index */ ! 199: } ! 200: } ! 201: ! 202: ! 203: ! 204: /******************************************************************* ! 205: * LONGWORD DISPLACEMENT RELATIVE ADDRESSING: ! 206: * instruction = <op-code> <ef> <offset to dmp_op_1> ! 207: * { <ef> <offset to dmp_op_2> } ! 208: *******************************************************************/ ! 209: tst_l() ! 210: { ! 211: fill_reg_buf( load_regs ); /* set data for registers */ ! 212: fill_reg_buf( exp_regs ); /* set data for registers */ ! 213: addr_mode = ADR_L_DSP; ! 214: addr_code = addr_code2 = 0xef; ! 215: addr_size = 4; /* longword (4 byte) ops. */ ! 216: if( no_ops == 2 ) ! 217: min_shift = 6; ! 218: else ! 219: min_shift = 11; ! 220: index = 0; ! 221: for( shift_count = 15; shift_count >= min_shift; shift_count-- ) ! 222: { ! 223: get_current_data(); ! 224: *adr_op1 = dbl_value_1.m; /* set the operand */ ! 225: *adr_op1_lsw = dbl_value_1.l; ! 226: *adr_op2 = dbl_value_2.m; ! 227: *adr_op2_lsw = dbl_value_2.l; ! 228: get_exp_faults( 3, 4, 4, 6 ); /* set exp fault cnt */ ! 229: addr_1 = os_op1 + 10 - shift_count; /* data's offset */ ! 230: addr_2 = os_op2 + 5 - shift_count; ! 231: pack_inst(); /* pack the instr. code */ ! 232: run_code(); /* execute the instruction */ ! 233: dbl_value_3.m = *adr_op1; /* get the final operand */ ! 234: dbl_value_3.l = *adr_op1_lsw; ! 235: (*test_ptr)(); /* verify the results */ ! 236: if( force_loop ) ! 237: run_code(); /* start the error loop */ ! 238: index++; /* bump the data index */ ! 239: } ! 240: } ! 241: ! 242: ! 243: ! 244: /******************************************************************* ! 245: * BYTE DISPLACEMENT RELATIVE DEFERRED ADDRESSING: ! 246: * instruction = <op-code> <bf> <offset to dmp_byte_op_1> ! 247: * { <bf> <offset to dmp_byte_op_2> } ! 248: *******************************************************************/ ! 249: tst_b_d() ! 250: { ! 251: fill_reg_buf( load_regs ); /* set data for registers */ ! 252: fill_reg_buf( exp_regs ); /* set data for registers */ ! 253: addr_mode = ADR_B_DSP_DEF; ! 254: addr_code = addr_code2 = 0xbf; ! 255: addr_size = 1; /* 1 byte operand */ ! 256: *adr_b_op1 = (int) adr_op1; /* set byte offset ptr #1 */ ! 257: *adr_b_op2 = (int) adr_op2; /* set byte offset ptr #2 */ ! 258: if( no_ops == 2 ) ! 259: min_shift = 11; ! 260: else ! 261: min_shift = 13; ! 262: index = 0; ! 263: for( shift_count = 15; shift_count >= min_shift; shift_count-- ) ! 264: { ! 265: get_current_data(); ! 266: *adr_op1 = dbl_value_1.m; /* set the operand */ ! 267: *adr_op1_lsw = dbl_value_1.l; ! 268: *adr_op2 = dbl_value_2.m; ! 269: *adr_op2_lsw = dbl_value_2.l; ! 270: get_exp_faults( 3, 4, 4, 6 ); /* set exp fault cnt */ ! 271: addr_1 = os_b_op1 + 13 - shift_count; /* data's offset */ ! 272: addr_2 = os_b_op2 + 11 - shift_count; ! 273: pack_inst(); /* pack the instr. code */ ! 274: run_code(); /* execute the instruction */ ! 275: dbl_value_3.m = *adr_op1; /* get the final operand */ ! 276: dbl_value_3.l = *adr_op1_lsw; ! 277: (*test_ptr)(); /* verify the results */ ! 278: if( force_loop ) ! 279: run_code(); /* start the error loop */ ! 280: index++; /* bump the data index */ ! 281: } ! 282: } ! 283: ! 284: ! 285: ! 286: ! 287: /******************************************************************* ! 288: * WORD DISPLACEMENT RELATIVE DEFERRED ADDRESSING: ! 289: * instruction = <op-code> <df> <offset to dmp_op_1> ! 290: * { <df> <offset to dmp_op_2> } ! 291: *******************************************************************/ ! 292: tst_w_d() ! 293: { ! 294: fill_reg_buf( load_regs ); /* set data for registers */ ! 295: fill_reg_buf( exp_regs ); /* set data for registers */ ! 296: addr_mode = ADR_W_DSP_DEF; ! 297: addr_code = addr_code2 = 0xdf; ! 298: addr_size = 2; /* word (2 byte) operand */ ! 299: if( no_ops == 2 ) ! 300: min_shift = 10; ! 301: else ! 302: min_shift = 13; ! 303: index = 0; ! 304: for( shift_count = 15; shift_count >= min_shift; shift_count-- ) ! 305: { ! 306: get_current_data(); ! 307: *adr_op1 = dbl_value_1.m; /* set the operand */ ! 308: *adr_op1_lsw = dbl_value_1.l; ! 309: *adr_op2 = dbl_value_2.m; ! 310: *adr_op2_lsw = dbl_value_2.l; ! 311: get_exp_faults( 4, 5, 6, 8 ); /* set exp fault cnt */ ! 312: addr_1 = os_ad_op1 + 12 - shift_count; /* operand offset */ ! 313: addr_2 = os_ad_op2 + 9 - shift_count; ! 314: pack_inst(); /* pack the instr. code */ ! 315: run_code(); /* execute the instruction */ ! 316: dbl_value_3.m = *adr_op1; /* get the final operand */ ! 317: dbl_value_3.l = *adr_op1_lsw; ! 318: (*test_ptr)(); /* verify the results */ ! 319: if( force_loop ) ! 320: run_code(); /* start the error loop */ ! 321: index++; /* bump the data index */ ! 322: } ! 323: } ! 324: ! 325: ! 326: ! 327: /******************************************************************* ! 328: * LONGWORD DISPLACEMENT RELATIVE DEFERRED ADDRESSING: ! 329: * instruction = <op-code> <ff> <offset to dmp_op_1> ! 330: * { <ff> <offset to dmp_op_1> } ! 331: *******************************************************************/ ! 332: tst_l_d() ! 333: { ! 334: fill_reg_buf( load_regs ); /* set data for registers */ ! 335: fill_reg_buf( exp_regs ); /* set data for registers */ ! 336: addr_mode = ADR_L_DSP_DEF; ! 337: addr_code = addr_code2 = 0xff; ! 338: addr_size = 4; /* longword (4 byte) op. */ ! 339: if( no_ops == 2 ) ! 340: min_shift = 6; ! 341: else ! 342: min_shift = 11; ! 343: index = 0; ! 344: for( shift_count = 15; shift_count >= min_shift; shift_count-- ) ! 345: { ! 346: get_current_data(); ! 347: *adr_op1 = dbl_value_1.m; /* set the operand */ ! 348: *adr_op1_lsw = dbl_value_1.l; ! 349: *adr_op2 = dbl_value_2.m; /* set the operand */ ! 350: *adr_op2_lsw = dbl_value_2.l; ! 351: get_exp_faults( 4, 5, 6, 8 ); /* set exp fault cnt */ ! 352: addr_1 = os_ad_op1 + 10 - shift_count; /* operand offset */ ! 353: addr_2 = os_ad_op2 + 5 - shift_count; ! 354: pack_inst(); /* pack the instr. code */ ! 355: run_code(); /* execute the instruction */ ! 356: dbl_value_3.m = *adr_op1; /* get the final operand */ ! 357: dbl_value_3.l = *adr_op1_lsw; ! 358: (*test_ptr)(); /* verify the results */ ! 359: if( force_loop ) ! 360: run_code(); /* start the error loop */ ! 361: index++; /* bump the data index */ ! 362: } ! 363: } ! 364: ! 365: ! 366: ! 367: /******************************************************************* ! 368: * DIRECT REGISTER ADDRESSING: ! 369: * instruction = <op-code> <50> { <54> } ! 370: *******************************************************************/ ! 371: tst_r() ! 372: { ! 373: fill_reg_buf( load_regs ); /* set data for registers */ ! 374: fill_reg_buf( exp_regs ); /* set data for registers */ ! 375: addr_mode = ADR_REG; ! 376: addr_code = 0x50; /* 1st op in registers 0/1 */ ! 377: addr_code2 = 0x54; /* 2nd op in registers 4/5 */ ! 378: addr_size = 0; /* no addressing bytes */ ! 379: pack_inst(); /* pack the instr. code */ ! 380: exp_page_faults = 2; /* 2 pages used */ ! 381: if( no_ops == 2 ) ! 382: min_shift = 14; ! 383: else ! 384: min_shift = 15; ! 385: for( shift_count = 15; shift_count >= min_shift; shift_count-- ) ! 386: { ! 387: for( index = 0; index < 3; index++ ) ! 388: { ! 389: get_current_data(); ! 390: load_regs[0] = dbl_value_1.m; /* get the data */ ! 391: load_regs[1] = dbl_value_1.l; ! 392: load_regs[4] = dbl_value_2.m; ! 393: load_regs[5] = dbl_value_2.l; ! 394: exp_regs[4] = load_regs[4]; /* set exp final reg value */ ! 395: exp_regs[5] = load_regs[5]; ! 396: if( op_type == LOAD ) ! 397: { ! 398: exp_regs[0] = dbl_value_1.m; ! 399: exp_regs[1] = dbl_value_1.l; ! 400: } else { ! 401: exp_regs[0] = dbl_expected.m; ! 402: exp_regs[1] = dbl_expected.l; ! 403: } ! 404: if( op_code == CVDL_OP_CODE ) /* correct for sgl store */ ! 405: exp_regs[1] = dbl_value_1.l; /* r1 shouldn't change */ ! 406: run_code(); /* execute the instruction */ ! 407: dbl_value_3.m = store_regs[0]; /* get final r0, r1 values */ ! 408: dbl_value_3.l = store_regs[1]; ! 409: (*test_ptr)(); /* verify the results */ ! 410: if( force_loop ) ! 411: run_code(); /* start the error loop */ ! 412: } ! 413: } ! 414: } ! 415: ! 416: ! 417: ! 418: /******************************************************************* ! 419: * REGISTER DEFERRED ADDRESSING: ! 420: * instruction = <op-code> <60> {<61>} ! 421: *******************************************************************/ ! 422: tst_r_d() ! 423: { ! 424: fill_reg_buf( load_regs ); /* set data for registers */ ! 425: fill_reg_buf( exp_regs ); /* set data for registers */ ! 426: addr_mode = ADR_REG_DEF; ! 427: addr_code = 0x60; ! 428: addr_code2 = 0x61; ! 429: addr_size = 0; /* no address byte(s) */ ! 430: load_regs[0] = (int) adr_op1; /* get addr of op. 1 */ ! 431: load_regs[1] = (int) adr_op2; /* get addr of op. 2 */ ! 432: exp_regs[0] = load_regs[0]; ! 433: exp_regs[1] = load_regs[1]; ! 434: pack_inst(); /* pack the instr. code */ ! 435: if( no_ops == 2 ) ! 436: min_shift = 14; ! 437: else ! 438: min_shift = 15; ! 439: for( shift_count = 15; shift_count >= min_shift; shift_count-- ) ! 440: { ! 441: for( index = 0; index < 3; index++ ) ! 442: { ! 443: get_current_data(); ! 444: *adr_op1 = dbl_value_1.m; /* set the 1st data */ ! 445: *adr_op1_lsw = dbl_value_1.l; ! 446: *adr_op2 = dbl_value_2.m; /* set the 2nd data */ ! 447: *adr_op2_lsw = dbl_value_2.l; ! 448: get_exp_faults( 3, 4, 4, 6 ); /* set exp fault cnt */ ! 449: run_code(); /* execute the instruction */ ! 450: dbl_value_3.m = *adr_op1; /* get op's final value */ ! 451: dbl_value_3.l = *adr_op1_lsw; ! 452: (*test_ptr)(); /* verify the results */ ! 453: if( force_loop ) ! 454: run_code(); /* start the error loop */ ! 455: } ! 456: } ! 457: } ! 458: ! 459: ! 460: ! 461: ! 462: /******************************************************************* ! 463: * AUTO-DECREMENTED STACK POINTER ADDRESSING ( PUSH ): ! 464: * instruction = <op-code> <7e> ! 465: * ! 466: * The final result will be popped by "run_code" ! 467: *******************************************************************/ ! 468: tst_push() ! 469: { ! 470: fill_reg_buf( load_regs ); /* set data for registers */ ! 471: fill_reg_buf( exp_regs ); /* set data for registers */ ! 472: addr_mode = ADR_PUSH; ! 473: addr_code = 0x7e; ! 474: addr_size = 0; /* no addressing bytes */ ! 475: exp_page_faults = 3; /* 3 pages used */ ! 476: shift_count = 15; ! 477: pack_inst(); /* pack the instr. code */ ! 478: for( index = 0; index < 3; index++ ) ! 479: { ! 480: get_current_data(); ! 481: run_code(); /* execute the instruction */ ! 482: dbl_value_3.m = *adr_op1; /* get op's final value */ ! 483: (*test_ptr)(); /* verify the results */ ! 484: if( force_loop ) ! 485: run_code(); /* start the error loop */ ! 486: } ! 487: } ! 488: ! 489: ! 490: ! 491: ! 492: /******************************************************************* ! 493: * AUTO-INCREMENTED STACK POINTER ADDRESSING ( POP ): ( sgl ops only ) ! 494: * instruction = <op-code> <8e> ! 495: * ! 496: * The data will be pushed by "run_code" ! 497: *******************************************************************/ ! 498: tst_pop() ! 499: { ! 500: fill_reg_buf( load_regs ); /* set data for registers */ ! 501: fill_reg_buf( exp_regs ); /* set data for registers */ ! 502: addr_mode = ADR_POP; ! 503: addr_code = 0x8e; ! 504: addr_size = 0; /* no addressing bytes */ ! 505: pack_inst(); /* pack the instr. code */ ! 506: exp_page_faults = 3; /* 3 pages used */ ! 507: shift_count = 15; ! 508: for( index = 0; index < 3; index++ ) ! 509: { ! 510: get_current_data(); ! 511: sgl_value_9 = dbl_value_1.m; /* data to be pushed */ ! 512: if( no_ops == 2 ) ! 513: sgl_value_10 = dbl_value_2.m; ! 514: run_code(); /* execute the instruction */ ! 515: (*test_ptr)(); /* verify the results */ ! 516: if( force_loop ) ! 517: run_code(); /* start the error loop */ ! 518: } ! 519: } ! 520: ! 521: ! 522: ! 523: ! 524: ! 525: /******************************************************************* ! 526: * AUTO-INCREMENTED STACK POINTER DEFERRED ADDRESSING: ! 527: * instruction = <op-code> <9e> { <9e> } ! 528: * ! 529: * The address of the data will be pushed by "run_code" ! 530: *******************************************************************/ ! 531: tst_pop_d() ! 532: { ! 533: fill_reg_buf( load_regs ); /* set data for registers */ ! 534: fill_reg_buf( exp_regs ); /* set data for registers */ ! 535: addr_mode = ADR_POP_DEF; ! 536: addr_code = addr_code2 = 0x9e; ! 537: addr_size = 0; /* no addressing bytes */ ! 538: pack_inst(); /* pack the instr. code */ ! 539: sgl_value_9 = (int) adr_op1; /* get 1st op to be popped */ ! 540: sgl_value_10 = (int) adr_op2; /* get 2nd op to be popped */ ! 541: if( no_ops == 2 ) ! 542: min_shift = 14; ! 543: else ! 544: min_shift = 15; ! 545: for( shift_count = 15; shift_count >= min_shift; shift_count-- ) ! 546: { ! 547: for( index = 0; index < 3; index++ ) ! 548: { ! 549: get_current_data(); ! 550: *adr_op1 = dbl_value_1.m; /* set the 1st op's data */ ! 551: *adr_op1_lsw = dbl_value_1.l; ! 552: *adr_op2 = dbl_value_2.m; /* set the 2nd op's data */ ! 553: *adr_op2_lsw = dbl_value_2.l; ! 554: get_exp_faults( 4, 5, 5, 7 ); /* set exp fault cnt */ ! 555: run_code(); /* execute the instruction */ ! 556: dbl_value_3.m = *adr_op1; /* get op's final value */ ! 557: dbl_value_3.l = *adr_op1_lsw; ! 558: (*test_ptr)(); /* verify the results */ ! 559: if( force_loop ) ! 560: run_code(); /* start the error loop */ ! 561: } ! 562: } ! 563: } ! 564: ! 565: ! 566: ! 567: ! 568: ! 569: ! 570: /******************************************************************* ! 571: * REGISTER + BYTE DISPLACEMENT ADDRESSING: ! 572: * instruction = <op-code> <a4> <(&op_1 -r4)> ! 573: * { <a5> <(&op_2- r5)> } ! 574: *******************************************************************/ ! 575: tst_r_b() ! 576: { ! 577: fill_reg_buf( load_regs ); /* set data for registers */ ! 578: fill_reg_buf( exp_regs ); /* set data for registers */ ! 579: addr_mode = ADR_REG_B; ! 580: addr_code = 0xa4; /* addr 1 is offset by r4 */ ! 581: addr_code2 = 0xa5; /* addr 2 is offset by r5 */ ! 582: addr_size = 1; /* 1 byte operand */ ! 583: addr_1 = 20; /* set the 1st byte offset */ ! 584: addr_2 = 4; /* set the 2nd byte offset */ ! 585: pack_inst(); /* pack the instr. code */ ! 586: load_regs[4] = (int) adr_op1 - 20; /* get the reg value */ ! 587: load_regs[5] = (int) adr_op2 - 4; ! 588: exp_regs[4] = load_regs[4]; ! 589: exp_regs[5] = load_regs[5]; ! 590: if( no_ops == 2 ) ! 591: min_shift = 12; ! 592: else ! 593: min_shift = 14; ! 594: index = 0; ! 595: for( shift_count = 15; shift_count >= min_shift; shift_count-- ) ! 596: { ! 597: get_current_data(); ! 598: *adr_op1 = dbl_value_1.m; /* set the 1st operand */ ! 599: *adr_op1_lsw = dbl_value_1.l; ! 600: *adr_op2 = dbl_value_2.m; /* set the 2nd operand */ ! 601: *adr_op2_lsw = dbl_value_2.l; ! 602: get_exp_faults( 3, 4, 4, 6 ); /* set exp fault cnt */ ! 603: run_code(); /* execute the instruction */ ! 604: dbl_value_3.m = *adr_op1; /* get the final operand */ ! 605: dbl_value_3.l = *adr_op1_lsw; ! 606: (*test_ptr)(); /* verify the results */ ! 607: if( force_loop ) ! 608: run_code(); /* start the error loop */ ! 609: index++; /* bump the data index */ ! 610: } ! 611: } ! 612: ! 613: ! 614: ! 615: /******************************************************************* ! 616: * REGISTER + WORD DISPLACEMENT ADDRESSING: ! 617: * instruction = <op-code> <c4> <(&op_1 -r4)> ! 618: * { <c5> <(&op_2 -r5)> } ! 619: *******************************************************************/ ! 620: tst_r_w() ! 621: { ! 622: fill_reg_buf( load_regs ); /* set data for registers */ ! 623: fill_reg_buf( exp_regs ); /* set data for registers */ ! 624: addr_mode = ADR_REG_W; ! 625: addr_code = 0xc4; /* addr 1 is offset by r4 */ ! 626: addr_code2 = 0xc5; /* addr 2 is offset by r5 */ ! 627: addr_size = 2; /* word (2 byte) operand */ ! 628: addr_1 = 511; /* set the 1st word offset */ ! 629: addr_2 = 513; /* set the 2nd word offset */ ! 630: pack_inst(); /* pack the instr. code */ ! 631: load_regs[4] = (int) adr_op1 - 511; /* get the reg value */ ! 632: load_regs[5] = (int) adr_op2 - 513; ! 633: exp_regs[4] = load_regs[4]; ! 634: exp_regs[5] = load_regs[5]; ! 635: if( no_ops == 2 ) ! 636: min_shift = 10; ! 637: else ! 638: min_shift = 13; ! 639: index = 0; ! 640: for( shift_count = 15; shift_count >= min_shift; shift_count-- ) ! 641: { ! 642: get_current_data(); ! 643: *adr_op1 = dbl_value_1.m; /* set the 1st operand */ ! 644: *adr_op1_lsw = dbl_value_1.l; ! 645: *adr_op2 = dbl_value_2.m; /* set the 2nd operand */ ! 646: *adr_op2_lsw = dbl_value_2.l; ! 647: get_exp_faults( 3, 4, 4, 6 ); /* set exp fault cnt */ ! 648: run_code(); /* execute the instruction */ ! 649: dbl_value_3.m = *adr_op1; /* get the final operand */ ! 650: dbl_value_3.l = *adr_op1_lsw; ! 651: (*test_ptr)(); /* verify the results */ ! 652: if( force_loop ) ! 653: run_code(); /* start the error loop */ ! 654: index++; /* bump the data index */ ! 655: } ! 656: } ! 657: ! 658: ! 659: ! 660: ! 661: /******************************************************************* ! 662: * REGISTER + LONGWORD DISPLACEMENT ADDRESSING: ! 663: * instruction = <op-code> <e4> <(op_1 -r4)> ! 664: * { <e5> <(op_2 -r5)> } ! 665: *******************************************************************/ ! 666: tst_r_l() ! 667: { ! 668: fill_reg_buf( load_regs ); /* set data for registers */ ! 669: fill_reg_buf( exp_regs ); /* set data for registers */ ! 670: addr_mode = ADR_REG_B; ! 671: addr_code = 0xe4; /* addr 1 is offset by r4 */ ! 672: addr_code2 = 0xe5; /* addr 2 is offset by r5 */ ! 673: addr_size = 4; /* longword (4 byte) op. */ ! 674: addr_1 = (int) adr_op1 - 123; /* get the 1st addr base */ ! 675: addr_2 = (int) adr_op2 - 130; /* get the 2nd addr base */ ! 676: load_regs[4] = 123; /* reg 4 = 123 */ ! 677: exp_regs[4] = 123; ! 678: load_regs[5] = 130; /* reg 5 = 130 */ ! 679: exp_regs[5] = 130; ! 680: pack_inst(); /* pack the instr. code */ ! 681: if( no_ops == 2 ) ! 682: min_shift = 6; ! 683: else ! 684: min_shift = 11; ! 685: index = 0; ! 686: for( shift_count = 15; shift_count >= min_shift; shift_count-- ) ! 687: { ! 688: get_current_data(); ! 689: *adr_op1 = dbl_value_1.m; /* set the 1st operand */ ! 690: *adr_op1_lsw = dbl_value_1.l; ! 691: *adr_op2 = dbl_value_2.m; /* set the 2nd operand */ ! 692: *adr_op2_lsw = dbl_value_2.l; ! 693: get_exp_faults( 3, 4, 4, 6 ); /* set exp fault cnt */ ! 694: run_code(); /* execute the instruction */ ! 695: dbl_value_3.m = *adr_op1; /* get the final operand */ ! 696: dbl_value_3.l = *adr_op1_lsw; ! 697: (*test_ptr)(); /* verify the results */ ! 698: if( force_loop ) ! 699: run_code(); /* start the error loop */ ! 700: index++; /* bump the data index */ ! 701: } ! 702: } ! 703: ! 704: ! 705: ! 706: ! 707: /******************************************************************* ! 708: * REGISTER + BYTE DISPLACEMENT DEFERRED ADDRESSING: ! 709: * instruction = <op-code> <b4> <(&ptr_to_op_1 -r4)> ! 710: * { <b5> <(&ptr_to_op_1 -r5)>} ! 711: *******************************************************************/ ! 712: tst_r_bd() ! 713: { ! 714: fill_reg_buf( load_regs ); /* set data for registers */ ! 715: fill_reg_buf( exp_regs ); /* set data for registers */ ! 716: addr_mode = ADR_REG_B_DEF; ! 717: addr_code = 0xb4; /* addr 1 is offset by r4 */ ! 718: addr_code2 = 0xb5; /* addr 2 is offset by r5 */ ! 719: addr_size = 1; /* 1 byte operand */ ! 720: addr_1 = 20; /* set the 1st byte offset */ ! 721: addr_2 = 4; /* set the 2nd byte offset */ ! 722: pack_inst(); /* pack the instr. code */ ! 723: load_regs[4] = (int) adr_op1_ptr - 20; /* get the reg value */ ! 724: load_regs[5] = (int) adr_op2_ptr - 4; ! 725: exp_regs[4] = load_regs[4]; ! 726: exp_regs[5] = load_regs[5]; ! 727: if( no_ops == 2 ) ! 728: min_shift = 12; ! 729: else ! 730: min_shift = 14; ! 731: index = 0; ! 732: for( shift_count = 15; shift_count >= min_shift; shift_count-- ) ! 733: { ! 734: get_current_data(); ! 735: *adr_op1 = dbl_value_1.m; /* set the 1st operand */ ! 736: *adr_op1_lsw = dbl_value_1.l; ! 737: *adr_op2 = dbl_value_2.m; /* set the 2nd operand */ ! 738: *adr_op2_lsw = dbl_value_2.l; ! 739: get_exp_faults( 4, 5, 6, 8 ); /* set exp fault cnt */ ! 740: run_code(); /* execute the instruction */ ! 741: dbl_value_3.m = *adr_op1; /* get the final operand */ ! 742: dbl_value_3.l = *adr_op1_lsw; ! 743: (*test_ptr)(); /* verify the results */ ! 744: if( force_loop ) ! 745: run_code(); /* start the error loop */ ! 746: index++; /* bump the data index */ ! 747: } ! 748: } ! 749: ! 750: ! 751: ! 752: /******************************************************************* ! 753: * REGISTER + WORD DISPLACEMENT DEFERRED ADDRESSING: ! 754: * instruction = <op-code> <d4> <(word &ptr_to_op_1 -r4)> ! 755: * { <d5> <(word &ptr_to_op_1 -r5)> } ! 756: *******************************************************************/ ! 757: tst_r_wd() ! 758: { ! 759: fill_reg_buf( load_regs ); /* set data for registers */ ! 760: fill_reg_buf( exp_regs ); /* set data for registers */ ! 761: addr_mode = ADR_REG_W_DEF; ! 762: addr_code = 0xd4; /* addr 1 is offset by r4 */ ! 763: addr_code2 = 0xd5; /* addr 2 is offset by r5 */ ! 764: addr_size = 2; /* word (2 byte) operand */ ! 765: addr_1 = 511; /* set the 1st word offset */ ! 766: addr_2 = 601; /* set the 2nd word offset */ ! 767: pack_inst(); /* pack the instr. code */ ! 768: load_regs[4] = (int) adr_op1_ptr - 511; /* get the reg value */ ! 769: load_regs[5] = (int) adr_op2_ptr - 601; ! 770: exp_regs[4] = load_regs[4]; ! 771: exp_regs[5] = load_regs[5]; ! 772: if( no_ops == 2 ) ! 773: min_shift = 10; ! 774: else ! 775: min_shift = 13; ! 776: index = 0; ! 777: for( shift_count = 15; shift_count >= min_shift; shift_count-- ) ! 778: { ! 779: get_current_data(); ! 780: *adr_op1 = dbl_value_1.m; /* set the 1st operand */ ! 781: *adr_op1_lsw = dbl_value_1.l; ! 782: *adr_op2 = dbl_value_2.m; /* set the 2nd operand */ ! 783: *adr_op2_lsw = dbl_value_2.l; ! 784: get_exp_faults( 4, 5, 6, 8 ); /* set exp fault cnt */ ! 785: run_code(); /* execute the instruction */ ! 786: dbl_value_3.m = *adr_op1; /* get the final operand */ ! 787: dbl_value_3.l = *adr_op1_lsw; ! 788: (*test_ptr)(); /* verify the results */ ! 789: if( force_loop ) ! 790: run_code(); /* start the error loop */ ! 791: index++; /* bump the data index */ ! 792: } ! 793: } ! 794: ! 795: ! 796: ! 797: ! 798: /******************************************************************* ! 799: * REGISTER + LONGWORD DISPLACEMENT DEFERRED ADDRESSING: ! 800: * instruction = <op-code> <f4> <(longword &ptr_to_op_1 -r4)> ! 801: * { <f5> <(longword &ptr_to_op_1 -r5)> } ! 802: *******************************************************************/ ! 803: tst_r_ld() ! 804: { ! 805: fill_reg_buf( load_regs ); /* set data for registers */ ! 806: fill_reg_buf( exp_regs ); /* set data for registers */ ! 807: addr_mode = ADR_REG_L_DEF; ! 808: addr_code = 0xf4; /* addr 1 is offset by r4 */ ! 809: addr_code2 = 0xf5; /* addr 2 is offset by r5 */ ! 810: addr_size = 4; /* longword (4 byte) op. */ ! 811: addr_1 = (int) adr_op1_ptr - 123; /* set the 1st byte offset */ ! 812: addr_2 = (int) adr_op2_ptr - 212; /* set the 2nd byte offset */ ! 813: pack_inst(); /* pack the instr. code */ ! 814: load_regs[4] = 123; /* reg 4 = 123 */ ! 815: load_regs[5] = 212; /* reg 5 = 212 */ ! 816: exp_regs[4] = load_regs[4]; ! 817: exp_regs[5] = load_regs[5]; ! 818: if( no_ops == 2 ) ! 819: min_shift = 6; ! 820: else ! 821: min_shift = 11; ! 822: index = 0; ! 823: for( shift_count = 15; shift_count >= min_shift; shift_count-- ) ! 824: { ! 825: get_current_data(); ! 826: *adr_op1 = dbl_value_1.m; /* set the 1st operand */ ! 827: *adr_op1_lsw = dbl_value_1.l; ! 828: *adr_op2 = dbl_value_2.m; /* set the 2nd operand */ ! 829: *adr_op2_lsw = dbl_value_2.l; ! 830: get_exp_faults( 4, 5, 6, 8 ); /* set exp fault cnt */ ! 831: run_code(); /* execute the instruction */ ! 832: dbl_value_3.m = *adr_op1; /* get the final operand */ ! 833: dbl_value_3.l = *adr_op1_lsw; ! 834: (*test_ptr)(); /* verify the results */ ! 835: if( force_loop ) ! 836: run_code(); /* start the error loop */ ! 837: index++; /* bump the data index */ ! 838: } ! 839: } ! 840: ! 841: ! 842: ! 843: /******************************************************************* ! 844: * FRAME POINTER DEFERRED + LONGWORD INDEX ADDRESSING: ! 845: * instruction = <op-code> <44> <6d> { <45> <6d> } ! 846: * ! 847: * The indeces used will be either quadword indeces ( for DBL operands ) ! 848: * of longword indeces ( for SGL operands ). ! 849: * ! 850: * NOTE: ! 851: * dmp_op_2 is exactly 4 pages away from dmp_op_1. (200 hex quadwords) ! 852: * IF THIS RELATIVE DISPLACEMENT IS CHANGED THEN THE R5 INDEX MUST ! 853: * BE CHANGED IN THIS CODE!!! ( used by CMPF2 & CMPD2 ) ! 854: *******************************************************************/ ! 855: tst_x_fpd() ! 856: { ! 857: fill_reg_buf( load_regs ); /* set data for registers */ ! 858: fill_reg_buf( exp_regs ); /* set data for registers */ ! 859: addr_mode = ADR_I_FP_DEF; ! 860: addr_code = 0x44; /* code for reg. 4 index */ ! 861: addr_code2 = 0x45; /* code for reg. 5 index */ ! 862: addr_codeB = 0x6d; /* code for FP deferred */ ! 863: addr_size = 0; /* no addr. field per se */ ! 864: pack_inst(); /* pack the instr. code */ ! 865: /* ! 866: * set the frame pointer to 'operand 1 - 16 bytes' (2 quad-words) ! 867: */ ! 868: asm("movl _adr_op1,_sgl_dummy1"); /* get the addr of op 1 */ ! 869: load_regs[13] = sgl_dummy1-16; /* SP = op 1's addr - 16 */ ! 870: exp_regs[13] = load_regs[13]; ! 871: if( sgl_op ) ! 872: { ! 873: load_regs[4] = 4; /* SP to op_1 (longwords) */ ! 874: load_regs[5] = 0x404; /* SP to op_2 (longwords) */ ! 875: } else { ! 876: load_regs[4] = 2; /* SP to op_1 (quadwords) */ ! 877: load_regs[5] = 0x202; /* SP to op_2 (quadwords) */ ! 878: } ! 879: exp_regs[4] = load_regs[4]; ! 880: exp_regs[5] = load_regs[5]; ! 881: if( no_ops == 2 ) ! 882: min_shift = 12; ! 883: else ! 884: min_shift = 14; ! 885: index = 0; ! 886: for( shift_count = 15; shift_count >= min_shift; shift_count-- ) ! 887: { ! 888: get_current_data(); ! 889: *adr_op1 = dbl_value_1.m; /* set the 1st operand */ ! 890: *adr_op1_lsw = dbl_value_1.l; ! 891: *adr_op2 = dbl_value_2.m; /* set the 2nd operand */ ! 892: *adr_op2_lsw = dbl_value_2.l; ! 893: get_exp_faults( 3, 4, 4, 6 ); /* set exp fault cnt */ ! 894: run_code(); /* execute the instruction */ ! 895: dbl_value_3.m = *adr_op1; /* get the final operand */ ! 896: dbl_value_3.l = *adr_op1_lsw; ! 897: (*test_ptr)(); /* verify the results */ ! 898: if( force_loop ) ! 899: run_code(); /* start the error loop */ ! 900: index++; /* bump the data index */ ! 901: } ! 902: } ! 903: ! 904: ! 905: ! 906: /******************************************************************* ! 907: * INDEXED LONGWORD DISPLACEMENT ADDRESSING: ! 908: * instruction = <op-code> <44> <ef> <longword offset> ! 909: * { <45> <ef> <longword offset> } ! 910: *******************************************************************/ ! 911: tst_x_l() ! 912: { ! 913: fill_reg_buf( load_regs ); /* set data for registers */ ! 914: fill_reg_buf( exp_regs ); /* set data for registers */ ! 915: addr_mode = ADR_I_L; ! 916: addr_code = 0x44; /* code for reg. 4 index */ ! 917: addr_code2 = 0x45; /* code for reg. 5 index */ ! 918: addr_codeB = 0xef; /* code for longword disp */ ! 919: addr_size = 4; /* longword (4 byte) op. */ ! 920: if( sgl_op ) ! 921: { ! 922: load_regs[4] = 4; /* reg 4 = 4 (longwords) */ ! 923: load_regs[5] = 6; /* reg 5 = 6 (longwords) */ ! 924: } else { ! 925: load_regs[4] = 2; /* reg 4 = 2 (quadwords) */ ! 926: load_regs[5] = 3; /* reg 5 = 3 (quadwords) */ ! 927: } ! 928: exp_regs[4] = load_regs[4]; ! 929: exp_regs[5] = load_regs[5]; ! 930: if( no_ops == 2 ) ! 931: min_shift = 4; ! 932: else ! 933: min_shift = 10; ! 934: index = 0; ! 935: for( shift_count = 15; shift_count >= min_shift; shift_count-- ) ! 936: { ! 937: get_current_data(); ! 938: *adr_op1 = dbl_value_1.m; /* set the 1st operand */ ! 939: *adr_op1_lsw = dbl_value_1.l; ! 940: *adr_op2 = dbl_value_2.m; /* set the 2nd operand */ ! 941: *adr_op2_lsw = dbl_value_2.l; ! 942: get_exp_faults( 3, 4, 4, 6 ); /* set exp fault cnt */ ! 943: addr_1 = os_op1 + 9 - shift_count; /* data's offset */ ! 944: addr_1 -=16; /* -16 bytes (2 Q-words) */ ! 945: addr_2 = os_op2 + 3 - shift_count; /* data's offset */ ! 946: addr_2 -=24; /* -24 bytes (3 Q-words) */ ! 947: pack_inst(); /* pack the instr. code */ ! 948: run_code(); /* execute the instruction */ ! 949: dbl_value_3.m = *adr_op1; /* get the final operand */ ! 950: dbl_value_3.l = *adr_op1_lsw; ! 951: (*test_ptr)(); /* verify the results */ ! 952: if( force_loop ) ! 953: run_code(); /* start the error loop */ ! 954: index++; /* bump the data index */ ! 955: } ! 956: } ! 957: ! 958: ! 959: ! 960: /************************************************************************** ! 961: * Get data for double precision instructions ! 962: **************************************************************************/ ! 963: get_current_data() ! 964: { ! 965: if( no_ops == 2 ) ! 966: { ! 967: dbl_ld_acc = ldd_data[ index +1 ].op_1; ! 968: dbl_value_1 = data_ptr[ index ].op_1; ! 969: dbl_value_2 = data_ptr[ index ].op_2; ! 970: dbl_expected = data_ptr[ index ].exp; ! 971: } ! 972: else ! 973: { ! 974: dbl_ld_acc = data_ptr[ index ].op_1; ! 975: dbl_value_1 = data_ptr[ index ].op_2; ! 976: dbl_expected = data_ptr[ index ].exp; ! 977: } ! 978: } ! 979: ! 980: ! 981: /**************************************************************************** ! 982: * Get the expected number of translation faults ! 983: ****************************************************************************/ ! 984: get_exp_faults( sgl_1, dbl_1, sgl_2, dbl_2 ) ! 985: int sgl_1; /* exp # faults for 1 sgl operand */ ! 986: int dbl_1; /* exp # faults for 1 dbl operand */ ! 987: int sgl_2; /* exp # faults for 2 sgl operands */ ! 988: int dbl_2; /* exp # faults for 2 dbl operands */ ! 989: { ! 990: if( no_ops == 1 ) ! 991: { ! 992: if( sgl_op ) ! 993: exp_page_faults = sgl_1; /* 1 sgl operand */ ! 994: else ! 995: exp_page_faults = dbl_1; /* 1 dbl operand */ ! 996: } else { ! 997: if( sgl_op ) ! 998: exp_page_faults = sgl_2; /* 2 sgl operands */ ! 999: else ! 1000: exp_page_faults = dbl_2; /* 2 dbl operands */ ! 1001: } ! 1002: /* ! 1003: * In DBL compare instructions, the system won't fetch the least significant ! 1004: * half of the operand(s) if the most significant halves are different. ! 1005: */ ! 1006: if( (op_code == CMPD_OP_CODE) && (dbl_value_1.m != dbl_ld_acc.m) || ! 1007: (op_code == CMPD2_OP_CODE) && (dbl_value_1.m != dbl_value_2.m) ) ! 1008: exp_page_faults--; ! 1009: }
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