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Power 6/32 Unix version 1.21

/*	prvreg.h	10/6/82						*/


/*	privileged registers constants (addresses)			*/



	.set	SBR,0			/*system base register		*/
	.set	SLR,1			/*system length reg		*/
	.set	P0BR,2			/*p0 base reg			*/
	.set	P0LR,3			/*p0 length reg			*/
	.set	P1BR,4			/*p1 base reg			*/
	.set	P1LR,5			/*p1 length reg			*/
	.set	P2BR,6			/*p2 base reg			*/
	.set	P2LR,7			/*p2 length reg			*/
	.set	IPL,8			/*int priority level reg	*/
	.set	MME,9			/*memory mgmt enable reg	*/
	.set	TBIA,10			/*trans buf invalidate all	*/
					/*entries			*/
	.set	TBIS,11			/*trans buf invalidate single	*/
					/*entry				*/
	.set	DCK,12			/*data cache key		*/
	.set	CCK,13			/*code cache key		*/
	/*	PSL */			/*program status long word	*/
	/*	PSW */			/*program status word		*/
	.set	PCBB,14			/*process control block base	*/
	.set	ISP,15			/*interrupt stack pointer	*/
	.set	SIRR,16			/*software int request reg	*/
	.set	SISR,17			/*software int summary reg	*/
	.set	SCBB,18			/*system control block base reg	*/
	.set	KSP,19			/*kernel stack pointer reg	*/
	.set	USP,20			/*user stack pointer		*/
	.set	DCB,21
	.set	PACC,23			/*purge (invalidate) all pages	*/
					/*of process in code cache	*/
	.set	P1DC,24			/*purge one page of data cache	*/
	.set	PADC,25			/*purge all the pages of 	*/
					/*process in data cache		*/
	.set	HISR,26			/* Hardware interrupt summary reg  */
	.set	DCR,27			/* Diagnostic control register */
	.set	PDCS,28			/* Purge data cache slot */

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