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Power 6/32 Unix version 1.21

# 1 "temp$.s"





	.set	SBR,0			
	.set	SLR,1			
	.set	P0BR,2			
	.set	P0LR,3			
	.set	P1BR,4			
	.set	P1LR,5			
	.set	P2BR,6			
	.set	P2LR,7			
	.set	IPL,8			
	.set	MME,9			
	.set	TBIA,10			
					
	.set	TBIS,11			
					
	.set	DCK,12			
	.set	CCK,13			
	.set	PCBB,14			
	.set	ISP,15			
	.set	SIRR,16			
	.set	SISR,17			
	.set	SCBB,18			
	.set	KSP,19			
	.set	USP,20			
	.set	DCB,21			
	.set	PACC,23			
					
	.set	P1DC,24			
	.set	PADC,25			
					
	.set	HISR,26			
	.set	DCR,27			
	.set	PDCS,28			
	

 #TAHOE program status longword


	.set  	PSL_C,0x00000001	
	.set  	PSL_V,0x00000002	
	.set  	PSL_Z,0x00000004	
	.set  	Z,0x00000004
	.set  	PSL_N,0x00000008	
	.set  	PSL_T,0x00000010	
	.set  	PSL_I,0x00000020	
	.set	PSL_EN_OVFL,0x20	
	.set	PSL_EN_UNDFL,0x40	
	.set  	PSL_DBL,0x80		
	.set  	PSL_IPL,0x001f0000	
	.set  	PSL_MOD,0x01000000	
	.set  	PSL_IS,0x04000000	
	.set  	PSL_TP,0x40000000	


 # TAHOE page table entry
 #/
	.set  	PG_V,0x8000000
	.set  	PG_PROT,0x78000000
	.set  	PG_M,0x04000000
	.set  	PG_USED,0x02000000
	.set  	PG_NC,0x01000000
	.set  	PG_PFNUM,0x003fffff

	.set  	PG_NOACC,0
	.set  	PG_KR,0x40000000
	.set  	PG_KW,0x60000000
	.set  	PG_URKR,0x50000000
	.set  	PG_URKW,0x70000000
	.set  	PG_UW,0x78000000

 #*	PCB offsets & diagnostic extension to pcb			*/
 #*	PCB is at pcb0							*/


	.set	PCB_SIZE,	 24	
	.set	PCB_KSP,	 0
	.set	PCB_USP,	 4
	.set	PCB_R0,	 	 8
	.set	PCB_R1,	 	 12
	.set	PCB_R2,	 	 16
	.set	PCB_R3,	 	 20
	.set	PCB_R4,	 	 24
	.set	PCB_R5,	 	 28
	.set	PCB_R6,	 	 32
	.set	PCB_R7,	 	 36
	.set	PCB_R8,	 	 40
	.set	PCB_R9,	 	 44
	.set	PCB_R10,	 48
	.set	PCB_R11,	 52
	.set	PCB_R12,	 56
	.set	PCB_R13,	 60
	.set	PCB_PC,	 	 64
	.set	PCB_PSL,	 68
	.set	PCB_P0BR,	 72
	.set	PCB_P0LR,	 76
	.set	PCB_P1BR,	 80
	.set	PCB_P1LR,	 84
	.set	PCB_P2BR,	 88
	.set	PCB_P2LR,	 92
	.set	PCB_ACCM,	 96
	.set	PCB_ACCL,	100
 #*
 #	Diagnostic pcb extension
 #/
	.set	PCB_STAT,	104	



 #*	fundamental constants						*/

 #*
 # fundamental constants of the implementation--
 # cannot be changed easily.
 #/

	.set  	NBPG,1024
	.set  	PGOFSET,(NBPG-1)	
	.set  	PGSHIFT,10		
	.set 	HIGH,0x1f


 #*	SCB offsets							*/
 #*	SCB is at scb							*/

	.set	PFVEC,1*4		
	.set	PRVEC,2*4		
	.set	CLOCKVEC,7*4		
	.set	CRVEC,0xa*4		
	.set	CXVEC,44		
	.set	SIVEC1,0x1e*4 		
					
						
	.set	BEVEC,0x20*4			
	.set	SYSVEC,0x2b*4		
	.set	PINSTVEC,0x2c*4		
	.set	PRIVSVEC,0x2c*4		
	.set	ROVEC,0x2d*4		
	.set	RAVEC,0x2e*4		
	.set	PROTVEC,0x2f*4		
	.set	TRANS,0x30		
	.set	TRANSVEC,0x30*4		
	.set	KSPVEC,0x31*4		
	.set	TRACEVEC,0x32*4		
	.set	BPTVEC,0x33*4		
	.set	ARITHVEC,0x34*4		
	.set	ALIGNVEC,0x35*4			
	.set	FPMVEC,0x37*4		
	.set	IO14VEC,256		
	.set	IO15VEC,320		
	.set	IO16VEC,384		
	.set	IO17VEC,448		

 #*	SPT (system page table) offsets					*/
 #*	SPT is at Sysmap						*/

	.set	SCBPTE,8		
	.set	BUFPTE,12		
	.set	ISPTE,16		
	.set	IS1PTE,20		
	.set	SPTPTE,20		
	.set	SPT1PTE,20		
	.set	IOMAPPTE,24		
	.set	PCBPTE,28		
	.set	U0P0PTE,32		
	.set	U0P1PTE,36		
	.set	U0P2PTE,40		
	.set	U1P0PTE,44
	.set	U1P1PTE,48
	.set	U1P2PTE,52
	.set	U2P0PTE,56
	.set	U2P1PTE,60
	.set	U2P2PTE,64
	.set	U3P0PTE,68
	.set	U3P1PTE,72
	.set	U3P2PTE,76
	.set	U4P0PTE,80
	.set	U4P1PTE,84
	.set	U4P2PTE,88
	.set	U5P0PTE,92
	.set	U5P1PTE,96
	.set	U5P2PTE,100
	.set	U6P0PTE,104
	.set	U6P1PTE,108
	.set	U6P2PTE,112
	.set	U7P0PTE,116		
	.set	U7P1PTE,120		
	.set	U7P2PTE,124		
	.set	IOB0PTE,128		
	.set	IOB1PTE,132
	.set	IOB2PTE,136
	.set	IOB3PTE,140
	.set	IOB4PTE,144
	.set	IOB5PTE,148
	.set	IOB6PTE,152
	.set	IOB7PTE,156		


 #*	trap.h	4.6	81/03/03	*/

 #*
 #* Trap type values
 #/

	.set  	RESADFLT,0		
	.set  	PRIVINFLT,1		
	.set  	RESOPFLT,2		
	.set  	BPTFLT,3		
	.set  	ALIGNFLT,4		
	.set  	SYSCALL,5		
	.set  	ARITHTRAP,6		
	.set  	PROTFLT,7		
	.set  	TRCTRAP,8		
	.set  	TRANSFLT,9		
	.set	DONE,255


 #  Event codes

	.set	RTCLOCK_CODE,7		
	.set	RESOP_CODE,0x2d		
	.set	RESAD_CODE,0x2e		
	.set	ARITH_CODE,0x34		
	.set	FPM_CODE,0x37		
	.set	INTEGER_OVERFLOW,1	


 #  Arithmetic Event types

	.set	INT_OVFL_CODE,1		
	.set	INT_0_DIV_CODE,2	
	.set	FLT_0_DIV_CODE,3	
	.set	FLT_OVFL_CODE,4		
	.set	FLT_UNDFL_CODE,5	


 #  Floating Point Instruction Op-Codes

	.set  LDF_OP_CODE,0x06		
	.set  LDD_OP_CODE,0x07		
	.set  LNF_OP_CODE,0x16		
	.set  LND_OP_CODE,0x17		
	.set  STF_OP_CODE,0x26		
	.set  STD_OP_CODE,0x27		
	.set  CMPF_OP_CODE,0x36		
	.set  CMPD_OP_CODE,0x37		
	.set  CMPF2_OP_CODE,0x46	
	.set  CMPD2_OP_CODE,0x47	
	.set  TSTF_OP_CODE,0x56		
	.set  TSTD_OP_CODE,0x57		
	.set  PUSHD_OP_CODE,0x67	
	.set  CVLF_OP_CODE,0x76		
	.set  CVLD_OP_CODE,0x77		
	.set  CVFL_OP_CODE,0x86		
	.set  CVDL_OP_CODE,0x87		
	.set  LDFD_OP_CODE,0x97		
	.set  CVDF_OP_CODE,0xa6		
	.set  NEGF_OP_CODE,0xb6		
	.set  NEGD_OP_CODE,0xb7		
	.set  ADDF_OP_CODE,0xc6		
	.set  ADDD_OP_CODE,0xc7		
	.set  SUBF_OP_CODE,0xd6		
	.set  SUBD_OP_CODE,0xd7		
	.set  MULF_OP_CODE,0xe6		
	.set  MULD_OP_CODE,0xe7		
	.set  DIVF_OP_CODE,0xf6		
	.set  DIVD_OP_CODE,0xf7		
	.set  SINF_OP_CODE,0x05		
	.set  COSF_OP_CODE,0x15		
	.set  ATANF_OP_CODE,0x25	
	.set  LOGF_OP_CODE,0x35		
	.set  SQRTF_OP_CODE,0x45	
	.set  EXPF_OP_CODE,0x55		
	.set  MULL2_OP_CODE,0x4c	
	.set  MULL3_OP_CODE,0x5c	



 #  Addressing test constants - These must agree with "fpp_defs.h"

	.set ADR_ABSOLUTE,1	
	.set ADR_LITERAL,2	
	.set ADR_IM_B,3		
	.set ADR_IM_W,4		
	.set ADR_IM_L,5		
	.set ADR_B_DSP,6	
	.set ADR_W_DSP,7	
	.set ADR_L_DSP,8	
	.set ADR_B_DSP_DEF,9	
	.set ADR_W_DSP_DEF,10	
	.set ADR_L_DSP_DEF,11	
	.set ADR_REG,12		
	.set ADR_REG_DEF,13	
	.set ADR_FP_DEF,14	
	.set ADR_SP_DEF,15	
	.set ADR_PUSH,16	
	.set ADR_POP,17		
	.set ADR_POP_DEF,18	
	.set ADR_REG_B,19	
	.set ADR_REG_W,20	
	.set ADR_REG_L,21	
	.set ADR_REG_B_DEF,22	
	.set ADR_REG_W_DEF,23	
	.set ADR_REG_L_DEF,24	
	.set ADR_I_FP_DEF,25	
	.set ADR_I_L,26		


 #*************************************************************************

 #	Stuff for the Demand Paging , Events, & Addressing Tests

 #************************************************************************/
	.set SGL,1			
	.set DBL,2			
	.set ENABLE_EVENTS,0x60		
	.set NONE,0			
	.set LOAD,1			
	.set STORE,2			

	.set NO_EVT_HLT,1		
	.set EVT_MSK_HLT,2		
	.set BAD_PSL_HLT,3		
	.set PUSH_CNT_HLT,4		
	.set PUSH_PSL_HLT,5		
	.set PUSH_PC_HLT,6		
	.set BAD_REG_HLT,7		
	.set BAD_ACC_HLT,8		


 # set DMP_PG_0 to the 1st empty page

	.set DMP_PG_0,0x36000
	.set DMP_PG_1,DMP_PG_0+0x400
	.set DMP_PG_2,DMP_PG_1+0x400
	.set DMP_PG_3,DMP_PG_2+0x400
	.set DMP_PG_4,DMP_PG_3+0x400
	.set DMP_PG_5,DMP_PG_4+0x400
	.set DMP_PG_6,DMP_PG_5+0x400
	.set DMP_PG_7,DMP_PG_6+0x400
	.set DMP_PG_8,DMP_PG_7+0x400
	.set DMP_PG_9,DMP_PG_8+0x400
	.set DMP_PG_10,DMP_PG_9+0x400
	.set DMP_PG_11,DMP_PG_10+0x400
	.set DMP_PG_12,DMP_PG_11+0x400
	.set DMP_PG_13,DMP_PG_12+0x400


 # test code space for the address / demand page tests

	.set START_OF_CODE,DMP_PG_1-20	
	.set CODE_BUF_SIZE,40		
	.set END_OF_CODE,START_OF_CODE+CODE_BUF_SIZE


 # data locations used by the event and demand page tests

	.set _dmp_byte_op_1,DMP_PG_1+0x30	
	.set _dmp_byte_op_2,DMP_PG_1+0x50	
	.set _dmp_byte_op_3,DMP_PG_1+0x70	
	.set _dmp_op_1,DMP_PG_3-4		
	.set _dmp_op_1_ptr,DMP_PG_4+0x30	
	.set _dmp_op_2_ptr,DMP_PG_5+0x30	
	.set _dmp_op_2,DMP_PG_7-4		
	.set _dmp_op_3,DMP_PG_8			
	.set _dmp_op_3_ptr,DMP_PG_9+0x30	
	.set _dmp_op_4,DMP_PG_10		
	.set _dmp_op_5,DMP_PG_11		
	.set _sp_minus,DMP_PG_13-4		
	.set _sp_page,DMP_PG_13			
	.set _sp_plus,DMP_PG_13+4		



 #	INIT.X for the Demand Pageing Tests				

 #	This file is a diagnostic version of locore.s.			
 #	It contains the following:					
 #	*system data area = scb, dump buffer, interrupt stack,		
 #	*system page table,user page tables,pcbs,iomap, & io buffers.	
 #									
 #	*system code = interrupt vectors, initialization of system data,
 #	*memory size calculation,initialization of SPT, zeroing of	
 #	*unused memory, & loading of SBR & SLR.				
 #	*								
 #	*at the end of this code, you are ready to go to virtual mode.	
 #	* --- GOOD LUCK!						

 ##########################################################################

 #   6-Mar-85 :  changed to user mode execution
 #  11-Mar-85 :  moved mode changeing from here to RUN_CODE
 #  17-Jul-85 :  added "mtpr" test for fpp/no-fpp wcs
 ##########################################################################




# 1 "./prvreg.h"







	.set	SBR,0			
	.set	SLR,1			
	.set	P0BR,2			
	.set	P0LR,3			
	.set	P1BR,4			
	.set	P1LR,5			
	.set	P2BR,6			
	.set	P2LR,7			
	.set	IPL,8			
	.set	MME,9			
	.set	TBIA,10			
					
	.set	TBIS,11			
					
	.set	DCK,12			
	.set	CCK,13			
				
				
	.set	PCBB,14			
	.set	ISP,15			
	.set	SIRR,16			
	.set	SISR,17			
	.set	SCBB,18			
	.set	KSP,19			
	.set	USP,20			
	.set	DCB,21
	.set	PACC,23			
					
	.set	P1DC,24			
	.set	PADC,25			
					
	.set	HISR,26			
	.set	DCR,27			
	.set	PDCS,28			
# 402 "temp$.s"
	


# 1 "./psl.h"

























# 405 "temp$.s"



# 1 "./pte.h"





























# 408 "temp$.s"
	


# 1 "./pcboffset.h"




 
	.set PCB_KSP,  0
	.set PCB_USP,  4
	.set PCB_R0,   8
	.set PCB_R1,   12
	.set PCB_R2,   16
	.set PCB_R3,   20
	.set PCB_R4,   24
	.set PCB_R5,   28
	.set PCB_R6,   32
	.set PCB_R7,   36
	.set PCB_R8,   40
	.set PCB_R9,   44
	.set PCB_R10,  48
	.set PCB_R11,  52
	.set PCB_R12,  56
	.set PCB_R13,  60
	.set PCB_PC,   64
	.set PCB_PSL,  68
	.set PCB_P0BR,  72
	.set PCB_P0LR,  76
	.set PCB_P1BR,  80
	.set PCB_P1LR,  84
	.set PCB_P2BR,  88
	.set PCB_P2LR,  92



	.set	PCB_STAT,	96	


# 411 "temp$.s"



# 1 "./const.h"


















































# 414 "temp$.s"



# 1 "./scboffset.h"




	.set	PFVEC,4			
	.set	CLOCKVEC,28		
	.set	CRVEC,40		
	.set	CXVEC,44		
	.set	SIVEC1,120		
					
						
	.set	BEVEC,128			
	.set	SYSVEC,172		
	.set	PINSTVEC,176		
	.set	ROVEC,180		
	.set	RAVEC,184		
	.set	PROTVEC,188		

	.set	TRANS,0x30		
	.set	TRANSVEC,192		

	.set	KSPVEC,196		
	.set	TRACEVEC,200		
	.set	BPTVEC,204		
	.set	ARITHVEC,208		
	.set	ALIGNVEC,212		
	.set	FPMVEC,220		
	.set	IO14VEC,256		
	.set	IO15VEC,320		
	.set	IO16VEC,384		
	.set	IO17VEC,448		

# 417 "temp$.s"


# 1 "./sptoffset.h"








	.set	SCBPTE,8		
	.set	BUFPTE,12		
	.set	ISPTE,16		
	.set	IS1PTE,20		
	.set	SPTPTE,20		
	.set	SPT1PTE,20		
	.set	IOMAPPTE,24		
	.set	PCBPTE,28		
	.set	U0P0PTE,32		
	.set	U0P1PTE,36		
	.set	U0P2PTE,40		
	.set	U1P0PTE,44
	.set	U1P1PTE,48
	.set	U1P2PTE,52
	.set	U2P0PTE,56
	.set	U2P1PTE,60
	.set	U2P2PTE,64
	.set	U3P0PTE,68
	.set	U3P1PTE,72
	.set	U3P2PTE,76
	.set	U4P0PTE,80
	.set	U4P1PTE,84
	.set	U4P2PTE,88
	.set	U5P0PTE,92
	.set	U5P1PTE,96
	.set	U5P2PTE,100
	.set	U6P0PTE,104
	.set	U6P1PTE,108
	.set	U6P2PTE,112
	.set	U7P0PTE,116		
	.set	U7P1PTE,120		
	.set	U7P2PTE,124		
	.set	IOB0PTE,128		
	.set	IOB1PTE,132
	.set	IOB2PTE,136
	.set	IOB3PTE,140
	.set	IOB4PTE,144
	.set	IOB5PTE,148
	.set	IOB6PTE,152
	.set	IOB7PTE,156		


# 419 "temp$.s"



# 1 "./trap.h"
















# 422 "temp$.s"





	.set	HIGH,0x1f	
	.set	MCKVEC,4	
	.set	NISP,2		
	.set	DONE,255	
	.set	TTRAP,0x32
	.set	PRIVS,0x2c

	.text

		

# 1 "./pstorage.s"
 #


















_pstore:
	.globl	_pstore
	.space		1024			

_pstore1:				
	.globl	_pstore1		

_pcbb:	.space	4			
	.globl	_isp
_isp:	.space	4			
_sirr:	.space	4			
	.globl	_sisr
_sisr:	.space	4			
	
	.space	4			
	.space	4
	.space	4

_cpmdcb: .space	4			
_cpfdcb: .space	4
_cpcdcb: .space	4
_cpidcb: .space	4
_cpstat: .space	4
_cpctl:  .space	4

	.globl	_hisr
_hisr:	.space	4			
_dcr:	.space	4			

	.space	4*48			

_pstemp:
	.globl	_pstemp			
					
_tr0:	.space	16			
					
_tpc:	.space	4			
_tpsl:	.space	4			
_tsp:	.space	4			
_tksp:	.space	4			
_tusp:	.space	4			
_tcck:	.space	4			
_tdck:	.space	4			
_ttbk:	.space	4			
_tsbr:	.space	4			
_tslr:	.space	4			
_tp0br:	.space	4			
_tp0lr:	.space	4			
_tp1br:	.space	4			
_tp1lr:	.space	4			
_tp2br:	.space	4			
_tp2lr:	.space	4			
_tipl:	.space	4			
_tmme:	.space	4			
_ttbia:	.space	4			
_ttbis:	.space	4			
					
					
_tpcbb:	.space	4			
_tisp:	.space	4			
_tsirr:	.space	4			
_tsisr:	.space	4			
_tscbb:	.space	4			
_tp1cc:	.space	4			
					
_tpacc:	.space	4			
					
_tp1dc:	.space	4			
_tpadc:	.space	4			
_tcpmdcb:
	.space	4			
_tcpfdcb:
	.space	4
_tcpcdcb:
	.space	4
_tcpidcb:
	.space	4
_tcpstat:
	.space	4
_tcpctl:
	.space	4

_probflag:
	.space	4			
_inexcflg:
	.space	4			

	.space	4*10			
_psend:	.globl	_psend			
	.set    MM,(_psend - _pstore1)
	.space  1024 - MM


 #





	.set	PCBB,0x400		#process control block base

	.globl	INTSP
	.set	INTSP,0x404		#Interrupt stack pointer
	.set	SIRR,0x408		#Software interrupt request

	.globl	SSR
	.set	SSR,0x40C		#Software interrupt summary

	.globl	HSR
	.set	HSR,0x410		#Hardware interrupt summary

	.set	SBB,0x414		#Pointer to system control block base
	.set	TBCR,0x418		#Current value of hardware TBCR
	.set	CPMDCB,0x420		#pointer to CP master DCB
	.set	CPCTL,0x424		#CPU control word
	.set	CPREQ,0x428		#CPU request
	.set	CPRUN,0x42C		#CPU run status (8 = step mode)
	.set	CPRSW,0x430		#CP interrupt request word
	.set	PSL,0x434		#Software Process Status Longword
	.set	TVAPR,0x5E8		#saved vapr register
	.set	TRA,0x5EC		#
	.set	TLSP,0x5F0		#
	.set	TIAR,0x5F4		#
	.set	TLIA,0x5F8		#
	.set	TQ,0x5FC		#
	.set	TR0,0x600		#decellerated processor registers
	.set	TR1,0x604		#decellerated processor registers
	.set	TR2,0x608		#decellerated processor registers
	.set	TR3,0x60C		#decellerated processor registers
	.set	TR4,0x610		#decellerated processor registers
	.set	TR5,0x614		#decellerated processor registers
	.set	TR6,0x618		#decellerated processor registers
	.set	TR7,0x61C		#decellerated processor registers
	.set	TR8,0x620		#decellerated processor registers
	.set	TR9,0x624		#decellerated processor registers
	.set	TR10,0x628		#decellerated processor registers
	.set	TR11,0x62C		#decellerated processor registers
	.set	TR12,0x630		#decellerated processor registers
	.set	TR13,0x634		#decellerated processor registers
	.set	TR14,0x638		#decellerated processor registers
	.set	TR15,0x63C		#decellerated processor registers
	.set	TPC,0x640		#decellerated program counter
	.set	TPSL,0x644		#decellerated process status longword
	.set	TSP,0x648		#decellerated stack pointer
	.set	TKSP,0x64C		#decellerated kernel stack pointer
	.set	TUSP,0x650		#decellerated user stack pointer
	.globl	TCCK
	.set	TCCK,0x654		#decellerated Code cache key
	.globl	TDCK
	.set	TDCK,0x658		#decellerated data cache key
	.set	TTBK,0x65C		#decellerated translation buffer key
	.set	TSBR,0x660		#decellerated System Base Register
	.set	TSLR,0x664		#decellerated System length register
	.set	TP0BR,0x668		#decellerated P0 base register
	.set	TP0LR,0x66C		#decellerated P0 length register
	.set	TP1BR,0x670		#decellerated P1 base register
	.set	TP1LR,0x674		#decellerated P1 length register
	.set	TP2BR,0x678		#decellerated P2 base register
	.set	TP2LR,0x67C		#decellerated P1 length register
	.set	TIPL,0x680		#decellerated Interrupt priority level
	.set	TMME,0x684		#decellerated Memory management enable
	.set	TTBIA,0x68C		#decellerated translation buffer invalid
	.set	TTBIS,0x68C		#decellerated transl buffer invalid single
	.set	TPCBB,0x690		#decellerated Process control block base
	.set	TISP,0x694		#decellerated Interrupt stack pointer
	.set	TSIRR,0x698		#decellerated Software interrupt request
	.set	TSISR,0x69C		#decellerated Software interrupt summary
	.set	TSCBB,0x6A0		#decellerated System control block base
	.set	TP1CC,0x6A4		#decellerated 
	.set	TPACC,0x6A8		#decellerated
	.set	TP1DC,0x6AC		#decellerated
	.set	TPADC,0x6B0		#decellerated
	.set	TCPMDCB,0x6B4		#decellerated address of master DCB
	.set	PROBFLG,0x6B8		#decellerated
	.set	INEXCFLG,0x6BC		#decellerated
	.set	PCTYPFLG,0x6C0		#
	.set	NOOFPARS,0x6C4		#
	.set	STKPAR1,0x6C8		#
	.set	STKPAR2,0x6CC		#
	.set	JMPVEC,0x6D0		#
	.set	PSEND,0x7FC		#
# 438 "temp$.s"

	.globl	_Entry
_Entry:
	jmp	start
	.space	(1024-6)




				


	.set	NLWU,35		
				
				
				
	.globl	_Codek
_Codek:	.long	0		

	.globl	_restart
_restart:
	.space	4		
				
				
					
	.globl	_maxmem
_maxmem:
	.space	4		

	.globl	_maxpages
_maxpages:
	.space	4		

	.globl	_lastadd
_lastadd:
	.space	4		

	.globl	_unused
_unused:
	.space	4		

	.globl	_ctlblk
_ctlblk:
	.long	0		

	.globl	_savvec0	
_savvec0:
	.space	4

	.globl	_savvec1	
_savvec1:
	.space	4

	.globl	_savvec2	
_savvec2:
	.space	4

	.globl	_savvec3	
_savvec3:
	.space	4

	.globl	_savvec4	
_savvec4:
	.space	4

	.globl	_savvec5	
_savvec5:
	.space	4
	.globl	_savvec6	
_savvec6:
	.space	4
	.globl	_savvec7	
_savvec7:
	.space	4

	.globl	_savvec8	
_savvec8:
	.space	4

	.globl	_r_no
_r_no:
	.long	0
	.globl	_pt_base
_pt_base:
	.long	0
	.globl	_saved_psl
_saved_psl:
	.long   0
	.globl	_saved_sp
_saved_sp:
	.long	0
	.globl	_saved_fp
_saved_fp:
	.long	0
	.globl	_ret_adr
_ret_adr:
	.long	0
	.globl	_exp_par0
_exp_par0:
	.long	0
	.globl	_exp_par1
_exp_par1:
	.long	0
	.globl	_f_vaddr
_f_vaddr:
	.long	0			

	.globl	_f_ptr
_f_ptr:
	.long   0			
	.globl	_df_cnt
_df_cnt:
	.long	0			

	.globl	_if_cnt
_if_cnt:
	.long	0			

	.globl	_newepc
_newepc:
	.long	0

	.globl	_errcnt
_errcnt:
	.long	0

	.globl	_clk_cnt
_clk_cnt:
	.long	0

	.globl	_ttcnt
_ttcnt:
	.long	0			
	.globl	_trcnt
_trcnt:
	.long	0			

	.globl	_Ufpte
_Ufpte: .long	0
	.globl	_Ulpte
_Ulpte: .long	0

	.globl	_dbuf		
_dbuf:
	.space		1024 - (NLWU *4)
edbuf:


	.globl	_intstack	
_intstack:			
	.space	NISP*	1024
eintstack:


	.set	SYSPTSIZE,512	
 


 
	.align	2
	.globl	_Sysmap
_Sysmap:
	.space	SYSPTSIZE*4 	
eSysmap:
	.globl	_Syssize
	.set	_Syssize,(eSysmap-_Sysmap)/4	
	
	.globl	_iomap		
_iomap:	.space	1024		
	.globl	_eiomap
_eiomap:

	.globl	_pcb0		
_pcb0:	.space	128		
	.globl	_pcb1
_pcb1:	.space 128		
	.globl	_pcb2
_pcb2:	.space 128		
	.globl	_pcb3
_pcb3:	.space 128		
	.globl	_pcb4
_pcb4:	.space 128		
	.globl	_pcb5
_pcb5:	.space 128		
	.globl	_pcb6
_pcb6:	.space 128		
	.globl	_pcb7
_pcb7:	.space 128		





	.align	2
	.globl	_u0p0pt
_u0p0pt:
	.space	1024		
	.globl	_u0p1pt
_u0p1pt:	
	.space	1024		
	.globl	_u0p2pt
_u0p2pt:	
	.space	1020		
eu0p2pt:
	.space	4





	.align	2
	.globl	_u1p0pt
_u1p0pt:
	.space	1024		
	.globl	_u1p1pt
_u1p1pt:	
	.space	1024		
	.globl	_u1p2pt
_u1p2pt:	
	.space	1020		
eu1p2pt:
	.space	4






	.align	2
	.globl	_u2p0pt
_u2p0pt:
	.space	1024		
	.globl	_u2p1pt
_u2p1pt:	
	.space	1024		
	.globl	_u2p2pt
_u2p2pt:	
	.space	1020		
eu2p2pt:
	.space	4






	.align	2
	.globl	_u3p0pt
_u3p0pt:
	.space	1024		
	.globl	_u3p1pt
_u3p1pt:	
	.space	1024		
	.globl	_u3p2pt
_u3p2pt:	
	.space	1020		
eu3p2pt:
	.space	4





	.globl	_u4p0pt
_u4p0pt:
	.space	(9*	1024) - 4
eu6p2pt:
	.space	4






	.align	2
	.globl	_Kstack		
_Kstack:			
	.space	3*	1024
	.globl	ekstack	
ekstack:


	.globl	_iob0		
_iob0:	.space	1024
	.globl	_iob1		
_iob1:	.space	1024
	.globl	_iob2		
_iob2:	.space	1024
	.globl	_iob3		
_iob3:	.space	1024
	.globl	_iob4		
_iob4:	.space	1024
	.globl	_iob5		
_iob5:	.space	1024
	.globl	_iob6		
_iob6:	.space	1024
esysdata:



# 1 "./scblock.s"

 #


	.align	2
	.globl	_scb
_scb:







	.long	_Xunknown;			.long	_Xpowerfail;	
	.long	_Xunknown;		.long	_Xunknown;
	.long	_Xunknown;		.long	_Xunknown;
	.long	_Xunknown;			.long	_Xhardclock;
	.long	_Xunknown;		.long	_Xunknown;		
		.long	_Xcnrint;		.long	_Xcnxint;
	.long	_Xunknown;		.long	_Xunknown;		
	.long	_Xunknown;		.long	_Xunknown;
		.long	_Xs15;		.long	_Xs14;	
		.long	_Xs13;		.long	_Xs12;
		.long	_Xs11;		.long	_Xs10;	
		.long	_Xs9;		.long	_Xs8;
		.long	_Xs7;		.long	_Xs6;	
		.long	_Xs5;		.long	_Xs4;
		.long	_Xs3;		.long	_Xs2;	
		.long	_Xs1;	.long	_Xunknown;
		.long	_Xbuserror;	.long	_Xunknown;		
	.long	_Xunknown;		.long	_Xunknown;
	.long	_Xunknown;		.long	_Xunknown;		
	.long	_Xunknown;		.long	_Xunknown;
	.long	_Xunknown;		.long	_Xunknown;		
	.long	_Xunknown;			.long	_Xkcall;
		.long	_Xprvinflt;		.long	_Xresopflt;	
		.long	_Xresadflt;		.long	_Xprotflt;
		.long	_Xtransflt;		.long	_Xkspnotval;	
		.long	_Xtracep;		.long	_Xbptflt;
		.long	_Xarithtrap;		.long	_Xalignflt;	
	.long	_Xunknown;			.long	_Xfpp_emulate;
	.long	_Xunknown;		.long	_Xunknown;		
	.long	_Xunknown;		.long	_Xunknown;
	.long	_Xunknown;		.long	_Xunknown;		
	.long	_Xunknown;		.long	_Xunknown;
		.long	_Xiovec14;	.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;	
		.long	_Xiovec15; 	.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;	
		.long	_Xiovec16; 	.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;	
		.long	_Xiovec17; 	.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;.long	_Xunknown;	

	.space	512		


# 738 "temp$.s"




# 1 "./evthandlers.s"


 



































	.align 2  		     	.globl _Xunknown 			_Xunknown:
	pushl 	$0
	callf	$8,_XTrap
	halt












	.align 2  		     	.globl _Xpowerfail 			_Xpowerfail:
	pushl 	$1
	callf	$8,_XTrap
	halt






	.align 2  		     	.globl _Xhardclock 			_Xhardclock:
	incl	_clock_event	
	rei





	.align 2  		     	.globl _Xcnrint 			_Xcnrint:
	pushl 	$0xa
	callf	$8,_XTrap
	halt




	.align 2  		     	.globl _Xcnxint 			_Xcnxint:
	rei		




	.align 2  		     	.globl _Xs15 			_Xs15:
	pushl 	$0x10
	callf	$8,_XTrap
	halt




	.align 2  		     	.globl _Xs14 			_Xs14:
	pushl 	$0x11
	callf	$8,_XTrap
	halt




	.align 2  		     	.globl _Xs13 			_Xs13:
	pushl 	$0x12
	callf	$8,_XTrap
	halt




	.align 2  		     	.globl _Xs12 			_Xs12:
	pushl 	$0x13
	callf	$8,_XTrap
	halt




	.align 2  		     	.globl _Xs11 			_Xs11:
	pushl 	$0x14
	callf	$8,_XTrap
	halt




	.align 2  		     	.globl _Xs10 			_Xs10:
	pushl 	$0x15
	callf	$8,_XTrap
	halt




	.align 2  		     	.globl _Xs9 			_Xs9:
	pushl 	$0x16
	callf	$8,_XTrap
	halt




	.align 2  		     	.globl _Xs8 			_Xs8:
	pushl 	$0x17
	callf	$8,_XTrap
	halt




	.align 2  		     	.globl _Xs7 			_Xs7:
	pushl 	$0x18
	callf	$8,_XTrap
	halt




	.align 2  		     	.globl _Xs6 			_Xs6:
	pushl 	$0x19
	callf	$8,_XTrap
	halt




	.align 2  		     	.globl _Xs5 			_Xs5:
	pushl 	$0x1a
	callf	$8,_XTrap
	halt




	.align 2  		     	.globl _Xs4 			_Xs4:
	pushl 	$0x1b
	callf	$8,_XTrap
	halt




	.align 2  		     	.globl _Xs3 			_Xs3:
	pushl 	$0x1c
	callf	$8,_XTrap
	halt




	.align 2  		     	.globl _Xs2 			_Xs2:
	pushl 	$0x1d
	callf	$8,_XTrap
	halt




	.align 2  		     	.globl _Xs1 			_Xs1:
	pushl 	$0x1e
	callf	$8,_XTrap
	halt





	.align 2  		     	.globl _Xiovec14 			_Xiovec14:
	halt
	.align 2  		     	.globl _Xiovec15 			_Xiovec15:
	halt
	.align 2  		     	.globl _Xiovec16 			_Xiovec16:
	halt
	.align 2  		     	.globl _Xiovec17 			_Xiovec17:
	halt


















	.align 2  		     	.globl _Xbuserror 			_Xbuserror:
	pushl 	$0x20
	callf	$8,_XTrap
	halt











	.align 2  		     	.globl _Xkspnotval 			_Xkspnotval:
	pushl 	$0x31
	callf	$8,_XTrap
	halt


 


	.align 2  		     	.globl _Xprvinflt 			_Xprvinflt:
	movpsl	_psl_val		
	mtpr	$0x1f,$IPL		
	bitl $PSL_DBL,_psl_val  	
	beql 1f 
	std	_post_evt_acc		
	brb	2f
1:	stf	_post_evt_acc		
2:	storer 	$0x1fff,_store_regs  	
	moval	(r13),_post_event_fp	
	moval	(r14),_post_event_sp	
	pushl 	$0x2c
	callf	$8,_XTrap
	halt






	.align 2  		     	.globl _Xresopflt 			_Xresopflt:
 	mtpr $0x1f,$IPL   
 	movpsl _psl_val  		
	bitl $PSL_DBL,_psl_val  	
	beql 1f 
	std _post_evt_acc  		
	brw  2f
1:	stf _post_evt_acc  		
	clrl _post_evt_acc+4 
2:
	storer $0x1fff,_store_regs  	
	moval (r13),_post_event_fp	
	moval (r14),_post_event_sp	
	pushl 	$0x2d
	callf	$8,_XTrap
	halt


	.align 2  		     	.globl _Xresadflt 			_Xresadflt:
	movpsl	_psl_val		
	mtpr	$0x1f,$IPL		
	bitl $PSL_DBL,_psl_val  	
	beql 1f 
	std	_post_evt_acc		
	brb	2f
1:	stf	_post_evt_acc		
2:	storer 	$0x1fff,_store_regs  	
	moval	(r13),_post_event_fp	
	moval	(r14),_post_event_sp	
	pushl 	$0x2e
	callf	$8,_XTrap
	halt

	.align 2  		     	.globl _Xbptflt 			_Xbptflt:
	pushl 	$0x33
	callf	$8,_XTrap
	halt

	.align 2  		     	.globl _Xtracep 			_Xtracep:
	movpsl	_psl_val		
	mtpr	$0x1f,$IPL		
	bitl $PSL_DBL,_psl_val  	
	beql 1f 
	std	_post_evt_acc		
	brb	2f
1:	stf	_post_evt_acc		
2:	storer 	$0x1fff,_store_regs  	
	pushl 	$0x32
	callf	$8,_XTrap
	halt






	.align 2  		     	.globl _Xarithtrap 			_Xarithtrap:
 	mtpr $0x1f,$IPL   
 	movpsl _psl_val  		
	bitl $PSL_DBL,_psl_val  	
	beql 1f 
	std _post_evt_acc  		
	brw  2f
1:
	stf _post_evt_acc  		
	clrl _post_evt_acc+4 
2:
	storer 	$0x1fff,_store_regs  	
	moval	(r13),_post_event_fp	
	moval	(r14),_post_event_sp	
	pushl 	$0x34
	callf	$8,_XTrap
	halt


	.align 2  		     	.globl _Xprotflt 			_Xprotflt:			
	movpsl	_psl_val		
	moval	(r14),_post_event_sp	
	pushl 	$0x2f
	callf	$8,_XTrap
	halt
	.align 2  		     	.globl _Xtransflt 			_Xtransflt:
	pushl 	$0x30
	callf	$8,_XTrap
	halt
	.align 2  		     	.globl _Xalignflt 			_Xalignflt:
	movpsl	_psl_val		
	mtpr	$0x1f,$IPL		
	bitl $PSL_DBL,_psl_val  	
	beql 1f 
	std	_post_evt_acc		
	brb	2f
1:	stf	_post_evt_acc		
2:	storer 	$0x1fff,_store_regs  	
	pushl 	$0x35
	callf	$8,_XTrap
	halt
	.align 2  		     	.globl _Xfpp_emulate 			_Xfpp_emulate:			
	movpsl	_psl_val		
	movl	_psl_val,_post_event_psl   
	storer 	$0x1fff,_store_regs  	
	moval	(r13),_post_event_fp	
	moval	(r14),_post_event_sp	
	movl	(sp),_fpm_ms_op		
	movl	4(sp),_fpm_ls_op	
	movl	8(sp),_fpm_op_code	
	movl	12(sp),_fpm_pc		
	movl	16(sp),_fpm_psl		
	bitl $PSL_DBL,_psl_val  	
	beql 1f 
	std	_post_evt_acc		
	brb	2f
1:	stf	_post_evt_acc		
	clrl	_post_evt_acc+4
2:
	pushl	$0x37
	callf	$8,_XTrap
	halt

alltraps:
	halt

	.align 2  		     	.globl _Xkcall 			_Xkcall:			
	pushl 	$0x2b
	callf	$8,_XTrap
	halt


# 742 "temp$.s"





 #	*INITIALIZATION CODE
 #	*
 #	* MME off; mode = k; IPL = 31; IS = 1
 #	*

	
	.globl	start
start:
	mtpr	$0,$MME		
	movl	r0,_run_list
	movl	r1,_OPTIONS
	clrl	_nonstop	
	movl	r2,_count	
	bneq	1f		
	movl	$1,_count	
1:	bgeq	1f		
	movl	$1,_nonstop	
1:
	mtpr	$0x400,$DCR	
	tstl	r1		
	bneq	1f
	movl	$1,_no_fpp_wcs	
1:
	movab	_scb,r0
	andl2	$0x3ffffc00,r0
	mtpr	r0,$SCBB	
	mtpr	$0x1f,$IPL	

	andl3	$4,r11,_ss1	


 # clear the option flags

	clrl	_halt_flg	
	clrl	_loop_on_err	
	movl	$1,_prt_error	
	movl	$1,_prt_hdrs	
	movl	$1,_en_data_cache  
	movl	$1,_user_mode	
	clrl	_exp_event	
	clrl	_event_return	
	clrl	_unexp_event_ret 


 # set the option flags as needed

	bitl	$1,_OPTIONS	
	beql	1f
	movl	$1,_halt_flg	
1:
	bitl	$2,_OPTIONS	
	beql	1f
	movl	$1,_loop_on_err	
1:
	bitl	$4,_OPTIONS	
	beql	1f
	clrl	_prt_error	
1:
	bitl	$8,_OPTIONS	
	beql	1f
	clrl	_prt_hdrs	
1:
	bitl	$16,_OPTIONS	
	beql	1f
	clrl	_en_data_cache	
1:
	bitl	$32,_OPTIONS	
	beql	1f
	clrl	_user_mode	
1:
	movpsl	r1
	andl2	$0xffffff00,r1		
	cmpl	r1,$0x041f0000		
	beql	1f
2:	movl	$1,r0
	movl	$0x041f0000,r2
	halt			
1:
	movl	$_intstack+NISP*	1024,r0
	andl2	$0x3fffffff,r0		
	mtpr	r0,$ISP			
	movl	r0,sp			
	movab	(sp),fp			

 #	Clear system data area all the way upto system code
 #	this includes dump buffer,interrupt stack,spt,iomap,pcbs,user 
 #	page tables, & io buffer area.

3:	
	movab	esysdata,r7
	movab	_restart,r6
1:	clrl	(r6)
	   addl2 $4,r6;  cmpl r6,r7;  bleq 1b;

 #	Initialize System Page Table

5:
	clrl	r2
	movab	esysdata,r1	
	andl2	$0x3fffffff,r1	
	shar	$	10		,r1,r1	
				
1:
	orl3	$	0x80000000|	0x60000000,r2,_Sysmap[r2]
	aoblss	r1,r2,1b


 # 	Map system text area 1 to 1, Kernel read/write.
 #	For this to work, the label _etext must exist at the end 
 #	of system code; Add in 4 more pages for data area used in C

	movab	_Esys,r1	
	andl2	$0x3fffffff,r1
	shar	$	10		,r1,r1
1:
	orl3	$	0x80000000|	0x60000000,r2,_Sysmap[r2]
	aobleq	r1,r2,1b

 #	Map from here to last page used by user :
 #	invalid, User access, & virtual = physical

	movl	r2,_unused	
	movl	r2,_Ufpte		
	movl	$0x80000,r1		
	shar	$	10		,r1,r1
	movl	r1,_Ulpte		

1:
	orl3	$	0x80000000|	0x78000000,r2,_Sysmap[r2]	
	aoblss	r1,r2,1b


 #	Initialize SBR, SLR

sysrdy:
	mtpr	$_Sysmap,$SBR      		
	mtpr	$_Syssize,$SLR
	mtpr	$64,$DCR			

 # 		GO TO VIRTUAL MODE
 #	Double map the kernel into user addresses : 
 #	This will enable system to go to virtual mode the 1st time !!


	orl3	$0xc0000000,$_Sysmap,r0	
	mtpr	r0,$P0BR		
	mtpr	$_Syssize,$P0LR
	mtpr	$1,$PADC		
	mtpr	$1,$TBIA		
	
	mfpr	$SCBB,r0
	movab	_Trans,TRANSVEC(r0)	
	movab	_Prvis,PRIVSVEC(r0)	
	moval	_FPM_handler,FPMVEC(r0)	
	mtpr	$_pcb0,$0xe		
	
	movab	_pcb0,r0
	movab	ekstack,PCB_KSP(r0)	
	movab	eustack,PCB_USP(r0)	
	mfpr	$P0BR,PCB_P0BR(r0)	
	mfpr	$P0LR,PCB_P0LR(r0)	
	movl	$0x001f000,PCB_PSL(r0)	
	ldpctx				

	mtpr	$1,$PACC		
	movl	$1,_Codek
	mtpr	_Codek,$CCK		

	callf	$4,_monitor		



# 1 "./fault_handlers.s"







































	.align	2
	.globl	_Trans
_Trans:
	mtpr	$0x1f,$IPL		
	movl	r0,_trans_r0		
	movl	(sp)+,r0		
	movl	(sp)+,_f_vaddr		
	incl	_no_page_faults		
	tstl	_pipe_test		
	bneq	1f			
	cmpl	(sp),_code_addr		
	beql	1f			
	movl	r0,_pop_val_1		
	movl	_f_vaddr,_pop_val_2	
	movl	(sp),_pop_val_3		
	movl	(sp)+,_pop_val_3	
	callf	$4,_bad_trans_stack	
1:	nop
	shar	$	10		,_f_vaddr,r0	
	orl2	$0x80000000,_Sysmap[r0] 
	mtpr	_f_vaddr,$TBIS



	movl	_no_page_faults,r0
	cmpl	$1,r0
	bneq	1f
	brb	2f			
1:	cmpl	$2,r0
	bneq	1f
	nop
	nop
	brb	2f			
1:	cmpl	$3,r0
	bneq	1f
	nop
	nop
	brb	2f			
1:	cmpl	$4,r0
	bneq	1f
	nop
	nop
	brb	2f			
1:	cmpl	$5,r0
	bneq	1f
	nop
	nop
	brb	2f			
1:	cmpl	$6,r0
	bneq	1f
	nop
	nop
	brb	2f			
1:	cmpl	$7,r0
	bneq	1f
	nop
	nop
	brb	2f			
1:	cmpl	$8,r0
	bneq	1f
	nop
	nop
	brb	2f			
1:	cmpl	$9,r0
	bneq	1f
	nop
	nop
	brb	2f			
	nop				
	nop
2:



	tstl	_pipe_test		
	bneq	1f			
	tstl	_load_type_inst		
	bneq	1f			
	tstl	_force_loop		
	bneq	1f			
	tstl	_trans_acc_error	
	bneq	1f			
	callf	$4,_chk_trans_acc	
1:



	tstl	_i_cache_hit		
	bneq	2f			
	incl	_Codek			
	cmpl	_Codek,$255		
	jlss	1f
	movl	$1,_Codek		
	mtpr	$1,$PACC		
1:
	mtpr	_Codek,$CCK		
2:
	nop
	movl	_trans_r0,r0		
	rei				
 
	.align 	2
_trans_r0:				
	.long	0















	.align	2
	.globl	_Prvis
_Prvis:
	mtpr	$0x1f,$IPL		
	movl	(sp)+,_act_pc		
	movl	(sp)+,_f_ptr		
	cmpl	_act_pc,$_run_code_mtpr	
	bneq	1f
	pushl	_run_code_psl		
	pushl	$_run_code_mtpr		
	rei				
1:
	pushl	_f_ptr			
	pushl	_act_pc			
	pushl	$0x2c			
	callf	$8,_XTrap		



























	.align	2
	.globl	_FPM_handler
_FPM_handler:
	movpsl	_psl_val		
	mtpr	$0x1f,$IPL		
	movl	_psl_val,_post_event_psl   
	storer 	$0x1fff,_store_regs  	
	moval	(r13),_post_event_fp	
	moval	(r14),_post_event_sp	
	movl	$1,_fpm_trap_occurred	
	tstl	_emulated_inst		
	bneq	1f			
	pushl	$FPM_CODE		
	callf	$8,_XTrap
	halt
1:					
	cmpl	_acc_st_size,$DBL	
	beql	1f
	stf	_dbl_st_acc		
	brb	2f
1:	std	_dbl_st_acc		
2:
	movl	(sp)+,_fpm_ms_op	
	movl	(sp)+,_fpm_ls_op	
	movl	(sp)+,_fpm_op_code	
	movl	(sp)+,_fpm_pc		
	movl	(sp)+,_fpm_psl		
	bitl	$PSL_DBL,_psl_val  	
	beql	1f 
	std	_post_evt_acc		
	brb	2f
1:	stf	_post_evt_acc		
	clrl	_post_evt_acc+4
2:
	pushl	_run_code_psl		
	pushl	_event_return		
	rei				

# 919 "temp$.s"


 # 



	.globl	_Esys			
_Esys:
	.space		1024
	
	.globl	_Ustack			
_Ustack:
	.space	(2*	1024)-4		
	.globl	eustack
eustack:
	.long	0			

	.globl	U_area
U_area:

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