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1.1 root 1:
2: #include "dmp_defs.h"
3:
4:
5: /*
6: **************************************************************************
7: *
8: * Test an instruction that has no operands
9: *
10: * This code will test instrucions with no operands. PUSHD is the only
11: * one of these instructions that will store any data.
12: *
13: * 29-Apr-85 added pipeline test
14: * 5-Jun-85 converted from assembler to C code
15: *
16: **************************************************************************
17: */
18: test_0_ops()
19: {
20: if( (precision == SGL) || (op_code == LDFD_OP_CODE) )
21: acc_ld_size = SGL; /* load a single Acc */
22: else
23: acc_ld_size = DBL; /* load a double Acc */
24: if( (precision == SGL) || (op_code == CVDF_OP_CODE) )
25: acc_st_size = SGL; /* store a single Acc */
26: else
27: acc_st_size = DBL; /* store a double Acc */
28: tst_0_no_pipe(); /* test with no pipelineing */
29: if( !no_fpp_wcs ) {
30: tst_0_pipe1(); /* run pipeline test #1 */
31: tst_0_pipe2(); /* run pipeline test #2 */
32: }
33: }
34:
35:
36:
37: /*
38: ****************************************************************************
39: *
40: * NON PIPELINED TEST FOR INSTRUCTIONS WITH NO OPERANDS
41: *
42: ****************************************************************************
43: */
44: tst_0_no_pipe()
45: {
46: pipe_test = FALSE; /* clear the PIPE TEST flg */
47: pack_inst(); /* pack the instr's code */
48: if( op_code == PUSHD_OP_CODE ) /* Push Double instr? */
49: exp_page_faults = 3; /* expect 3 page fault */
50: else
51: exp_page_faults = 1; /* expect 1 page fault */
52: shift_count = 20; /* shift the code 16 bytes */
53: fill_reg_buf( load_regs ); /* set register load data */
54: fill_reg_buf( exp_regs ); /* set expected reg. data */
55: for( index = 0; index <= max_index; index++ ) {
56: dbl_ld_acc = data_ptr[ index ].op_1;
57: dbl_expected = data_ptr[ index ].exp;
58: run_code(); /* execute the instruction */
59: }
60: }
61:
62:
63:
64:
65:
66:
67: /*
68: *************************************************************************
69: *
70: * PIPELINE TEST #1 FOR INSTRUCTIONS WITH NO OPERANDS
71: *
72: * This test will put a LOAD instruction immediately in front of the
73: * test instruction and a MULTIPLY instruction immediately behind it.
74: * The instruction buffer will look like:
75: *
76: * <ldf/ldd> <instruction> <mulf/muld> where:
77: *
78: * The load will be done indirect through register R6
79: * The 2nd multiply addressing mode will be indirect through register R2.
80: *************************************************************************
81: */
82: tst_0_pipe1()
83: {
84: pipe_test = 1; /* set pipelined test flag to pipe test #2 */
85: if( acc_ld_size == DBL )
86: pipe_inst1 = LDD_OP_CODE;
87: else
88: pipe_inst1 = LDF_OP_CODE;
89: if( acc_st_size == DBL )
90: pipe_inst2 = MULD_OP_CODE;
91: else
92: pipe_inst2 = MULF_OP_CODE;
93: addr_code_p1 = 0x66; /* addr mode 1 = (R6) */
94: addr_code_p2 = 0x62; /* addr mode 2 = (R2) */
95: if( op_code == PUSHD_OP_CODE ) /* Push Double instr? */
96: exp_page_faults = 6; /* expect 3 page fault */
97: else
98: exp_page_faults = 4; /* expect 1 page fault */
99: pack_inst(); /* pack the instr's code */
100: fill_reg_buf( load_regs ); /* set register load data */
101: fill_reg_buf( exp_regs ); /* set expected reg. data */
102: load_regs[2] = (int) adr_op5; /* the MULx op. is in op#5 */
103: exp_regs[2] = load_regs[2];
104: load_regs[6] = (int) adr_op4; /* the LDx op. is in op#4 */
105: exp_regs[6] = load_regs[6];
106: adr_op5->m = 0x40800000; /* set the MULx instrs' */
107: adr_op5->l = 0; /* operands = '1.0' */
108: min_shift = 17;
109: shift_count = 18;
110: for( index = 0; index <= max_index; index++ ) {
111: dbl_ld_acc = data_ptr[ index ].op_1;
112: dbl_expected = data_ptr[ index ].exp;
113: adr_op4->m = dbl_ld_acc.m; /* get the data for */
114: adr_op4->l = dbl_ld_acc.l; /* the load instruction */
115: run_code(); /* execute the instruction */
116: if( --shift_count < min_shift )
117: shift_count = 18;
118: }
119: pipe_test = FALSE; /* clear the pipe test flag */
120: }
121:
122:
123:
124:
125:
126:
127: /*
128: ****************************************************************************
129: *
130: * PIPELINE TEST #2 FOR INSTRUCTIONS WITH NO OPERANDS
131: *
132: * This test will put a MULTIPLY instruction immediately in front of the
133: * test instruction and a MULTIPLY instruction immediately behind it.
134: * Both multiplys will be times "1.0".
135: *
136: * The instruction buffer will look like:
137: * <mulf/muld> <instruction> <mulf/muld>
138: *
139: * The 1st multiply will be done indirect through register R6
140: * The 2nd multiply will be done indirect through register R2.
141: *
142: ****************************************************************************
143: */
144: tst_0_pipe2()
145: {
146: pipe_test = 2; /* set pipelined test flag to pipe test #1 */
147: if( acc_ld_size == DBL )
148: pipe_inst1 = MULD_OP_CODE;
149: else
150: pipe_inst1 = MULF_OP_CODE;
151: if( acc_st_size == DBL )
152: pipe_inst2 = MULD_OP_CODE;
153: else
154: pipe_inst2 = MULF_OP_CODE;
155: addr_code_p1 = 0x66; /* addr mode 1 = (R6) */
156: addr_code_p2 = 0x62; /* addr mode 2 = (R2) */
157: if( op_code == PUSHD_OP_CODE ) /* Push Double instr? */
158: exp_page_faults = 6; /* expect 3 page fault */
159: else
160: exp_page_faults = 4; /* expect 1 page fault */
161: pack_inst(); /* pack the instr's code */
162: fill_reg_buf( load_regs ); /* set register load data */
163: fill_reg_buf( exp_regs ); /* set expected reg. data */
164: load_regs[2] = (int) adr_op4; /* 2nd MULx op. is in op#4 */
165: exp_regs[2] = load_regs[2];
166: load_regs[6] = (int) adr_op5; /* 1st MULx op. is in op#5 */
167: exp_regs[6] = load_regs[6];
168: adr_op4->m = 0x40800000; /* set the MULx instrs' */
169: adr_op4->l = 0; /* operands = '1.0' */
170: adr_op5->m = 0x40800000;
171: adr_op5->l = 0;
172: min_shift = 17;
173: shift_count = 18;
174: for( index = 0; index <= max_index; index++ ) {
175: dbl_ld_acc = data_ptr[ index ].op_1;
176: dbl_expected = data_ptr[ index ].exp;
177: run_code(); /* execute the instruction */
178: if( --shift_count < min_shift )
179: shift_count = 18;
180: }
181: pipe_test = FALSE; /* clear the pipe test flag */
182: }
183:
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