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Power 6/32 Unix version 1.21

#include "dmp_defs.h"


/*
 **************************************************************************
 *
 *		Test an instruction that has no operands
 *
 *  This code will test instrucions with no operands. PUSHD is the only
 *  one of these instructions that will store any data.
 *
 *  29-Apr-85  added pipeline test
 *   5-Jun-85  converted from assembler to C code
 *
 **************************************************************************
*/
test_0_ops()
{
	if( (precision == SGL) || (op_code == LDFD_OP_CODE) )
	     acc_ld_size = SGL;			/* load a single Acc     */
	else
	     acc_ld_size = DBL;			/* load a double Acc     */
	if( (precision == SGL) || (op_code == CVDF_OP_CODE) )
	     acc_st_size = SGL;			/* store a single Acc    */
	else
	     acc_st_size = DBL;			/* store a double Acc    */
	tst_0_no_pipe();			/* test with no pipelineing */
	if( !no_fpp_wcs ) {
	     tst_0_pipe1();			/* run pipeline test #1  */
	     tst_0_pipe2();			/* run pipeline test #2  */
	}
}



/*
 ****************************************************************************
 *
 *	NON PIPELINED TEST FOR INSTRUCTIONS WITH NO OPERANDS
 *
 ****************************************************************************
*/
tst_0_no_pipe()
{
	pipe_test = FALSE;			/* clear the PIPE TEST flg */
	pack_inst();				/* pack the instr's code   */
	if( op_code == PUSHD_OP_CODE )		/* Push Double instr?      */
	     exp_page_faults = 3;		/* expect 3 page fault     */
	else
	     exp_page_faults = 1;		/* expect 1 page fault     */
	shift_count = 20;			/* shift the code 16 bytes */
	fill_reg_buf( load_regs );		/* set register load data  */
	fill_reg_buf( exp_regs );		/* set expected reg. data  */
	for( index = 0; index <= max_index; index++ ) {
	     dbl_ld_acc   = data_ptr[ index ].op_1;
	     dbl_expected = data_ptr[ index ].exp;
	     run_code();		/* execute the instruction */
	}
}






/*
 *************************************************************************
 *
 *	PIPELINE TEST #1 FOR INSTRUCTIONS WITH NO OPERANDS
 *
 *  This test will put a LOAD instruction immediately in front of the
 *  test instruction and a MULTIPLY instruction immediately behind it.
 *  The instruction buffer will look like:
 *
 *  <ldf/ldd> <instruction> <mulf/muld> where:
 *
 *  The load will be done indirect through register R6
 *  The 2nd multiply addressing mode will be indirect through register R2.
 *************************************************************************
*/
tst_0_pipe1()
{
	pipe_test = 1;		/* set pipelined test flag to pipe test #2 */
	if( acc_ld_size == DBL )
	     pipe_inst1 = LDD_OP_CODE;
	else
	     pipe_inst1 = LDF_OP_CODE;
	if( acc_st_size == DBL )
	     pipe_inst2 = MULD_OP_CODE;
	else
	     pipe_inst2 = MULF_OP_CODE;
	addr_code_p1 = 0x66;			/* addr mode 1 = (R6)      */
	addr_code_p2 = 0x62;			/* addr mode 2 = (R2)      */
	if( op_code == PUSHD_OP_CODE )		/* Push Double instr?      */
	     exp_page_faults = 6;		/* expect 3 page fault     */
	else
	     exp_page_faults = 4;		/* expect 1 page fault     */
	pack_inst();				/* pack the instr's code   */
	fill_reg_buf( load_regs );		/* set register load data  */
	fill_reg_buf( exp_regs );		/* set expected reg. data  */
	load_regs[2] = (int) adr_op5;		/* the MULx op. is in op#5 */
	exp_regs[2] = load_regs[2];
	load_regs[6] = (int) adr_op4;		/* the LDx op. is in op#4  */
	exp_regs[6] = load_regs[6];
	adr_op5->m = 0x40800000;		/* set the MULx instrs'    */
	adr_op5->l = 0;				/*    operands = '1.0'     */
	min_shift = 17;
	shift_count = 18; 
	for( index = 0; index <= max_index; index++ ) {
	     dbl_ld_acc   = data_ptr[ index ].op_1;
	     dbl_expected = data_ptr[ index ].exp;
	     adr_op4->m = dbl_ld_acc.m;		/* get the data for        */
	     adr_op4->l = dbl_ld_acc.l;		/*   the load instruction  */
	     run_code();			/* execute the instruction */
	     if( --shift_count < min_shift )
		  shift_count = 18;
	}
	pipe_test = FALSE;			/* clear the pipe test flag */
}






/*
 ****************************************************************************
 *
 *	PIPELINE TEST #2 FOR INSTRUCTIONS WITH NO OPERANDS
 *
 *  This test will put a MULTIPLY instruction immediately in front of the
 *  test instruction and a MULTIPLY instruction immediately behind it.
 *  Both multiplys will be times "1.0".
 *
 *  The instruction buffer will look like:
 *  	<mulf/muld> <instruction> <mulf/muld> 
 *
 *  The 1st multiply will be done indirect through register R6
 *  The 2nd multiply will be done indirect through register R2.
 *
 ****************************************************************************
*/
tst_0_pipe2()
{
	pipe_test = 2;		/* set pipelined test flag to pipe test #1 */
	if( acc_ld_size == DBL )
	     pipe_inst1 = MULD_OP_CODE;
	else
	     pipe_inst1 = MULF_OP_CODE;
	if( acc_st_size == DBL )
	     pipe_inst2 = MULD_OP_CODE;
	else
	     pipe_inst2 = MULF_OP_CODE;
	addr_code_p1 = 0x66;			/* addr mode 1 = (R6)      */
	addr_code_p2 = 0x62;			/* addr mode 2 = (R2)      */
	if( op_code == PUSHD_OP_CODE )		/* Push Double instr?      */
	     exp_page_faults = 6;		/* expect 3 page fault     */
	else
	     exp_page_faults = 4;		/* expect 1 page fault     */
	pack_inst();				/* pack the instr's code   */
	fill_reg_buf( load_regs );		/* set register load data  */
	fill_reg_buf( exp_regs );		/* set expected reg. data  */
	load_regs[2] = (int) adr_op4;		/* 2nd MULx op. is in op#4 */
	exp_regs[2] = load_regs[2];
	load_regs[6] = (int) adr_op5;		/* 1st MULx op. is in op#5 */
	exp_regs[6] = load_regs[6];
	adr_op4->m = 0x40800000;		/* set the MULx instrs'    */
	adr_op4->l = 0;				/*    operands = '1.0'     */
	adr_op5->m = 0x40800000;
	adr_op5->l = 0;	
	min_shift = 17;
	shift_count = 18; 
	for( index = 0; index <= max_index; index++ ) {
	     dbl_ld_acc   = data_ptr[ index ].op_1;
	     dbl_expected = data_ptr[ index ].exp;
	     run_code();			/* execute the instruction */
	     if( --shift_count < min_shift )
		  shift_count = 18;
	}
	pipe_test = FALSE;			/* clear the pipe test flag */
}

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