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1.1 root 1:
2: /*******************************************************************
3: * ABSOLUTE ADDRESSING:
4: * instruction = <op-code> <9f> <&dmp_op_1> {<9f> <&dmp_op_2>}
5: *******************************************************************/
6: tst_abs()
7: {
8: pipe_test = FALSE; /* clear the pipe test flag */
9: fill_reg_buf( load_regs ); /* set data for registers */
10: fill_reg_buf( exp_regs ); /* set data for registers */
11: addr_mode = ADR_ABSOLUTE;
12: addr_code = addr_code2 = 0x9f;
13: addr_size = 4; /* longword (4 byte) ops. */
14: addr_1 = DMP_OP_1; /* abs. address of data */
15: addr_2 = DMP_OP_2;
16: if( no_ops == 2 )
17: min_shift = 6;
18: else
19: min_shift = 11;
20: shift_count = 15;
21: for( index = 0; index <= max_index; index++ ) {
22: get_current_data( adr_op1, adr_op2 );
23: get_exp_faults( 3, 4, 4, 6 ); /* set exp fault cnt */
24: pack_inst(); /* pack the instr. code */
25: run_code(); /* execute the instruction */
26: if( --shift_count < min_shift )
27: shift_count = 15;
28: }
29: }
30:
31:
32:
33:
34:
35: /*******************************************************************
36: * LONGWORD DISPLACEMENT RELATIVE DEFERRED ADDRESSING:
37: * instruction = <op-code> <ff> <offset to dmp_op_1>
38: * { <ff> <offset to dmp_op_1> }
39: *******************************************************************/
40: tst_l_d()
41: {
42: pipe_test = FALSE; /* clear the pipe test flag */
43: fill_reg_buf( load_regs ); /* set data for registers */
44: fill_reg_buf( exp_regs ); /* set data for registers */
45: addr_mode = ADR_L_DSP_DEF;
46: addr_code = addr_code2 = 0xff;
47: addr_size = 4; /* longword (4 byte) op. */
48: if( no_ops == 2 )
49: min_shift = 6;
50: else
51: min_shift = 11;
52: shift_count = 15;
53: for( index = 0; index <= max_index; index++ )
54: {
55: get_current_data( adr_op1, adr_op2 );
56: get_exp_faults( 4, 5, 6, 8 ); /* set exp fault cnt */
57: addr_1 = os_ad_op1 + 10 - shift_count; /* operand offset */
58: addr_2 = os_ad_op2 + 5 - shift_count;
59: pack_inst(); /* pack the instr. code */
60: run_code(); /* execute the instruction */
61: if( --shift_count < min_shift )
62: shift_count = 15;
63: }
64: }
65:
66:
67:
68:
69:
70: /*******************************************************************
71: * AUTO-INCREMENTED STACK POINTER ADDRESSING ( POP ): ( sgl ops only )
72: * instruction = <op-code> <8e>
73: *
74: * The data will be pushed by "run_code"
75: * Pop will be run with SGL instructions only.
76: *******************************************************************/
77: tst_pop()
78: {
79: pipe_test = FALSE; /* clear the pipe test flag */
80: fill_reg_buf( load_regs ); /* set data for registers */
81: fill_reg_buf( exp_regs ); /* set data for registers */
82: addr_mode = ADR_POP;
83: addr_code = addr_code2 = 0x8e;
84: addr_size = 0; /* no addressing bytes */
85: pack_inst(); /* pack the instr. code */
86: if( no_ops == 2 ) {
87: min_shift = 14;
88: exp_page_faults = 4; /* 4 pages are used */
89: } else {
90: min_shift = 15;
91: exp_page_faults = 3; /* 3 pages are used */
92: }
93: shift_count = 15;
94: for( index = 0; index <= max_index; index++ )
95: {
96: get_current_data( adr_op1, adr_op2 );
97: sgl_value_9 = dbl_value_1.m; /* data to be pushed */
98: sgl_value_10 = dbl_value_2.m;
99: run_code(); /* execute the instruction */
100: (*test_ptr)(); /* verify the results */
101: if( force_loop )
102: run_code(); /* start the error loop */
103: if( --shift_count < min_shift )
104: shift_count = 15;
105: }
106: }
107:
108:
109:
110:
111:
112:
113: /*******************************************************************
114: * REGISTER + BYTE DISPLACEMENT ADDRESSING:
115: * instruction = <op-code> <a4> <(&op_1 -r4)>
116: * { <a5> <(&op_2- r5)> }
117: *******************************************************************/
118: tst_r_b()
119: {
120: pipe_test = FALSE; /* clear the pipe test flag */
121: fill_reg_buf( load_regs ); /* set data for registers */
122: fill_reg_buf( exp_regs ); /* set data for registers */
123: addr_mode = ADR_REG_B;
124: addr_code = 0xa4; /* addr 1 is offset by r4 */
125: addr_code2 = 0xa5; /* addr 2 is offset by r5 */
126: addr_size = 1; /* 1 byte operand */
127: addr_1 = 20; /* set the 1st byte offset */
128: addr_2 = 4; /* set the 2nd byte offset */
129: pack_inst(); /* pack the instr. code */
130: load_regs[4] = (int) adr_op1 - 20; /* get the reg value */
131: load_regs[5] = (int) adr_op2 - 4;
132: exp_regs[4] = load_regs[4];
133: exp_regs[5] = load_regs[5];
134: if( no_ops == 2 )
135: min_shift = 12;
136: else
137: min_shift = 14;
138: shift_count = 15;
139: for( index = 0; index <= max_index; index++ )
140: {
141: get_current_data( adr_op1, adr_op2 );
142: get_exp_faults( 3, 4, 4, 6 ); /* set exp fault cnt */
143: run_code(); /* execute the instruction */
144: if( --shift_count < min_shift )
145: shift_count = 15;
146: }
147: }
148:
149:
150:
151:
152: /*******************************************************************
153: * INDEXED LONGWORD DISPLACEMENT ADDRESSING:
154: * instruction = <op-code> <44> <ef> <longword offset>
155: * { <45> <ef> <longword offset> }
156: *******************************************************************/
157: tst_x_l()
158: {
159: pipe_test = FALSE; /* clear the pipe test flag */
160: fill_reg_buf( load_regs ); /* set data for registers */
161: fill_reg_buf( exp_regs ); /* set data for registers */
162: addr_mode = ADR_I_L;
163: addr_code = 0x44; /* code for reg. 4 index */
164: addr_code2 = 0x45; /* code for reg. 5 index */
165: addr_codeB = 0xef; /* code for longword disp */
166: addr_size = 4; /* longword (4 byte) op. */
167: if( sgl_op )
168: {
169: load_regs[4] = 4; /* reg 4 = 4 (longwords) */
170: load_regs[5] = 6; /* reg 5 = 6 (longwords) */
171: } else {
172: load_regs[4] = 2; /* reg 4 = 2 (quadwords) */
173: load_regs[5] = 3; /* reg 5 = 3 (quadwords) */
174: }
175: exp_regs[4] = load_regs[4];
176: exp_regs[5] = load_regs[5];
177: if( no_ops == 2 )
178: min_shift = 4;
179: else
180: min_shift = 10;
181: shift_count = 15;
182: for( index = 0; index <= max_index; index++ )
183: {
184: get_current_data( adr_op1, adr_op2 );
185: get_exp_faults( 3, 4, 4, 6 ); /* set exp fault cnt */
186: addr_1 = os_op1 + 9 - shift_count; /* data's offset */
187: addr_1 -=16; /* -16 bytes (2 Q-words) */
188: addr_2 = os_op2 + 3 - shift_count; /* data's offset */
189: addr_2 -=24; /* -24 bytes (3 Q-words) */
190: pack_inst(); /* pack the instr. code */
191: run_code(); /* execute the instruction */
192: if( --shift_count < min_shift )
193: shift_count = 15;
194: }
195: }
196:
197:
198:
199:
200:
201:
202:
203: /*******************************************************************
204: * PIPELINED TEST #2 -LONGWORD DISPLACEMENT RELATIVE ADDR. WITH A PRE MULTIPLY
205: *
206: * This test will put MULTIPLY instructions immediately in front of and
207: * behind the test instruction.
208: * The instruction buffer will look like:
209: *
210: * <mulf/muld> <instruction> <mulf/muld> where:
211: * instruction = <op-code> <ef> <offset to dmp_op_1>
212: * { <ef> <offset to dmp_op_2> }
213: *
214: * The 1st multiply's addressing will be indirect through register R6.
215: * The 2nd multiply's addressing will be indirect through register R2.
216: *******************************************************************/
217: tst_p2()
218: {
219: pipe_test = 2; /* set the piplined flag to test # 2 */
220: if( acc_ld_size == DBL )
221: pipe_inst1 = MULD_OP_CODE;
222: else
223: pipe_inst1 = MULF_OP_CODE;
224: if( acc_st_size == DBL )
225: pipe_inst2 = MULD_OP_CODE;
226: else
227: pipe_inst2 = MULF_OP_CODE;
228: fill_reg_buf( load_regs ); /* set data for registers */
229: fill_reg_buf( exp_regs ); /* set data for registers */
230: load_regs[2] = (int) adr_op3; /* 2nd MULx is w/ op. #3 */
231: exp_regs[2] = load_regs[2];
232: load_regs[6] = (int) adr_op4; /* 1st MULx is w/ op. #4 */
233: exp_regs[6] = load_regs[6];
234: adr_op3->m = 0x40800000; /* set the piped mult's */
235: adr_op3->l = 0; /* operand = '1.0' */
236: adr_op4->m = 0x40800000;
237: adr_op4->l = 0;
238: addr_mode = ADR_L_DSP;
239: addr_code = addr_code2 = 0xef;
240: addr_size = 4; /* longword (4 byte) ops. */
241: if( no_ops == 2 )
242: min_shift = 2;
243: else
244: min_shift = 7;
245: shift_count = 15;
246: for( index = 0; index <= max_index; index++ )
247: {
248: get_current_data( adr_op1, adr_op2 );
249: get_exp_faults( 5, 6, 6, 8 ); /* set exp fault cnt */
250: addr_1 = os_op1 + 8 - shift_count; /* data's offset */
251: addr_2 = os_op2 + 3 - shift_count;
252: pack_inst(); /* pack the instr. code */
253: run_code(); /* execute the instruction */
254: if( --shift_count < min_shift )
255: shift_count = 15;
256: }
257: pipe_test = FALSE; /* clear the pipe test flag */
258: }
259:
260:
261:
262:
263:
264: /*
265: ***************************************************************************
266: *
267: * GET DATA FOR DOUBLE PRECISION INSTRUCTIONS
268: *
269: ***************************************************************************
270: */
271: get_current_data( dptr_1, dptr_2 )
272: struct u64 *dptr_1; /* pointer to 1st operand */
273: struct u64 *dptr_2; /* pointer to 2nd operand */
274: {
275: if( no_ops == 2 )
276: {
277: dbl_ld_acc = ldd_data[ index +1 ].op_1;
278: dbl_value_1 = data_ptr[ index ].op_1;
279: dbl_value_2 = data_ptr[ index ].op_2;
280: dbl_expected = data_ptr[ index ].exp;
281: *dptr_1 = dbl_value_1; /* set 1st operand */
282: *dptr_2 = dbl_value_2; /* set 2nd operand */
283: } else { /* only 1 operand */
284: dbl_ld_acc = data_ptr[ index ].op_1;
285: dbl_value_1 = data_ptr[ index ].op_2;
286: dbl_expected = data_ptr[ index ].exp;
287: *dptr_1 = dbl_value_1; /* set the operand */
288: }
289: }
290:
291:
292:
293: /*
294: ***************************************************************************
295: * Set the number of translation faults expected
296: *
297: * The entry parameters are the number of faults expected with an instruction
298: * cache miss and with varying data types. The correct fault count is
299: * selected and put into "exp_page_faults".
300: * In double precision compare operations, the system won't fetch the
301: * least significant half of the operand(s) if the most significant halves
302: * are different. The # of faults expected will be adjusted for this.
303: *
304: ***************************************************************************
305: */
306: get_exp_faults( sgl_1, dbl_1, sgl_2, dbl_2 )
307: int sgl_1; /* exp # faults for 1 sgl operand */
308: int dbl_1; /* exp # faults for 1 dbl operand */
309: int sgl_2; /* exp # faults for 2 sgl operands */
310: int dbl_2; /* exp # faults for 2 dbl operands */
311: {
312: if( no_ops == 1 ) {
313: if( sgl_op )
314: exp_page_faults = sgl_1; /* 1 sgl operand */
315: else
316: exp_page_faults = dbl_1; /* 1 dbl operand */
317: } else {
318: if( sgl_op )
319: exp_page_faults = sgl_2; /* 2 sgl operands */
320: else
321: exp_page_faults = dbl_2; /* 2 dbl operands */
322: }
323: if( (op_code == CMPD_OP_CODE) && (dbl_value_1.m != dbl_ld_acc.m) ||
324: (op_code == CMPD2_OP_CODE) && (dbl_value_1.m != dbl_value_2.m) )
325: exp_page_faults--;
326: }
327:
328:
329:
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