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1.1 root 1:
2: #define ALINE 80 /* 80 char maximun in aline */
3: #define SPACE ' '
4: #define CR '\n'
5: #define MINUS '-'
6: #define COMMA ','
7: #define EQUAL '='
8: #define ATYPE 'h'
9: #define NTYPE 'h'
10: #define HEX 'h'
11: #define DEC 'd'
12: #define NOBYTES 13
13: #define NULL '\0'
14:
15:
16:
17: /* TAHOE PRIVILEGE REGISTERS */
18:
19: asm(" .set SBR,0");
20: asm(" .set SLR,1");
21: asm(" .set P0BR,2");
22: asm(" .set P0LR,3");
23: asm(" .set P1BR,4");
24: asm(" .set P1LR,5");
25: asm(" .set P2BR,6");
26: asm(" .set P2LR,7");
27: asm(" .set IPL,8");
28: asm(" .set MAPEN,9");
29: asm(" .set MME,9");
30: asm(" .set TBIA,10");
31: asm(" .set TBIS,11");
32: asm(" .set DCK,12");
33: asm(" .set CCK,13");
34: asm(" .set PCBB,14");
35: asm(" .set KSP,19");
36: asm(" .set USP,20");
37: asm(" .set CPMDCB,21");
38: asm(" .set PADC,25");
39: asm(" .set DCR,27"); /* Diagnostic control register */
40: asm(" .set DC_ON,1"); /* DCR opcode of Enable data cache */
41: asm(" .set DC_OFF,2"); /* DCR opcode of Disable data cache */
42:
43: #define SBR 0
44: #define SLR 1
45: #define P0BR 2
46: #define P0LR 3
47: #define P1BR 4
48: #define P1LR 5
49: #define P2BR 6
50: #define P2LR 7
51: #define IPL 8
52: #define MME 9
53: #define MAPEN 9
54: #define TBIA 10
55: #define TBIS 11
56: #define DCK 12
57: #define CCK 13
58: #define PCBB 14
59: #define KSP 19
60: #define USP 20
61: #define PADC 25
62: #define DCR 27 /* Diagnostic control register */
63: #define SCB 0x800 /* address of SCB is at page 2 */
64:
65:
66:
67:
68: /* offsets to elements in PCB */
69:
70: #define PCB_KSP 0
71: #define PCB_USP 1*4
72: #define PCB_R0 2*4
73: #define PCB_R1 3*4
74: #define PCB_R2 4*4
75: #define PCB_R3 5*4
76: #define PCB_R4 6*4
77:
78: #define PCB_PC 16*4 /* Offset to PC in Process Control Block */
79: #define PCB_PSL 17*4
80: #define PCB_P0BR 18*4
81: #define PCB_P0LR 19*4
82: #define PCB_P1BR 20*4
83: #define PCB_P1LR 21*4
84: #define PCB_P2BR 22*4
85: #define PCB_P2LR 23*4
86:
87:
88: /* Offsets to vectors in SCB */
89:
90: #define CHMK_VEC 0x2b /* Offset to System call vector in SCB */
91: #define PROT_VEC 0x2f /* Protection fault vector */
92: #define TRANS_VEC 0x30 /* Translation fault vector */
93: #define RESV_INST 0x2c /* Reserved opcode */
94: #define RESV_ADRM 0x2e /* Reserved addr. mode */
95: #define ALIGN_FLT 0x35 /* Data alignment fault */
96:
97: /* PSL */
98: #define PSL_TP 0x40000000
99: #define PSL_IS 0x4000000
100: #define PSL_USR 0x1000000
101:
102:
103:
104: #define NBPG 1024
105: #define PGSHIFT 10
106: #define ENDVMEM 0xc01fffff /* max system virtual mem : 2 meg */
107: #define WRITE 1
108: #define READ 0
109: #define TRUE 1
110: #define FALSE 0
111: #define USER 1
112: #define KERNEL 0
113: #define LENGTH 1
114: #define VALID 0
115:
116: #define PTE_V 0x80000000 /* Valid bit */
117: #define PTE_PROT 0x78000000 /* Access bits in PTE */
118: #define PTE_UC 0x1000000 /* Uncachable bit */
119: #define PTE_M 0x800000 /* position of Modify bit in PTE */
120: #define PTE_U 0x400000 /* Used bit */
121: #define PTE_PFN 0x3fffff /* Page frame number in PTE */
122:
123: #define PTE_NOACC 0 /* No access */
124: #define PTE_KR 0x40000000 /* Kernel read */
125: #define PTE_KW 0x60000000 /* Kernel read/write */
126: #define PTE_URKR 0x50000000 /* User/Kernel read */
127: #define PTE_URKW 0x70000000 /* User read, Kernel read/write */
128: #define PTE_UW 0x78000000 /* User/Kernel read/write */
129:
130: #define SADDR 0xc0000000 /* Bit 30-31 of System, P0, P1, P2 */
131: #define P0ADDR 0 /* virtual address */
132: #define P1ADDR 0x40000000
133: #define P2ADDR 0x80000000
134:
135:
136:
137:
138:
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