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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / entry|
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1.1 ! root 1: #/* PROCESSOR STORAGE ! 2: # * ! 3: # *This is the first two K bytes of physical main memory to ! 4: # *be used by hardware/firmware. Software should never use ! 5: # *this area. ! 6: # *physical locations = 0x00000000 to 0x000007ff ! 7: # *virtual locations = 0xc0000000 to 0xc00007ff ! 8: # *physical = virtual# kernel read/write access ! 9: # * ! 10: # *divided into three areas: ! 11: # *(1) WCS load area (0x00000000 - 0x000003fc) ! 12: # label = _pstore: ! 13: # *(2) Architecturally defined privileged registers (not ! 14: # label = _pstore1: ! 15: # * provided in CPU hardware (0x00000400 - 0x000005fc) ! 16: # *(3) Temporary area for firmware (0x00000600 - 0x00007fc) ! 17: # label = _pstemp: = _tr0: ! 18: # * ! 19: #*/ ! 20: _pstore: ! 21: .globl _pstore ! 22: .space NBPG /*Reserved for WCS loading */ ! 23: ! 24: _pstore1: /*architecturally defined */ ! 25: .globl _pstore1 /*privileged registers area */ ! 26: ! 27: _pcbb: .space 4 /*process control block base reg*/ ! 28: .globl _isp ! 29: _isp: .space 4 /*interrupt stack pointer */ ! 30: _sirr: .space 4 /*software interrupt request reg*/ ! 31: .globl _sisr ! 32: _sisr: .space 4 /*software interrupt summary reg*/ ! 33: ! 34: .space 4 /*RESERVED*/ ! 35: .space 4 ! 36: .space 4 ! 37: ! 38: _cpmdcb: .space 4 /*console processor registers */ ! 39: _cpfdcb: .space 4 ! 40: _cpcdcb: .space 4 ! 41: _cpidcb: .space 4 ! 42: _cpstat: .space 4 ! 43: _cpctl: .space 4 ! 44: ! 45: .globl _hisr ! 46: _hisr: .space 4 /*hardware interrupt summary reg*/ ! 47: _dcr: .space 4 /*diagnostic control register */ ! 48: ! 49: .space 4*48 /*RESERVED - 48 unused longwords*/ ! 50: ! 51: _pstemp: ! 52: .globl _pstemp /*temporary storage area for */ ! 53: /*firmware */ ! 54: _tr0: .space 16 /*temporary storage for general */ ! 55: /*registers 0 thru 15 */ ! 56: _tpc: .space 4 /*program counter */ ! 57: _tpsl: .space 4 /*program status long word */ ! 58: _tsp: .space 4 /*stack pointer */ ! 59: _tksp: .space 4 /*kernel stack pointer */ ! 60: _tusp: .space 4 /*user stack pointer */ ! 61: _tcck: .space 4 /*code cache key */ ! 62: _tdck: .space 4 /*data cache key */ ! 63: _ttbk: .space 4 /*translation buffer key */ ! 64: _tsbr: .space 4 /*system base register */ ! 65: _tslr: .space 4 /*system length register */ ! 66: _tp0br: .space 4 /*p0 base register */ ! 67: _tp0lr: .space 4 /*p0 length register */ ! 68: _tp1br: .space 4 /*p1 base register */ ! 69: _tp1lr: .space 4 /*p1 length register */ ! 70: _tp2br: .space 4 /*p2 base register */ ! 71: _tp2lr: .space 4 /*p2 length register */ ! 72: _tipl: .space 4 /*interrupt priority level */ ! 73: _tmme: .space 4 /*memory mgmt enable */ ! 74: _ttbia: .space 4 /*trans buffer invalidate all */ ! 75: _ttbis: .space 4 /*trans buffer invalidate single*/ ! 76: /*the last two probably will */ ! 77: /*never be used */ ! 78: _tpcbb: .space 4 /*process control block base */ ! 79: _tisp: .space 4 /*interrupt stack pointer */ ! 80: _tsirr: .space 4 /*software int request reg */ ! 81: _tsisr: .space 4 /*software int summary reg */ ! 82: _tscbb: .space 4 /*system control block base */ ! 83: _tp1cc: .space 4 /*invalidate 1 page of process */ ! 84: /*code cache */ ! 85: _tpacc: .space 4 /*invalidate all process pages */ ! 86: /*in code cache */ ! 87: _tp1dc: .space 4 /*inval. 1 pg of proc data cache*/ ! 88: _tpadc: .space 4 /*inval. all pgs of proc data ch*/ ! 89: _tcpmdcb: ! 90: .space 4 /*temporary area for cp regs */ ! 91: _tcpfdcb: ! 92: .space 4 ! 93: _tcpcdcb: ! 94: .space 4 ! 95: _tcpidcb: ! 96: .space 4 ! 97: _tcpstat: ! 98: .space 4 ! 99: _tcpctl: ! 100: .space 4 ! 101: ! 102: _probflag: ! 103: .space 4 /*flag for probe instr */ ! 104: _inexcflg: ! 105: .space 4 /*in exception flag */ ! 106: ! 107: .space 4*10 /*RESERVED - unused */ ! 108: _psend: .globl _psend /* End of processor storage area*/ ! 109: .set MM,(_psend - _pstore1) ! 110: .space 1024 - MM ! 111: ! 112: ! 113: #/* Processor storage physical memory ! 114: # This section defines those names to be used when refering to ! 115: # processor storage. The use of many of these locations are defined ! 116: # in the architecture manual. ! 117: # These values always appear in the literal field. ! 118: #*/ ! 119: .set PCBB,0x400 #process control block base ! 120: ! 121: .globl INTSP ! 122: .set INTSP,0x404 #Interrupt stack pointer ! 123: .set SIRR,0x408 #Software interrupt request ! 124: ! 125: .globl SSR ! 126: .set SSR,0x40C #Software interrupt summary ! 127: ! 128: .globl HSR ! 129: .set HSR,0x410 #Hardware interrupt summary ! 130: ! 131: .set SBB,0x414 #Pointer to system control block base ! 132: .set TBCR,0x418 #Current value of hardware TBCR ! 133: .set CPMDCB,0x420 #pointer to CP master DCB ! 134: .set CPCTL,0x424 #CPU control word ! 135: .set CPREQ,0x428 #CPU request ! 136: .set CPRUN,0x42C #CPU run status (8 = step mode) ! 137: .set CPRSW,0x430 #CP interrupt request word ! 138: .set PSL,0x434 #Software Process Status Longword ! 139: .set TVAPR,0x5E8 #saved vapr register ! 140: .set TRA,0x5EC # ! 141: .set TLSP,0x5F0 # ! 142: .set TIAR,0x5F4 # ! 143: .set TLIA,0x5F8 # ! 144: .set TQ,0x5FC # ! 145: .set TR0,0x600 #decellerated processor registers ! 146: .set TR1,0x604 #decellerated processor registers ! 147: .set TR2,0x608 #decellerated processor registers ! 148: .set TR3,0x60C #decellerated processor registers ! 149: .set TR4,0x610 #decellerated processor registers ! 150: .set TR5,0x614 #decellerated processor registers ! 151: .set TR6,0x618 #decellerated processor registers ! 152: .set TR7,0x61C #decellerated processor registers ! 153: .set TR8,0x620 #decellerated processor registers ! 154: .set TR9,0x624 #decellerated processor registers ! 155: .set TR10,0x628 #decellerated processor registers ! 156: .set TR11,0x62C #decellerated processor registers ! 157: .set TR12,0x630 #decellerated processor registers ! 158: .set TR13,0x634 #decellerated processor registers ! 159: .set TR14,0x638 #decellerated processor registers ! 160: .set TR15,0x63C #decellerated processor registers ! 161: .set TPC,0x640 #decellerated program counter ! 162: .set TPSL,0x644 #decellerated process status longword ! 163: .set TSP,0x648 #decellerated stack pointer ! 164: .set TKSP,0x64C #decellerated kernel stack pointer ! 165: .set TUSP,0x650 #decellerated user stack pointer ! 166: .globl TCCK ! 167: .set TCCK,0x654 #decellerated Code cache key ! 168: .globl TDCK ! 169: .set TDCK,0x658 #decellerated data cache key ! 170: .set TTBK,0x65C #decellerated translation buffer key ! 171: .set TSBR,0x660 #decellerated System Base Register ! 172: .set TSLR,0x664 #decellerated System length register ! 173: .set TP0BR,0x668 #decellerated P0 base register ! 174: .set TP0LR,0x66C #decellerated P0 length register ! 175: .set TP1BR,0x670 #decellerated P1 base register ! 176: .set TP1LR,0x674 #decellerated P1 length register ! 177: .set TP2BR,0x678 #decellerated P2 base register ! 178: .set TP2LR,0x67C #decellerated P1 length register ! 179: .set TIPL,0x680 #decellerated Interrupt priority level ! 180: .set TMME,0x684 #decellerated Memory management enable ! 181: .set TTBIA,0x68C #decellerated translation buffer invalid ! 182: .set TTBIS,0x68C #decellerated transl buffer invalid single ! 183: .set TPCBB,0x690 #decellerated Process control block base ! 184: .set TISP,0x694 #decellerated Interrupt stack pointer ! 185: .set TSIRR,0x698 #decellerated Software interrupt request ! 186: .set TSISR,0x69C #decellerated Software interrupt summary ! 187: .set TSCBB,0x6A0 #decellerated System control block base ! 188: .set TP1CC,0x6A4 #decellerated ! 189: .set TPACC,0x6A8 #decellerated ! 190: .set TP1DC,0x6AC #decellerated ! 191: .set TPADC,0x6B0 #decellerated ! 192: .set TCPMDCB,0x6B4 #decellerated address of master DCB ! 193: .set PROBFLG,0x6B8 #decellerated ! 194: .set INEXCFLG,0x6BC #decellerated ! 195: .set PCTYPFLG,0x6C0 # ! 196: .set NOOFPARS,0x6C4 # ! 197: .set STKPAR1,0x6C8 # ! 198: .set STKPAR2,0x6CC # ! 199: .set JMPVEC,0x6D0 # ! 200: .set PSEND,0x7FC #
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