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Power 6/32 Unix version 1.2b

 #/*		PROCESSOR STORAGE
 #	*
 #	*This is the first two K bytes of physical main memory to
 #	*be used by hardware/firmware. Software should never use
 #	*this area.
 #	*physical locations = 0x00000000 to 0x000007ff
 #	*virtual locations =  0xc0000000 to 0xc00007ff
 #	*physical = virtual# kernel read/write access
 #	*
 #	*divided into three areas:
 #	*(1) WCS load area (0x00000000 - 0x000003fc)
 #	     label = _pstore:
 #	*(2) Architecturally defined privileged registers (not
 #	     label = _pstore1:	
 #	*    provided in CPU hardware (0x00000400 - 0x000005fc)
 #	*(3) Temporary area for firmware (0x00000600 - 0x00007fc)
 #	     label = _pstemp: = _tr0:	
 #	*
 #*/
_pstore:
	.globl	_pstore
	.space	NBPG			/*Reserved for WCS loading	*/

_pstore1:				/*architecturally defined	*/
	.globl	_pstore1		/*privileged registers area	*/

_pcbb:	.space	4			/*process control block base reg*/
	.globl	_isp
_isp:	.space	4			/*interrupt stack pointer	*/
_sirr:	.space	4			/*software interrupt request reg*/
	.globl	_sisr
_sisr:	.space	4			/*software interrupt summary reg*/
	
	.space	4			/*RESERVED*/
	.space	4
	.space	4

_cpmdcb: .space	4			/*console processor registers	*/
_cpfdcb: .space	4
_cpcdcb: .space	4
_cpidcb: .space	4
_cpstat: .space	4
_cpctl:  .space	4

	.globl	_hisr
_hisr:	.space	4			/*hardware interrupt summary reg*/
_dcr:	.space	4			/*diagnostic control register	*/

	.space	4*48			/*RESERVED - 48 unused longwords*/

_pstemp:
	.globl	_pstemp			/*temporary storage area for	*/
					/*firmware			*/
_tr0:	.space	16			/*temporary storage for general	*/
					/*registers 0 thru 15		*/
_tpc:	.space	4			/*program counter		*/
_tpsl:	.space	4			/*program status long word	*/
_tsp:	.space	4			/*stack pointer			*/
_tksp:	.space	4			/*kernel stack pointer		*/
_tusp:	.space	4			/*user stack pointer		*/
_tcck:	.space	4			/*code cache key		*/
_tdck:	.space	4			/*data cache key		*/
_ttbk:	.space	4			/*translation buffer key	*/
_tsbr:	.space	4			/*system base register		*/
_tslr:	.space	4			/*system length register	*/
_tp0br:	.space	4			/*p0 base register		*/
_tp0lr:	.space	4			/*p0 length register		*/
_tp1br:	.space	4			/*p1 base register		*/
_tp1lr:	.space	4			/*p1 length register		*/
_tp2br:	.space	4			/*p2 base register		*/
_tp2lr:	.space	4			/*p2 length register		*/
_tipl:	.space	4			/*interrupt priority level	*/
_tmme:	.space	4			/*memory mgmt enable		*/
_ttbia:	.space	4			/*trans buffer invalidate all	*/
_ttbis:	.space	4			/*trans buffer invalidate single*/
					/*the last two probably will	*/
					/*never be used			*/
_tpcbb:	.space	4			/*process control block base	*/
_tisp:	.space	4			/*interrupt stack pointer	*/
_tsirr:	.space	4			/*software int request reg	*/
_tsisr:	.space	4			/*software int summary reg	*/
_tscbb:	.space	4			/*system control block base	*/
_tp1cc:	.space	4			/*invalidate 1 page of process	*/
					/*code cache			*/
_tpacc:	.space	4			/*invalidate all process pages	*/
					/*in code cache			*/
_tp1dc:	.space	4			/*inval. 1 pg of proc data cache*/
_tpadc:	.space	4			/*inval. all pgs of proc data ch*/
_tcpmdcb:
	.space	4			/*temporary area for cp regs	*/
_tcpfdcb:
	.space	4
_tcpcdcb:
	.space	4
_tcpidcb:
	.space	4
_tcpstat:
	.space	4
_tcpctl:
	.space	4

_probflag:
	.space	4			/*flag for probe instr		*/
_inexcflg:
	.space	4			/*in exception flag		*/

	.space	4*10			/*RESERVED - unused		*/
_psend:	.globl	_psend			/* End of processor storage area*/
	.set    MM,(_psend - _pstore1)
	.space  1024 - MM


 #/*	Processor storage physical memory
 #	This section defines those names to be used when refering to
 #	processor storage.  The use of many of these locations are defined
 #	in the architecture manual.
 #	These values always appear in the literal field.
 #*/
	.set	PCBB,0x400		#process control block base

	.globl	INTSP
	.set	INTSP,0x404		#Interrupt stack pointer
	.set	SIRR,0x408		#Software interrupt request

	.globl	SSR
	.set	SSR,0x40C		#Software interrupt summary

	.globl	HSR
	.set	HSR,0x410		#Hardware interrupt summary

	.set	SBB,0x414		#Pointer to system control block base
	.set	TBCR,0x418		#Current value of hardware TBCR
	.set	CPMDCB,0x420		#pointer to CP master DCB
	.set	CPCTL,0x424		#CPU control word
	.set	CPREQ,0x428		#CPU request
	.set	CPRUN,0x42C		#CPU run status (8 = step mode)
	.set	CPRSW,0x430		#CP interrupt request word
	.set	PSL,0x434		#Software Process Status Longword
	.set	TVAPR,0x5E8		#saved vapr register
	.set	TRA,0x5EC		#
	.set	TLSP,0x5F0		#
	.set	TIAR,0x5F4		#
	.set	TLIA,0x5F8		#
	.set	TQ,0x5FC		#
	.set	TR0,0x600		#decellerated processor registers
	.set	TR1,0x604		#decellerated processor registers
	.set	TR2,0x608		#decellerated processor registers
	.set	TR3,0x60C		#decellerated processor registers
	.set	TR4,0x610		#decellerated processor registers
	.set	TR5,0x614		#decellerated processor registers
	.set	TR6,0x618		#decellerated processor registers
	.set	TR7,0x61C		#decellerated processor registers
	.set	TR8,0x620		#decellerated processor registers
	.set	TR9,0x624		#decellerated processor registers
	.set	TR10,0x628		#decellerated processor registers
	.set	TR11,0x62C		#decellerated processor registers
	.set	TR12,0x630		#decellerated processor registers
	.set	TR13,0x634		#decellerated processor registers
	.set	TR14,0x638		#decellerated processor registers
	.set	TR15,0x63C		#decellerated processor registers
	.set	TPC,0x640		#decellerated program counter
	.set	TPSL,0x644		#decellerated process status longword
	.set	TSP,0x648		#decellerated stack pointer
	.set	TKSP,0x64C		#decellerated kernel stack pointer
	.set	TUSP,0x650		#decellerated user stack pointer
	.globl	TCCK
	.set	TCCK,0x654		#decellerated Code cache key
	.globl	TDCK
	.set	TDCK,0x658		#decellerated data cache key
	.set	TTBK,0x65C		#decellerated translation buffer key
	.set	TSBR,0x660		#decellerated System Base Register
	.set	TSLR,0x664		#decellerated System length register
	.set	TP0BR,0x668		#decellerated P0 base register
	.set	TP0LR,0x66C		#decellerated P0 length register
	.set	TP1BR,0x670		#decellerated P1 base register
	.set	TP1LR,0x674		#decellerated P1 length register
	.set	TP2BR,0x678		#decellerated P2 base register
	.set	TP2LR,0x67C		#decellerated P1 length register
	.set	TIPL,0x680		#decellerated Interrupt priority level
	.set	TMME,0x684		#decellerated Memory management enable
	.set	TTBIA,0x68C		#decellerated translation buffer invalid
	.set	TTBIS,0x68C		#decellerated transl buffer invalid single
	.set	TPCBB,0x690		#decellerated Process control block base
	.set	TISP,0x694		#decellerated Interrupt stack pointer
	.set	TSIRR,0x698		#decellerated Software interrupt request
	.set	TSISR,0x69C		#decellerated Software interrupt summary
	.set	TSCBB,0x6A0		#decellerated System control block base
	.set	TP1CC,0x6A4		#decellerated 
	.set	TPACC,0x6A8		#decellerated
	.set	TP1DC,0x6AC		#decellerated
	.set	TPADC,0x6B0		#decellerated
	.set	TCPMDCB,0x6B4		#decellerated address of master DCB
	.set	PROBFLG,0x6B8		#decellerated
	.set	INEXCFLG,0x6BC		#decellerated
	.set	PCTYPFLG,0x6C0		#
	.set	NOOFPARS,0x6C4		#
	.set	STKPAR1,0x6C8		#
	.set	STKPAR2,0x6CC		#
	.set	JMPVEC,0x6D0		#
	.set	PSEND,0x7FC		#

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