File:  [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / entry / sbwc.c
Revision 1.1.1.1 (vendor branch): download - view: text, annotated - select for diffs
Sun Jul 28 12:24:19 2019 UTC (7 years ago) by root
Branches: bsd, MAIN
CVS tags: v12b, v121, HEAD
Power 6/32 Unix version 1.2b

#define disp_error error

/*		constants definition for SBWC instruction		*/
/*									*/
/*									*/

#define		SBWC		0x9d		/*opcode		*/

asm(".set PSWMASK,0xf");

#define		MAX_PATTERNS	10

extern long scoplp;
extern long force_lp;

#define		DIF1		0x7fffffff	/*initial value of dif	*/
#define		DIF2		0x7fffffff
#define		DIF3		0x80000000
#define		DIF4		0x80000000
#define		DIF5		0
#define		DIF6		0
#define		DIF7		-1
#define		DIF8		0x80000000
#define		DIF9		0
#define		DIF10		0x7fffffff

#define		SUB1		0x80000002	/*initial values for sub*/
#define		SUB2		0x80000001
#define		SUB3		-1
#define		SUB4		-1
#define		SUB5		1
#define		SUB6		-1
#define		SUB7		1
#define		SUB8		1
#define		SUB9		0x80000000
#define		SUB10		-1


#define		EXP1		0xfffffffd	/*expected result	*/
#define		EXP2		0xfffffffd
#define		EXP3		0x80000000
#define		EXP4		0x80000001
#define		EXP5		0xfffffffe 
#define		EXP6		1
#define		EXP7		0xfffffffe 
#define		EXP8		0x7ffffffe
#define		EXP9		0x80000000
#define		EXP10		0x7fffffff

#define		IPSW1		5		/*initial psw		*/
#define		IPSW2		4
#define		IPSW3		6
#define		IPSW4		7
#define		IPSW5		6
#define		IPSW6		11
#define		IPSW7		11
#define		IPSW8		12
#define		IPSW9		13
#define		IPSW10		4

/*	EXPECTED PSW 	*/

#define		EPSW1		2   
#define		EPSW2		2
#define		EPSW3		8
#define		EPSW4		8
#define		EPSW5		8
#define		EPSW6		0
#define		EPSW7		9
#define		EPSW8		11
#define		EPSW9		2
#define		EPSW10		0

#define		ERROR1		1		/*error definitions	*/
#define		ERROR2		2
#define		ERROR3		3


#define		EM1		"difference not equal to expected \n"
#define		EM2		"subtrahend operand altered \n"
#define		EM3		"psw not equal to expected \n"


/*		standard definition file				*/
/*		for 'C' diagnostic porgrams.				*/
/*									*/
/*									*/
#define		HIGH		31
#define		IPL		8
#define		PSWMASK		0xf
#define		T		16
#define		IV		32
#define		FU		64
#define		DV		128
#define		FLAGS		0x0000000f







/*	Global variables for subtract with carry test			*/
/*									*/
/*									*/

static short	index = 0;
static long	dif = 0;	/* destination location			*/
static long	sub = 0;	/*subtrahend location			*/
static long	psw;		/*processor status word			*/
static long	error_count = 0;

				/*initial flag values			*/
static	long	i_psw[MAX_PATTERNS] = {IPSW1,IPSW2,IPSW3,IPSW4,IPSW5,IPSW6,
				       IPSW7,IPSW8,IPSW9,IPSW10};
				/*expected flag values			*/
static	long	exp_psw[MAX_PATTERNS] = {EPSW1,EPSW2,EPSW3,EPSW4,EPSW5,EPSW6,
					 EPSW7,EPSW8,EPSW9,EPSW10};
				/* expected destination			*/
static	long	exp[MAX_PATTERNS] = {EXP1,EXP2,EXP3,EXP4,EXP5,EXP6,EXP7,
				     EXP8,EXP9,EXP10};
				/*dif values				*/
static long	d[MAX_PATTERNS] = {DIF1,DIF2,DIF3,DIF4,DIF5,DIF6,DIF7,
				   DIF8,DIF9,DIF10};
				/*sub values				*/
static long	s[MAX_PATTERNS] = {SUB1,SUB2,SUB3,SUB4,SUB5,SUB6,SUB7,
				   SUB8,SUB9,SUB10};
static long	savvec4;
static long	old_psw;

sbwc()
{
      asm("movl	$2,_no_opr");
      for (index = 0; index < MAX_PATTERNS; index++) t_sbwc();
      asm("jmp *return");
}	

static t_sbwc()
{

	long ix;
	for (ix=1;ix<5;ix++)

	  if (ix==1){ 
	   setjmp();
	   asm("s1:	movab	s1,_stpc");
	   asm("movl	$1,_subtst");
	   dif = d[index];	/*initialize dif, subtrahend, & psw	*/
	   sub = s[index]; 
	   asm("movw	_index,r11"); 
	   asm("shll	$16,_i_psw[r11],_savvec4"); 
	   asm("bicpsw	$PSWMASK");
	   asm("bispsw	_savvec4");
	   asm("movpsl	_old_psw");
				/*execute sbwc instruction		*/
	   asm("sbwc	_sub,_dif"); /* mem to mem */
	   asm("movpsl	_psw");	/*save psw				*/
	   psw &= FLAGS;	/*mask out all bits except flag bits	*/
		    }
	  if (ix==2){ 
	   setjmp();
	   asm("s2:	movab	s2,_stpc");
	   asm("movl	$2,_subtst");
	   dif = d[index];	/*initialize dif, subtrahend, & psw	*/
	   sub = s[index]; 
	   asm("movw	_index,r11"); 
	   asm("shll	$16,_i_psw[r11],_savvec4"); 
	   asm("movl	_sub,r6");	/* load source reg */
	   asm("movl	_dif,r7");	/* load dest reg */
	   asm("bicpsw	$PSWMASK");
	   asm("bispsw	_savvec4");
	   asm("movpsl	_old_psw");
				/*execute sbwc instruction		*/
	   asm("sbwc	r6,r7"); /* reg to reg */
	   asm("movpsl	_psw");	/*save psw				*/
	   asm("movl	r7,_dif");	/* load dest reg */
	   psw &= FLAGS;	/*mask out all bits except flag bits	*/
		    }
	  if (ix==3){ 
	   setjmp();
	   asm("s3:	movab	s3,_stpc");
	   asm("movl	$3,_subtst");
	   dif = d[index];	/*initialize dif, subtrahend, & psw	*/
	   sub = s[index]; 
	   asm("movw	_index,r11"); 
	   asm("movl	_sub,r6");	/* load source reg */
	   asm("shll	$16,_i_psw[r11],_savvec4"); 
	   asm("bicpsw	$PSWMASK");
	   asm("bispsw	_savvec4");
	   asm("movpsl	_old_psw");
				/*execute sbwc instruction		*/
	   asm("sbwc	r6,_dif"); /* reg to memory */
	   asm("movpsl	_psw");	/*save psw				*/
	   psw &= FLAGS;	/*mask out all bits except flag bits	*/
		    }
	  if (ix==4){ 
	   setjmp();
	   asm("s4:	movab	s4,_stpc");
	   asm("movl	$4,_subtst");
	   dif = d[index];	/*initialize dif, subtrahend, & psw	*/
	   sub = s[index]; 
	   asm("movw	_index,r11"); 
	   asm("movl	_dif,r7");	/* load dest reg */
	   asm("shll	$16,_i_psw[r11],_savvec4"); 
	   asm("bicpsw	$PSWMASK");
	   asm("bispsw	_savvec4");
	   asm("movpsl	_old_psw");
				/*execute sbwc instruction		*/
	   asm("sbwc	_sub,r7");/* mem to reg */
	   asm("movpsl	_psw");	/*save psw				*/
	   asm("movl	r7,_dif");	/* load dest reg */
	   psw &= FLAGS;	/*mask out all bits except flag bits	*/
		}
	   if (dif != exp[index])
		{
		asm("movl	$1,_ercode");
		if (scoplp) longjmp();
		disp_error(dif,exp[index],s[index],d[index]);
		}
	   if (sub != s[index])
		{
		asm("movl	$3,_ercode");
		if (scoplp) longjmp();
		disp_error(sub,s[index],s[index],d[index]);
		}
	   if (psw != exp_psw[index])
		{
		asm("movl	$2,_ercode");
		if (scoplp) longjmp();
	    	disp_error(psw,exp_psw[index],s[index],d[index]);
		}
    	   else
		if (force_lp) longjmp();
		return(0);	/*no error exit*/ 
          }


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