--- cci/d/event/align_evt.s	2019/07/28 12:24:19	1.1
+++ cci/d/event/align_evt.s	2019/07/28 12:30:54	1.1.1.2
@@ -12,7 +12,11 @@
  #	     3 : Error in PSL pushed on the stack
  #		 R1 = actual,  R2 = expected
  #	     4 : Too many parameters pushed on the stack
- #
+ #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ #	Modified 11/20/85 to include two subtests (9 and A) that     #
+ #	will generate an alignment fault when the error is in        #
+ #	the intermediate address of a deferred addressing mode.      #
+ #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 
 	.globl	_align_evt
@@ -26,8 +30,8 @@ _align_evt:
 	movl	$-1,-(sp)		/* Push marker on stack		*/
 	movab	_pcb0,r1		/* Partially set PCB0		*/
 	mtpr	r1,$PCBB		/* Set PCBB to PCB0		*/
-	movab	(sp),_pcb0		/* PCB_KSP = current SP		*/
-	movab	(sp),_pcb0+4		/* PCB_USP = current SP		*/
+	mfpr	$KSP,_savvec9		/* Save kernal stack pointer	*/
+	mfpr	$USP,_savveca		/* Save user stack pointer	*/
 
 	movpsl	r1			/* If not kernel mode, then force */
 	bitl	$0x01000000,r1		/* Kernel mode			*/
@@ -115,11 +119,39 @@ epc7:	shrq	$6,dtable+2,r0		/* Should cau
 #	Try to shift a quadword into an ODD address
 spc8:
 	movab	epc8,r5			/* R5 = expected PC on stack 	*/
-	movab	eee,r6			/* R6 = return from exception addr */
+	movab	spc9,r6			/* R6 = return from exception addr */
 	movpsl	r7			/* R7 = Expected PSL to to checked */
 epc8:	shrq	$6,dtable+3,r0		/* Should cause fault 	*/
 	movl	$1,r0		/* Error : NO fault happen		*/
 	jmp	*badrtn
+#	
+#	Now in KERNAL MODE; IPL = 0x1f
+#	try Register + longword Displacment deferred
+#	This should get a fault because the intermidiate address ( (r8) + 4 )
+#	is not longword aligned.
+
+spc9:	movab	epc9,r5			/* R5 = expected PC on stack	*/
+	movab	spca,r6			/* R6 = return from exception addr */
+	movpsl	r7			/* R7 = Expected PSL to be checked */
+	movab	dtable,tmp1
+	movab	tmp0+1,r8
+epc9:	movl	$0x6,*l^4(r8)		/* should cause an alignment fault */
+	movl	$1,r0			/* ERROR : Did not generate fault  */
+	jmp	*badrtn
+#	
+#	Now in KERNAL MODE; IPL = 0x1f
+#	try Register + longword Displacment deferred
+#	This should get a fault because the intermidiate address ( (r8) + 4 )
+#	is not longword aligned.
+#
+spca:	movab	epca,r5			/* R5 = expected PC on stack	*/
+	movab	eee,r6			/* R6 = return from exception addr */
+	movpsl	r7			/* R7 = Expected PSL to be checked */
+	movab	dtable,tmp1
+	movab	tmp0+2,r8
+epca:	movl	$0x6,*l^4(r8)		/* Should cause an alignment fault */
+	movl	$1,r0			/* ERROR : Did not generate fault  */
+	jmp 	*badrtn
 #
 #
 #	Event handler for Data alignment fault
@@ -155,12 +187,16 @@ vecvec:
 eee:
 	mtpr	$31,$IPL
 	movl	_savvec0,sp	/* Restore original vector		*/
+	mtpr	_savvec0,$ISP		/* restore interrupt stack pointer */
+	mtpr	_savvec9,$KSP		/* restore kernal stack pointer	*/
+	mtpr	_savveca,$USP		/* restore user stack pointer	*/
 	movl	_savvec2,_scb+ALIGNVEC
 	ret
 #
 #
 	.align	2
 tmp0:	.long   0
+tmp1:	.long	0
 dtable:	.byte	0x12
 	.byte	0x34
 	.byte	0x56