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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / event|
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1.1 root 1:
2: #
3: # *bus error event test
4: #
5: #
6: # *non_existent memory (done)
7: # *versabus timeout (done)
8: # *uncorrectable memory error (not done)
9: # *versabus error (not done)
10: # *versabus parity error (not done)
11: #
12: # R4 : PC that failed
13: # R5 : type of fault is testing
14: # 1 - Non existence memory
15: # 2 - Versabus time out
16: # R0 : error code
17: # 1 - expected fault didnot happen
18: # R1 : memory address
19: # 2 - error in SP after taking fault
20: # R1 : actual , R2 : expected
21: # 3 - error in PSL after taking fault
22: # R1 : actual , R2 : expected
23: # 4 - error in Versabus type pushed on stack
24: # R1 : actual , R2 : expected
25: # 5 - error in error code pushed on stack
26: # R1 : actual , R2 : expected
27: # 6 - error in PC pushed on stack
28: # R1 : actual , R2 : expected
29: # 7 - error in PSL pushed on stack
30: # R1 : actual , R2 : expected
31: #
32: # constants -- errorcodes from versabus (not final yet)
33:
34: .set NON_EXIST_MEM,6
35: .set VB_TOUT,4
36:
37: .globl _be_evt
38: _be_evt:
39: .word 0x1fff
40: mtpr $0x1c,$IPL
41: movl $0,*$HSR /* Clear HISR, SISR */
42: movl $0,*$SSR
43: movab (sp),_savvec0 /* Save current SP */
44: mtpr _savvec0,$ISP /* Init. ISP */
1.1.1.2 ! root 45: /*mfpr $KSP,_savvec9 /* Save cuurent KSP */
! 46: /*mfpr $USP,_savveca /* Save cuurent USP */
1.1 root 47: movpsl _savvec1 /* Save current PSL */
48: movl _scb+BEVEC,_savvec2 /* Save bus error vector */
49: movab 9f,_scb+BEVEC /* Set new vector for Bus error */
50: movl $1,bloop
51: _b2:
52: movl $2,r11 /* R11 = counter */
53:
54: # Non_existent memory error
55:
56: berr:
57: movl $1,r5 /* R5 = 1; Non_existence memory */
58: movl $0x03fffff0,r1 /* R1 = Non_existence memory address */
59: movpsl r6 /* R6 = saved expected PSL */
60: cmpl $1,r11
61: jeql exp_pc2
62: exp_pc1:
63: movab epc1,r4
64: epc1: tstl (r1) /* Should cause Non_existence memory fault */
65: movl $1,r0 /* R0 = 1; error code : Expected fault did */
66: jmp *badrtn /* not happen. R1 = memory address */
67: exp_pc2:
68: movab epc2,r4
69: epc2: clrl (r1) /* Should cause Non_existence memory fault */
70: movl $1,r0 /* R0 = 1; error code : Expected fault did */
71: jmp *badrtn /* not happen. R1 = memory address */
72: #
73: # Bus error event handler
74: #
75: .align 2
76: 9: movab (sp),r1
77: movl _savvec0,r2 /* Check current SP = ISP - 16 */
78: subl2 $16,r2 /* PC,PSL and 2 params should be on stack */
79: cmpl r1,r2
80: beql 1f
81: 2: movl $2,r0 /* R0 = 2; error in SP after taking fault */
82: jmp *badrtn /* SP not decremented by 16 after Bus error */
83: 1:
84: movpsl r1 /* Check current PSL_MODE */
85: andl3 $0x04000000,r1,r3 /* Expected PSL_MODE = Kernel */
86: bneq 1f
87: 2: movl $3,r0 /* R0 = 3; PSL not set correct */
88: movl $0x041d0000,r2 /* after taking Bus error exception */
89: jmp *badrtn
90: 1: andl3 $0x01000000,r1,r3 /* Check current PSL_IS */
91: bneq 2b /* Expected PSL_IS = 1 */
92: andl3 $0x001d0000,r1,r3 /* Check PSL_IPL = 0x1d */
93: cmpl $0x001d0000,r3
94: bneq 2b
95: #
96: # Check parameters pushed on SP
97: #
98: movl (sp)+,r3 /* R3 = Versabus type pushed on stack */
99: andl3 $0,r3,r1 /* For now , don't care */
100: movl $0,r2 /* R2 = expected type (don't care) */
101: cmpl r1,r2
102: beql 1f
103: movl $4,r0 /* R0 = 4; incorrect error code */
104: jmp *badrtn /* pushed on the stack */
105:
106: 1: movl (sp)+,r1 /* R1 = error code pushed on stack */
107: andl2 $0x7,r1 /* Only check the last byte */
108: movl $NON_EXIST_MEM,r2 /* R2 = expected error code */
109: cmpl r1,r2
110: beql 1f
111: movl $5,r0 /* R0 = 4; incorrect error code */
112: jmp *badrtn /* pushed on the stack */
113:
114: 1: movl (sp)+,r1 /* Check PC pushed on the stack */
115: movl exp_pc,r2
116: cmpl r1,r2
117: beql 1f
118: jmp 1f /* For now, PC is not checked !! */
119: movl $6,r0 /* R0 = 6; error in PC on stack */
120: jmp *badrtn /* R1 = actual; R2 = expected */
121:
122: 1: movl (sp)+,r1 /* Check PSL pushed on the stack */
123: andl2 $0xfffffff0,r1
124: movl r6,r2 /* R6 = saved PSL before exception */
125: andl2 $0xfffffff0,r2
126: cmpl r1,r2
127: beql 1f
128: movl $7,r0 /* R0 = 7; error in PSL pushed on stack */
129: jmp *badrtn /* R1 = actual; R2 = expected */
130:
131: 1:
132: decl r11
133: jneq berr /* do again */
134: #
135: # VERSABUS timeout error
136: #
137: movl $2,r5 /* R5 = 2; Versabus time out */
138: movab exp_pc3,r4
139: mtpr $0x1c,$IPL /* Set IPL = 0x1c */
140: movab 9f,_scb+BEVEC /* Set new vector to handle Bus error */
141: movl $0xffff8ff0,r1 /* R1 = Vesrabus non_existence address */
142: movab (sp),_savvec0
143: bispsw $15 /* Set PSW flags */
144: movpsl r6 /* Save PSL in R6 */
145: exp_pc3:
146: movb $255,(r1) /* Should cause Versabus time out exception */
147:
148: movl $1,r0 /* R0 = 8; Expected Versabus time out */
149: jmp *badrtn /* exception did not occur. R1 = Versabus adr */
150:
151: .align 2 /* New handler for Versabus time out exception */
152: 9: movab (sp),r1 /* Check current SP = ISP - 16 */
153: movl _savvec0,r2 /* R1 = actual SP */
154: subl2 $16,r2 /* R2 = expected SP */
155: cmpl r1,r2
156: beql 1f
157: movl $2,r0 /* R0 = 9; error in SP after taking Versabus */
158: jmp *badrtn /* timeout exception. */
159: 1:
160: movpsl r1 /* Check current PSL_IS */
161: andl3 $0x04000000,r1,r3 /* Expected PSL_IS = 1 */
162: bneq 1f
163: 2: movl $3,r0 /* R0 = 10; error in current PSL */
164: movl $0x041f0000,r2 /* R1 = actual; R2 = expected */
165: jmp *badrtn
166:
167: 1: andl3 $0x01000000,r1,r3 /* Check PSL_MODE */
168: bneq 2b /* Expected PSL_MODE = Kernel */
169:
170: andl3 $0x001f0000,r1,r3 /* Check PSL_IPL */
171: cmpl $0x001d0000,r3 /* Expected PSL_IPL = 0x1d */
172: bneq 2b
173: #
174: # Check paramters pushed on the stack
175: #
176: movl (sp)+,r3 /* R3 = Versabus type pushed on stack */
177: andl2 $0,r1 /* Don't care for now */
178: movl $0,r2 /* R2 = expected type */
179: cmpl r1,r2
180: beql 1f
181: movl $4,r0 /* R0 = 4; incorrect error code */
182: jmp *badrtn /* pushed on the stack */
183:
184: 1:
185: movl (sp)+,r3 /* R3 = error code pushed on SP */
186: andl3 $0x7,r3,r1 /* Only check the last 3 bits */
187: movl $VB_TOUT,r2 /* R2 = expected error code */
188: cmpl r1,r2
189: beql 1f
190: movl $5,r0 /* R0 = 5; incorrect error code pushed on SP */
191: jmp *badrtn
192: 1:
193: movl (sp)+,r1 /* R1 = PC pushed on stack */
194: movab exp_pc3,r2 /* R2 = expected PC */
195: cmpl r1,r2
196: beql 1f
197: jmp 1f /* For now, PC is not checked !! */
198: movl $6,r0 /* R0 = 6; incorrect PC pushed on SP */
199: jmp *badrtn
200: 1:
201: movl (sp)+,r1 /* R1 = PSL pushed on SP */
202: andl2 $0xfffffff0,r1
203: movl r6,r2 /* R2 = expected PSL */
204: andl2 $0xfffffff0,r2
205: cmpl r1,r2
206: beql 1f
207: movl $7,r0 /* R0 = 7; incorrect PSL pushed on SP */
208: jmp *badrtn
209: 1:
210: decl bloop
211: jeql 1f
212: jmp _b2 /* Try again this time code is in */
213: /* instruction cache */
214: 1:
215: movl _savvec2,_scb+BEVEC /* Restore original bus error vector */
216: movl _savvec0,sp /* Restore current SP */
217: mtpr $31,$IPL /* Set IPL = HIGH */
218: mtpr $1,$PADC /* Slow it down to loop */
219: ret
220:
221: .align 2
222: exp_pc: .long 0
223: bloop: .long 1
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