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Power 6/32 Unix version 1.21

#
#	*bus error event test
#
#
#	*non_existent memory	(done)
#	*versabus timeout	(done)
#	*uncorrectable memory error	(not done)
#	*versabus error		(not done)
#	*versabus parity error	(not done)
#
#     	R4 : PC that failed
#	R5 : type of fault is testing
#	     1 - Non existence memory
#	     2 - Versabus time out
#	R0 : error code
#	     1 - expected fault didnot happen
#	     	 R1 : memory address
#	     2 - error in SP after taking fault
#		 R1 : actual , R2 : expected
#	     3 - error in PSL after taking fault
#		 R1 : actual , R2 : expected
#	     4 - error in Versabus type pushed on stack
#		 R1 : actual , R2 : expected
#	     5 - error in error code pushed on stack
#		 R1 : actual , R2 : expected
#	     6 - error in PC pushed on stack
#		 R1 : actual , R2 : expected
#	     7 - error in PSL pushed on stack
#		 R1 : actual , R2 : expected
#
#	constants --  errorcodes from versabus 	(not final yet)	

	.set	NON_EXIST_MEM,6	
	.set	VB_TOUT,4

	.globl	_be_evt
_be_evt:
	.word	0x1fff
	mtpr	$0x1c,$IPL
	movl	$0,*$HSR		/* Clear HISR, SISR	*/
	movl	$0,*$SSR
	movab	(sp),_savvec0		/* Save current SP	*/
	mtpr	_savvec0,$ISP		/* Init. ISP 		*/
	/*mfpr	$KSP,_savvec9		/* Save cuurent KSP */
	/*mfpr	$USP,_savveca		/* Save cuurent USP */
	movpsl	_savvec1		/* Save current PSL	*/
	movl	_scb+BEVEC,_savvec2	/* Save bus error vector	*/
	movab	9f,_scb+BEVEC		/* Set new vector for Bus error */
	movl	$1,bloop
_b2:
	movl	$2,r11			/* R11 = counter */

#	Non_existent memory error

berr:
	movl	$1,r5			/* R5 = 1; Non_existence memory */
	movl	$0x03fffff0,r1		/* R1 = Non_existence memory address */
	movpsl	r6			/* R6 = saved expected PSL	*/	
	cmpl	$1,r11
	jeql	exp_pc2
exp_pc1:
	movab	epc1,r4
epc1:	tstl	(r1)		/* Should cause Non_existence memory fault */
	movl	$1,r0		/* R0 = 1; error code : Expected fault did */
	jmp	*badrtn		/* not happen. R1 = memory address	*/
exp_pc2:
	movab	epc2,r4
epc2:	clrl	(r1)		/* Should cause Non_existence memory fault */
	movl	$1,r0		/* R0 = 1; error code : Expected fault did */
	jmp	*badrtn		/* not happen. R1 = memory address	*/
#
#	 Bus error event handler
#
	.align	2
9:	movab	(sp),r1
	movl	_savvec0,r2	/* Check current SP = ISP - 16 		*/
	subl2	$16,r2		/* PC,PSL and 2 params should be on stack */
	cmpl	r1,r2
	beql	1f
2:	movl	$2,r0		/* R0 = 2; error in SP after taking fault */
	jmp	*badrtn		/* SP not decremented by 16 after Bus error */
1:
	movpsl	r1			/* Check current PSL_MODE 	*/
	andl3	$0x04000000,r1,r3	/* Expected PSL_MODE = Kernel	*/
	bneq	1f
2:	movl	$3,r0			/* R0 = 3; PSL not set correct */
	movl	$0x041d0000,r2		/* after taking Bus error exception */
	jmp	*badrtn
1:	andl3	$0x01000000,r1,r3	/* Check current PSL_IS		*/
	bneq	2b			/* Expected PSL_IS = 1		*/
	andl3	$0x001d0000,r1,r3	/* Check PSL_IPL = 0x1d		*/
	cmpl	$0x001d0000,r3
	bneq	2b
#
#	Check parameters pushed on SP
#
	movl	(sp)+,r3		/* R3 = Versabus type pushed on stack */
	andl3	$0,r3,r1		/* For now , don't care		*/
	movl	$0,r2			/* R2 = expected type (don't care)  */
	cmpl	r1,r2
	beql	1f
	movl	$4,r0			/* R0 = 4; incorrect error code */
	jmp	*badrtn			/* pushed on the stack 		*/

1:	movl	(sp)+,r1		/* R1 = error code pushed on stack */
	andl2	$0x7,r1			/* Only check the last  byte	*/
	movl	$NON_EXIST_MEM,r2	/* R2 = expected error code 	*/
	cmpl	r1,r2
	beql	1f
	movl	$5,r0			/* R0 = 4; incorrect error code */
	jmp	*badrtn			/* pushed on the stack 		*/

1:	movl	(sp)+,r1		/* Check PC pushed on the stack	*/
	movl	exp_pc,r2
	cmpl	r1,r2
	beql	1f
	jmp	1f		/* For now, PC is not checked !!	*/
	movl	$6,r0		/* R0 = 6; error in PC on stack		*/
	jmp	*badrtn		/* R1 = actual; R2 = expected		*/

1:	movl	(sp)+,r1	/* Check PSL pushed on the stack	*/
	andl2	$0xfffffff0,r1
	movl	r6,r2		/* R6 = saved PSL before exception	*/
	andl2	$0xfffffff0,r2
	cmpl	r1,r2
	beql	1f
	movl	$7,r0		/* R0 = 7; error in PSL pushed on stack */
	jmp	*badrtn		/* R1 = actual; R2 = expected 		*/

1:
	decl	r11
	jneq	berr		/* do again */
#
#	VERSABUS timeout error
#
	movl	$2,r5		/* R5 = 2; Versabus time out */
	movab	exp_pc3,r4
	mtpr	$0x1c,$IPL	/* Set IPL = 0x1c	*/
	movab	9f,_scb+BEVEC	/* Set new vector to handle Bus error */
	movl	$0xffff8ff0,r1	/* R1 = Vesrabus non_existence address */
	movab	(sp),_savvec0
	bispsw	$15		/* Set PSW flags	*/
	movpsl	r6		/* Save PSL in R6	*/	
exp_pc3:
	movb	$255,(r1)	/* Should cause Versabus time out exception */
	
	movl	$1,r0		/* R0 = 8; Expected Versabus time out	*/
	jmp	*badrtn		/* exception did not occur. R1 = Versabus adr */

	.align	2	/* New handler for Versabus time out exception */
9:	movab	(sp),r1		/* Check current SP = ISP - 16		*/
	movl	_savvec0,r2	/* R1 = actual SP 			*/
	subl2	$16,r2		/* R2 = expected SP			*/
	cmpl	r1,r2
	beql	1f
	movl	$2,r0		/* R0 = 9; error in SP after taking Versabus */
	jmp	*badrtn		/* timeout exception.	*/
1:
	movpsl	r1			/* Check current PSL_IS */
	andl3	$0x04000000,r1,r3	/* Expected PSL_IS = 1	*/
	bneq	1f
2:	movl	$3,r0		/* R0 = 10; error in current PSL 	*/
	movl	$0x041f0000,r2	/* R1 = actual; R2 = expected		*/
	jmp	*badrtn

1:	andl3	$0x01000000,r1,r3	/* Check PSL_MODE	*/
	bneq	2b			/* Expected PSL_MODE = Kernel */

	andl3	$0x001f0000,r1,r3	/* Check PSL_IPL  		*/
	cmpl	$0x001d0000,r3		/* Expected PSL_IPL = 0x1d	*/
	bneq	2b
#
#	Check paramters pushed on the stack
#
	movl	(sp)+,r3		/* R3 = Versabus type pushed on stack */
	andl2	$0,r1			/* Don't care for now		*/
	movl	$0,r2			/* R2 = expected type	 	*/
	cmpl	r1,r2
	beql	1f
	movl	$4,r0			/* R0 = 4; incorrect error code */
	jmp	*badrtn			/* pushed on the stack 		*/

1:
	movl	(sp)+,r3		/* R3 = error code pushed on SP */
	andl3	$0x7,r3,r1		/* Only check the last 3 bits	*/
	movl	$VB_TOUT,r2		/* R2 = expected error code	*/
	cmpl	r1,r2
	beql	1f
	movl	$5,r0		/* R0 = 5; incorrect error code pushed on SP */
	jmp	*badrtn
1:
	movl	(sp)+,r1		/* R1 = PC pushed on stack	*/
	movab	exp_pc3,r2		/* R2 = expected PC		*/
	cmpl	r1,r2
	beql	1f
	jmp	1f		/* For now, PC is not checked !!	*/
	movl	$6,r0		/* R0 = 6; incorrect PC pushed on SP */
	jmp	*badrtn
1:
	movl	(sp)+,r1		/* R1 = PSL pushed on SP 	*/
	andl2	$0xfffffff0,r1
	movl	r6,r2			/* R2 = expected PSL		*/
	andl2	$0xfffffff0,r2
	cmpl	r1,r2
	beql	1f
	movl	$7,r0		/* R0 = 7; incorrect PSL pushed on SP  */
	jmp	*badrtn
1:
	decl	bloop
	jeql	1f
	jmp	_b2		/* Try again this time code is in */
				/* instruction cache */
1:
	movl	_savvec2,_scb+BEVEC	/* Restore original bus error vector */
	movl	_savvec0,sp		/* Restore current SP		*/
	mtpr	$31,$IPL		/* Set IPL = HIGH		*/
	mtpr	$1,$PADC	/* Slow it down to loop */
	ret

	.align	2
exp_pc: .long	0
bloop:	.long	1

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