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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / event|
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1.1 root 1: #
2: # Multiple events tests :
3: # Check out the order of servicing multiple events
4: #
5:
6:
7: .set SFEVEC,0x36 /* Vector no. for SFE */
8: .set TTVEC,0x32 /* Vector no. for Trace trap */
9: .set SINT11,0x14 /* Vector no. for Soft int#11 */
10:
11: .globl _mulevt
12: _mulevt:
13: .word 0x1fff
14:
1.1.1.2 ! root 15: mtpr $18,$IPL /* do not allow clock interrupt */
1.1 root 16: mtpr $_Sysmap,$P0BR
17: mtpr $_Syssize,$P0LR
18: clrl _Udata
19: movl fp,_saved_fp /* Save FP */
20:
21: movl $SINT11,r1
22: movl _scb[r1],_savvec5 /* Save SOFTINT#11 vector */
23: movab si11_hdr,_scb[r1] /* Set new Soft int#11 vector */
24: /* Make User area User accessible */
25: mfpr $P0BR,r0
26: andl3 $0x3fffffff,$_Ucode,r1
27: shar $PGSHIFT,r1,r1 /* Get Page no */
28: orl2 $0xf8000000,(r0)[r1] /* Set User READ/WRITE */
29: mtpr $1,$TBIA
30:
31:
32: andl3 $_pcb0,$0x3fffffff,r1 /* Initialize PCB slightly */
33: mtpr r1,$PCBB /* Set PCBB */
34: orl2 $0xc0000000,r1
35: movab (sp),r7
36: subl3 $8,r7,_exp_isp /* Set expected ISP */
37: subl3 $40,r7,PCB_KSP(r1) /* Set PCB_KSP to (SP-40) */
38: movl PCB_KSP(r1),_exp_ksp /* Set expected SP after except. */
39: subl3 $80,r7,PCB_USP(r1) /* Set PCB_USP to (SP-80) */
40: mfpr $P0BR,PCB_P0BR(r1) /* Set PCB_P0BR */
41: mfpr $P0LR,PCB_P0LR(r1) /* Set PCB_P0BR */
42: movl $0x41000110,_exp_psl /* Set PCB_PSL : U_mode, */
43: movl _exp_psl,PCB_PSL(r1) /* SFE set, T_bit and TP_bit set */
44:
45: movab _Ucode,_exp_pc
46: movl _exp_pc,PCB_PC(r1) /* Set PCB_PC */
1.1.1.2 ! root 47: mtpr $0xb,$SIRR /* Request soft int#11 */
1.1 root 48: ldpctx /* Switch to Kernel SP, push PSL,PC */
49: mrei:
1.1.1.2 ! root 50: mtpr $0xc,$IPL /* Set IPL to 12 */
1.1 root 51: rei /* Should get soft int.#11 ! */
52:
53: fini:
54: movl _saved_fp,fp /* Restore FP */
55: ret /* Done with this sucker !! */
56: #
57: # **************
58: # Event Handlers
59: # **************
60: # /* **************************** */
61: .align 2 /* SFE exception handler */
62: sfehdlr: /* **************************** */
63: movpsl r10 /* R10 = PSL after exception */
1.1.1.2 ! root 64: mtpr $18,$IPL /* Disable clock during handler */
1.1 root 65: andl3 $0x101f0000,r10,r1 /* R1 = IS,IPL after exception */
66: clrl r2 /* R2 = Expected IS,IPL */
67: cmpl r1,r2
68: jeql 1f
69: movl $6,r0 /* Error : IPL not correct after */
70: jmp *badrtn /* SFE exception. R0 = error code */
71: 1:
72: movab (sp),r1 /* R1 : KSP after exception */
73: movl _exp_ksp,r2 /* R2 : Expected KSP */
74: cmpl r1,r2
75: beql 1f
76: movl $7,r0 /* Error : SP not correct after */
77: jmp *badrtn /* SFE exception */
78: 1:
79: movab (sp),r9
80: movl (r9),r1 /* R1 : PC on SP after exception */
81: movl _exp_pc,r2 /* R2 : expected PC */
82: cmpl r1,r2
83: beql 1f
84: movl $8,r0 /* Error : PC on SP not correct after */
85: jmp *badrtn /* SFE exception */
86: 1:
87: movl 4(r9),r1 /* R1 : PSL on SP after exception */
88: movl _exp_psl,r2 /* R2 : Expected PSL */
89: cmpl r1,r2
90: beql 1f
91: movl $9,r0 /* Error : PSL on SP incorrect after */
92: jmp *badrtn /* SFE exception */
93: 1:
94: andl3 $0xbfffffff,_exp_psl,_exp_psl /* Clear PSL_TP */
95: mfpr $ISP,r1 /* R1 : Expected ISP */
96: movl _exp_isp,r2 /* R2 : Expected ISP */
97: cmpl r1,r2
98: beql 1f
99: movl $10,r0 /* Error : PSL on SP incorrect after */
100: jmp *badrtn /* SFE exception */
101: 1:
102: movl $TTVEC,r1
103: movl _scb[r1],_savvec6 /* Save TRACE trap vector */
104: movab tt_hdlr,_scb[r1] /* Set new TRACE vector : Just REI */
1.1.1.2 ! root 105: mtpr $0,$IPL /* restore IPL (enable clock) */
1.1 root 106: rei /* Should take Trace trap */
107: #
108: #
109: # /* **************************** */
110: .align 2 /* TRACE trap handler */
111: tt_hdlr: /* **************************** */
1.1.1.2 ! root 112: movpsl r10 /* R10 = PSL after exception */
! 113: mtpr $0x1f,$IPL
1.1 root 114: movl _Udata,r1 /* Check if 1 inst. executed */
115: clrl r2 /* when REI from SFE handler.. */
116: cmpl r1,r2
117: jeql 1f
118: movl $11,r0 /* Error : did not get Trace trap */
119: jmp *badrtn /* when PSL_TP and PSL_T were set */
120: 1:
121: andl3 $0x101f0000,r10,r1 /* R1 = IS,IPL after exception */
122: clrl r2 /* R2 = Expected IS,IPL */
123: cmpl r1,r2
124: jeql 1f
125: movl $12,r0 /* Error : IPL not correct after */
126: jmp *badrtn /* SFE exception. R0 = error code */
127: 1:
128: movab (sp),r1 /* R1 : KSP after exception */
129: movl _exp_ksp,r2 /* R2 : Expected KSP */
130: cmpl r1,r2
131: beql 1f
132: movl $13,r0 /* Error : SP not correct after */
133: jmp *badrtn /* Trace trap exception */
134: 1:
135: movab (sp),r9
136: movl (r9),r1 /* R1 : PC on SP after exception */
137: movl _exp_pc,r2 /* R2 : expected PC */
138: cmpl r1,r2
139: beql 1f
140: movl $14,r0 /* Error : PC on SP not correct after */
141: jmp *badrtn /* Trace trap exception */
142: 1:
143: movl 4(r9),r1 /* R1 : PSL on SP after exception */
144: movl _exp_psl,r2 /* R2 : Expected PSL */
145: cmpl r1,r2
146: beql 1f
147: movl $15,r0 /* Error : PSL on SP incorrect after */
148: jmp *badrtn /* Trace trap exception */
149: 1:
150: mfpr $ISP,r1 /* R1 : Expected ISP */
151: movl _exp_isp,r2 /* R2 : Expected ISP */
152: cmpl r1,r2
153: beql 1f
154: movl $16,r0 /* Error : PSL on SP incorrect */
155: jmp *badrtn
156: 1:
157: svpctx /* Switch to ISP */
158: mtpr $0x1f,$IPL
159: jmp fini
160: #
161: #
162: # /* **************************** */
163: .align 2 /* Soft Int.#11 handler */
164: si11_hdr: /* **************************** */
165: movpsl r10 /* R10 : PSL after taken soft int */
1.1.1.2 ! root 166: mtpr $18,$IPL /* Disable clock during handler */
1.1 root 167: andl3 $0x1f0000,r10,r1 /* R1 : Actual IPL after int. */
168: movl $0x0b0000,r2 /* R2 : Expected IPL */
169: cmpl r1,r2
170: beql 1f
171: movl $1,r0 /* Error : in IPL after taken int. */
172: jmp *badrtn
173: 1:
174: movab (sp),r7 /* R7 : current ISP */
175: movl r7,r1
176: movl _exp_isp,r2 /* R2 : expected ISP */
177: cmpl r1,r2
178: beql 1f
179: movl $2,r0 /* Error : in ISP after taken int. */
180: jmp *badrtn
181: 1:
182: addl3 $8,r7,_exp_isp /* Expected ISP after SFE exception */
183: movl (r7),r1 /* R1 : User PC on stack */
184: movl _exp_pc,r2 /* R2 : expected PC */
185: cmpl r1,r2
186: beql 1f
187: movl $3,r0 /* Error : PC on SP not correct after */
188: jmp *badrtn /* taking software int.#11 */
189: 1:
190: movl 4(r7),r1 /* R1 : User PSL on SP */
191: movl _exp_psl,r2 /* R2 : Expected PSL */
192: cmpl r1,r2
193: beql 1f
194: movl $4,r0 /* Error : PSL on SP incorrect after */
195: jmp *badrtn /* taking software int.#11 */
196: 1:
197: andl3 $0xfffffeff,_exp_psl,_exp_psl /* Mask out SFE bit */
198: mfpr $PCBB,r3
199: orl2 $0xc0000000,r3 /* VA of PCBB */
200: movl (r3),r1 /* R1 : Actual KSP */
201: movl _exp_ksp,r2 /* R2 : Expected KSP */
202: cmpl r1,r2
203: beql 1f
204: movl $5,r0 /* Error : PCBB_KSP incorrect after */
205: jmp *badrtn /* taking software int.#11 */
206: 1:
207: subl3 $8,r1,_exp_ksp /* Expected KSP after SFE exception */
208: movl $SFEVEC,r1
209: movl _scb[r1],_savvec7 /* Save SFE original vector */
210: movab sfehdlr,_scb[r1] /* Set new SFE handler */
1.1.1.2 ! root 211: mtpr $0xb,$IPL /* restore IPL (enable clock) */
1.1 root 212: rei /* Should take SFE exception */
213: halt
214:
215: #
216: # Data area
217: #
218: .align 2
219: _exp_pc:
220: .long 0
221: _exp_psl:
222: .long 0
223: _exp_ksp:
224: .long 0
225: _exp_isp:
226: .long 0
227: #
228: # User code area
229: #
230: .set PATERN,0xabababab
231: _Ucode:
232: movl $PATERN,_Udata /* Since the TP bit is on, this */
233: halt /* instr. will not be executed, goto Trace handler */
234: .align 2
235: _Udata :
236: .long 0
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