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1.1 root 1: # prvreg.s 1.0 9/3/82 */
2: #
3: # *Privileged registers test : MTPR/MFPR
4: #
5: # R2 : expected value
6: # R3 : actual value
7: # R4 : privilege register no. that fail
8:
9:
10: .globl _prvreg
11: _prvreg:
12: .word 0x1fff
13: movl $0x55555554,r2
14: mtpr r2,$SBR /* Entry point : Register to Memory */
15: mfpr $SBR,r3 /* Entry point : Memory to Register */
16: cmpl r2,r3
17: beql 1f
18: movl $0,r4 /* R4 = privilege reg. no that failed */
19: jmp *badrtn /* **** - r2 & r3 contains exp */
20: /* and observed values; r4 = prv reg no.*/
21: 1:
22: mtpr $0xaaaaaaa4,$SBR /* Entry point : Memory to Memory */
23: mfpr $SBR,prvar /* Entry point : Memory to Memory */
24: cmpl $0xaaaaaaa4,prvar
25: beql 2f
26: movl $0,r4 /* R4 = privilege reg. no that failed */
27: movl $0xaaaaaaa4,r2 /* R2 = Expected value; R3 = Actual value */
28: movl prvar,r3
29: jmp *badrtn
30: 2:
31:
32: movl $SLR,r12 /* System Length Register */
33: movl $0x35555555,r2
34: mtpr r2,r12 /* Entry point : Register to Register */
35: mfpr r12,r3 /* Entry point : Register to Register */
36: cmpl r2,r3
37: beql 1f
38: movl $1,r4 /* R4 = privilege reg. no that failed */
39: jmp *badrtn /***** - r2 & r3 contains exp */
40: /*and observed values; r4 = prv reg no. */
41: 1:
42: mtpr $0x3aaaaaaa,r12 /* Entry point : Memory to register */
43: mfpr r12,prvar /* Entry point : Register to Memory */
44: cmpl $0x3aaaaaaa,prvar
45: beql 2f
46: movl $1,r4 /* R4 = privilege reg. no that failed */
47: movl $0x3aaaaaaa,r2 /* R2 = Expected value; R3 = Actual value */
48: movl prvar,r3
49: jmp *badrtn
50: 2:
51:
52: movl $0x55555554,r2 /*p0 base register */
53: mtpr r2,$P0BR
54: movl $P0BR,_cache1
55: mfpr _cache1,r3 /* Cache to register */
56: cmpl r2,r3
57: beql 1f
58: movl $2,r4 /* R4 = privilege reg. no that failed */
59: jmp *badrtn /***** - r2 & r3 contains exp */
60: /*and observed values; r4 = prv reg no. */
61: 1:
62: movl $0xaaaaaaa4,r2
63: mtpr r2,$P0BR
64: mfpr _cache1,_cache2 /* Cache to cache */
65: movl _cache2,r3
66: cmpl r2,r3
67: beql 2f
68: movl $2,r4 /*reg no. */
69: jmp *badrtn /***** - r2 & r3 contains exp */
70: /*and observed values; r4 = prv reg no. */
71: 2:
72:
73: movl $0x35555555,r2 /*p0 length register */
74: andl2 $0x1fffffff,r2
75: mtpr r2,$P0LR
76: mfpr $P0LR,r3
77: cmpl r2,r3
78: beql 1f
79: movl $3,r4 /*reg no. */
80: jmp *badrtn /***** - r2 & r3 contains exp */
81: /*and observed values; r4 = prv reg no. */
82: 1:
83: movl $0x3aaaaaaa,r2
84: andl2 $0x1fffffff,r2
85: mtpr r2,$P0LR
86: mfpr $P0LR,r3
87: cmpl r2,r3
88: beql 2f
89: movl $3,r4 /*reg no. */
90: jmp *badrtn /***** - r2 & r3 contains exp */
91: /*and observed values; r4 = prv reg no. */
92: 2:
93:
94: movl $0x55555554,r2 /*p1 base register */
95: movl $P1BR,_sreg
96: mtpr r2,_sreg
97: mfpr $P1BR,r3
98: cmpl r2,r3
99: beql 1f
100: movl $4,r4 /*reg no. */
101: jmp *badrtn /***** - r2 & r3 contains exp */
102: /*and observed values; r4 = prv reg no. */
103: 1:
104: movl $0xaaaaaaa4,r2
105: mtpr r2,$P1BR
106: mfpr $P1BR,r3
107: cmpl r2,r3
108: beql 2f
109: movl $4,r4 /*reg no. */
110: jmp *badrtn /***** - r2 & r3 contains exp */
111: /*and observed values; r4 = prv reg no. */
112: 2:
113:
114:
115: movl $0x35555555,r2 /*p1 length register */
116: andl2 $0x1fffffff,r2
117: mtpr r2,$P1LR
118: mfpr $P1LR,r3
119: cmpl r2,r3
120: beql 1f
121: movl $5,r4 /*reg no. */
122: jmp *badrtn /***** - r2 & r3 contains exp */
123: /*and observed values; r4 = prv reg no. */
124: 1:
125: movl $0x3aaaaaaa,r2
126: andl2 $0x1fffffff,r2
127: mtpr r2,$P1LR
128: mfpr $P1LR,r3
129: cmpl r2,r3
130: beql 2f
131: movl $5,r4 /*reg no. */
132: jmp *badrtn /***** - r2 & r3 contains exp */
133: /*and observed values; r4 = prv reg no. */
134: 2:
135:
136:
137: movl $0x55555554,r2 /*p2 base register */
138: mtpr r2,$P2BR
139: mfpr $P2BR,r3
140: cmpl r2,r3
141: beql 1f
142: movl $6,r4 /*reg no. */
143: jmp *badrtn /***** - r2 & r3 contains exp */
144: /*and observed values; r4 = prv reg no. */
145: 1:
146: movl $0xaaaaaaa4,r2
147: mtpr r2,$P2BR
148: mfpr $P2BR,r3
149: cmpl r2,r3
150: beql 2f
151: movl $6,r4 /*reg no. */
152: jmp *badrtn /***** - r2 & r3 contains exp */
153: /*and observed values; r4 = prv reg no. */
154: 2:
155:
156: movl $0x35555555,r2 /*p2 length register */
157: andl2 $0x1fffffff,r2
158: mtpr r2,$P2LR
159: mfpr $P2LR,r3
160: cmpl r2,r3
161: beql 1f
162: movl $7,r4 /*reg no. */
163: jmp *badrtn /***** - r2 & r3 contains exp */
164: /*and observed values; r4 = prv reg no. */
165: 1:
166: movl $0x3aaaaaaa,r2
167: andl2 $0x1fffffff,r2
168: mtpr r2,$P2LR
169: mfpr $P2LR,r3
170: cmpl r2,r3
171: beql 2f
172: movl $7,r4 /*reg no. */
173: jmp *badrtn /***** - r2 & r3 contains exp */
174: /*and observed values; r4 = prv reg no. */
175: 2:
176:
177: movl $10,r2
178: mtpr r2,$IPL
179: mfpr $IPL,r3
180: cmpl r2,r3
181: beql 1f
182: movl $8,r4 /*reg no. */
183: jmp *badrtn /***** - r2 & r3 contains exp */
184: /*and observed values; r4 = prv reg no. */
185: 1:
186: movl $21,r2
187: mtpr r2,$IPL
188: mfpr $IPL,r3
189: cmpl r2,r3
190: beql 2f
191: movl $8,r4 /*reg no. */
192: jmp *badrtn /***** - r2 & r3 contains exp */
193: /*and observed values; r4 = prv reg no. */
194: 2:
195: movl $31,r2
196: mtpr r2,$IPL
197: mfpr $IPL,r3
198: cmpl r2,r3
199: beql 2f
200: movl $8,r4 /*reg no. */
201: jmp *badrtn /***** - r2 & r3 contains exp */
202: /*and observed values; r4 = prv reg no. */
203: 2:
204:
205: movl $0xffffc,r2 /*PCB base register */
206: mtpr r2,$PCBB
207: mfpr $PCBB,r3
208: cmpl r2,r3
209: beql 1f
210: movl $14,r4 /*reg no. */
211: jmp *badrtn /***** - r2 & r3 contains exp */
212: /*and observed values; r4 = prv reg no. */
213: 1:
214: movl $0xeeeec,r2
215: mtpr r2,$PCBB
216: mfpr $PCBB,r3
217: cmpl r2,r3
218: beql 2f
219: movl $14,r4 /*reg no. */
220: jmp *badrtn /***** - r2 & r3 contains exp */
221: /*and observed values; r4 = prv reg no. */
222: /*LET US HOPE WE DON'T GET EXCEPTION DURING THIS TEST */
223:
224: 2:
225: movl $0x55555554,r2 /*int stck ptr register */
226: mtpr r2,$ISP
227: mfpr $ISP,r3
228: cmpl r2,r3
229: beql 1f
230: movl $15,r4 /*reg no. */
231: jmp *badrtn /***** - r2 & r3 contains exp */
232: /*and observed values; r4 = prv reg no. */
233: 1:
234: movl $0xaaaaaaac,r2
235: mtpr r2,$ISP
236: mfpr $ISP,r3
237: cmpl r2,r3
238: beql 2f
239: movl $15,r4 /*reg no. */
240: jmp *badrtn /***** - r2 & r3 contains exp */
241: /*and observed values; r4 = prv reg no. */
242: 2:
243: movl $0xaaaa,r2 /* Soft int summary register */
244: movl r2,*$SSR /* is a read only register */
245: mfpr $SISR,r3 /* funtional test no comparison */
246: cmpl r2,r3
247: beql 1f
248: movl $17,r4 /*reg no. */
249: jmp *badrtn /***** - r2 & r3 contains exp */
250: /*and observed values; r4 = prv reg no. */
251: 1:
252: movl $0x5555,r2
253: movl r2,*$SSR
254: mfpr $SISR,r3
255: cmpl r2,r3
256: beql 2f
257: movl $17,r4 /*reg no. */
258: jmp *badrtn /***** - r2 & r3 contains exp */
259: /*and observed values; r4 = prv reg no. */
260: 2:
261: clrl *$SSR
262: movl $0xfff000,r2
263: movab _iob4,r9
264: mtpr r9,$PCBB /* Init PCBB */
265: mtpr r2,$USP
266: mfpr $USP,r3
267: cmpl r2,r3
268: beql 2f
269: movl $20,r4 /*reg no. */
270: jmp *badrtn /***** - r2 & r3 contains exp */
271: /*and observed values; r4 = prv reg no. */
272: 2:
273: movl $0xffe000,r2
274: mtpr r2,$KSP
275: mfpr $KSP,r3
276: cmpl r2,r3
277: beql 2f
278: movl $19,r4 /*reg no. */
279: jmp *badrtn /***** - r2 & r3 contains exp */
280: /*and observed values; r4 = prv reg no. */
281: 2:
282: movl *$0x414,r12 /* Save original SCB value in R12 */
283: movl $0xeee000,r2
284: mtpr r2,$SCBB
285: mfpr $SCBB,r3
286: cmpl r2,r3
287: beql 2f
288: movl $18,r4 /*reg no. */
289: jmp *badrtn /***** - r2 & r3 contains exp */
290: /*and observed values; r4 = prv reg no. */
291: 2:
292: movl r12,*$0x414 /* Restore original SCB */
293: mtpr $0x1f,$IPL /* Set IPL to High */
294: movl $0x8000,r2
295: mtpr $0xf,$SIRR /* Set SIRR at level 15 */
296: mfpr $SISR,r3 /* Read software int. summary register */
297: cmpl $0x8000,r3 /* Should indicate int. pending at level 15 */
298: beql 2f
299: movl $16,r4 /*reg no. */
300: jmp *badrtn /***** - r2 & r3 contains exp */
301: /*and observed values; r4 = prv reg no. */
302: 2:
303: mtpr $0,$SIRR /* Clear SIRR */
304: clrl *$SSR
305: movl $0xaa,r2
306: mtpr r2,$DCK
307: movl *$TDCK,r3
308: cmpl r2,r3
309: beql 2f
310: movl $12,r4 /*reg no. */
311: jmp *badrtn /***** - r2 & r3 contains exp */
312: /*and observed values; r4 = prv reg no. */
313: 2:
314: movl $0xbb,r2
315: mtpr r2,$CCK
316: movl *$TCCK,r3
317: cmpl r2,r3
318: beql 2f
319: movl $13,r4 /*reg no. */
320: jmp *badrtn /***** - r2 & r3 contains exp */
321: /*and observed values; r4 = prv reg no. */
322: 2:
323: mtpr $0x1f,$IPL
324: movl $0x150010,r2
325: movl r2,*$HSR /* Set HISR in processor storage */
326: mfpr $HISR,r3
327: cmpl r2,r3
328: beql 2f
329: movl $26,r4 /*reg no. */
330: jmp *badrtn /***** - r2 & r3 contains exp */
331: /*and observed values; r4 = prv reg no. */
332: 2:
333: clrl *$HSR /* Clear HISR in PSA */
334:
335: movl $0xffe000,r2
336: movl $KSP,_cache1
337: mtpr $0xffe000,_cache1 /* Literal to cache */
338: mfpr $KSP,r3
339: cmpl r2,r3
340: beql 2f
341: movl $27,r4 /* R4 = which part of the test */
342: jmp *badrtn /***** - r2 & r3 contains exp */
343: 2:
344: movl $0xffa000,r2
345: movl r2,_cache2
346: mtpr _cache2,_cache1 /* Cache to cache */
347: mfpr $KSP,r3
348: cmpl r2,r3
349: beql 2f
350: movl $28,r4 /* R4 = which part of the test */
351: jmp *badrtn /***** - r2 & r3 contains exp */
352: 2:
353: movl $0xffb000,r2
354: movl r2,_cache2
355: movl $KSP,r11
356: mtpr _cache2,r11 /* Cache to register */
357: mfpr $KSP,r3
358: cmpl r2,r3
359: beql 2f
360: movl $29,r4 /* R4 = which part of the test */
361: jmp *badrtn /***** - r2 & r3 contains exp */
362: 2:
363: movl $0xffc000,r2
364: movl r2,_cache2
365: mtpr _cache2,$KSP /* Cache to literal */
366: mfpr $KSP,r3
367: cmpl r2,r3
368: beql 2f
369: movl $30,r4 /* R4 = which part of the test */
370: jmp *badrtn /***** - r2 & r3 contains exp */
371: 2:
372: mfpr $MME,r9 /* The following MTPR/MFPR just to see */
373: mtpr $1,$TBIA /* if control return to program !! */
374: mtpr $_iob4,$TBIS
375: mfpr $DCB,r9
376: mtpr $4,$PADC
377: mtpr $_iob4,$P1DC
378: mtpr $2,$PACC
379: mtpr $0,$DCR
380: mfpr $DCR,r9
381: ret /* End of privileged registers test */
382:
383: .align 2
384: prvar: .long 0
385: _cache1:
386: .long 0
387: _cache2:
388: .long 0
389: _sreg: .long 0
390:
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