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Power 6/32 Unix version 1.21

#	prvreg.s	1.0	9/3/82					*/
#
#	*Privileged registers test : MTPR/MFPR
#
#	R2	: expected value		
#	R3	: actual value		
#	R4	: privilege register no. that fail


	.globl	_prvreg
_prvreg:
	.word	0x1fff
	movl	$0x55555554,r2
	mtpr	r2,$SBR		/* Entry point :  Register to Memory	*/
	mfpr	$SBR,r3		/* Entry point :  Memory to Register	*/
	cmpl	r2,r3
	beql	1f
	movl 	$0,r4		/* R4 = privilege reg. no that failed	*/
	jmp    *badrtn			/* **** - r2 & r3 contains exp	*/
				/* and observed values; r4 = prv reg no.*/
1:
	mtpr	$0xaaaaaaa4,$SBR 	/* Entry point : Memory to Memory */
	mfpr	$SBR,prvar		/* Entry point : Memory to Memory */
	cmpl	$0xaaaaaaa4,prvar
	beql	2f
	movl 	$0,r4		/* R4 = privilege reg. no that failed	*/
	movl	$0xaaaaaaa4,r2	/* R2 = Expected value; R3 = Actual value */
	movl	prvar,r3
	jmp    *badrtn
2:

	movl	$SLR,r12	/* System Length Register		*/
	movl	$0x35555555,r2
	mtpr	r2,r12		/* Entry point : Register to Register	*/
	mfpr	r12,r3		/* Entry point : Register to Register	*/
	cmpl	r2,r3
	beql	1f
	movl 	$1,r4		/* R4 = privilege reg. no that failed	*/
	jmp    *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
1:
	mtpr	$0x3aaaaaaa,r12	/* Entry point : Memory to register	*/
	mfpr	r12,prvar	/* Entry point : Register to Memory	*/
	cmpl	$0x3aaaaaaa,prvar
	beql	2f
	movl 	$1,r4		/* R4 = privilege reg. no that failed	*/
	movl	$0x3aaaaaaa,r2	/* R2 = Expected value; R3 = Actual value */
	movl	prvar,r3
	jmp     *badrtn	
2:

	movl	$0x55555554,r2			/*p0 base  register	*/
	mtpr	r2,$P0BR
	movl	$P0BR,_cache1
	mfpr	_cache1,r3		/* Cache to register */
	cmpl	r2,r3
	beql	1f
	movl 	$2,r4		/* R4 = privilege reg. no that failed	*/
	jmp    *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
1:
	movl	$0xaaaaaaa4,r2			
	mtpr	r2,$P0BR
	mfpr	_cache1,_cache2		/* Cache to cache */
	movl	_cache2,r3
	cmpl	r2,r3
	beql	2f
	movl $2,r4				/*reg no.		*/
	jmp    *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
2:

	movl	$0x35555555,r2			/*p0 length  register	*/
	andl2	$0x1fffffff,r2
	mtpr	r2,$P0LR
	mfpr	$P0LR,r3
	cmpl	r2,r3
	beql	1f
	movl $3,r4				/*reg no.		*/
	jmp    *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
1:
	movl	$0x3aaaaaaa,r2			
	andl2	$0x1fffffff,r2
	mtpr	r2,$P0LR
	mfpr	$P0LR,r3
	cmpl	r2,r3
	beql	2f
	movl $3,r4				/*reg no.		*/
	jmp    *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
2:

	movl	$0x55555554,r2			/*p1 base  register	*/
	movl	$P1BR,_sreg
	mtpr	r2,_sreg
	mfpr	$P1BR,r3
	cmpl	r2,r3
	beql	1f
	movl $4,r4				/*reg no.		*/
	jmp    *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
1:
	movl	$0xaaaaaaa4,r2			
	mtpr	r2,$P1BR
	mfpr	$P1BR,r3
	cmpl	r2,r3
	beql	2f
	movl $4,r4				/*reg no.		*/
	jmp    *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
2:


	movl	$0x35555555,r2			/*p1 length  register	*/
	andl2	$0x1fffffff,r2
	mtpr	r2,$P1LR
	mfpr	$P1LR,r3
	cmpl	r2,r3
	beql	1f
	movl $5,r4				/*reg no.		*/
	jmp    *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
1:
	movl	$0x3aaaaaaa,r2			
	andl2	$0x1fffffff,r2
	mtpr	r2,$P1LR
	mfpr	$P1LR,r3
	cmpl	r2,r3
	beql	2f
	movl $5,r4				/*reg no.		*/
	jmp    *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
2:


	movl	$0x55555554,r2			/*p2 base  register	*/
	mtpr	r2,$P2BR
	mfpr	$P2BR,r3
	cmpl	r2,r3
	beql	1f
	movl $6,r4				/*reg no.		*/
	jmp    *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
1:
	movl	$0xaaaaaaa4,r2			
	mtpr	r2,$P2BR
	mfpr	$P2BR,r3
	cmpl	r2,r3
	beql	2f
	movl $6,r4				/*reg no.		*/
	jmp    *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
2:

	movl	$0x35555555,r2			/*p2 length  register	*/
	andl2	$0x1fffffff,r2
	mtpr	r2,$P2LR
	mfpr	$P2LR,r3
	cmpl	r2,r3
	beql	1f
	movl $7,r4				/*reg no.		*/
	jmp    *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
1:
	movl	$0x3aaaaaaa,r2			
	andl2	$0x1fffffff,r2
	mtpr	r2,$P2LR
	mfpr	$P2LR,r3
	cmpl	r2,r3
	beql	2f
	movl $7,r4				/*reg no.		*/
	jmp    *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
2:

	movl	$10,r2
	mtpr	r2,$IPL
	mfpr	$IPL,r3
	cmpl	r2,r3
	beql	1f
	movl $8,r4				/*reg no.		*/
	jmp    *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
1:
	movl	$21,r2			
	mtpr	r2,$IPL
	mfpr	$IPL,r3
	cmpl	r2,r3
	beql	2f
	movl $8,r4				/*reg no.		*/
	jmp    *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
2:
	movl	$31,r2			
	mtpr	r2,$IPL
	mfpr	$IPL,r3
	cmpl	r2,r3
	beql	2f
	movl $8,r4				/*reg no.		*/
	jmp    *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
2:

	movl	$0xffffc,r2			/*PCB base register	*/
	mtpr	r2,$PCBB
	mfpr	$PCBB,r3
	cmpl	r2,r3
	beql	1f
	movl    $14,r4				/*reg no.		*/
	jmp     *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
1:
	movl	$0xeeeec,r2			
	mtpr	r2,$PCBB
	mfpr	$PCBB,r3
	cmpl	r2,r3
	beql	2f
	movl $14,r4				/*reg no.		*/
	jmp    *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
/*LET US HOPE WE DON'T GET EXCEPTION DURING THIS TEST			*/

2:
	mfpr	$ISP,_savvec0		/* save value of ISP	*/
	mtpr	$0x1f,$IPL		/* Set IPL to high	*/
	movl	$0x55555554,r2			/*int stck ptr register	*/
	mtpr	r2,$ISP
	mfpr	$ISP,r3
	cmpl	r2,r3
	beql	1f
	movl $15,r4				/*reg no.		*/
	jmp    *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
1:
	movl	$0xaaaaaaac,r2			
	mtpr	r2,$ISP
	mfpr	$ISP,r3
	cmpl	r2,r3
	beql	2f
	movl $15,r4				/*reg no.		*/
	jmp    *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
2:
	mtpr	_savvec0,$ISP	/* Restore ISP			*/
	movl	$0xaaaa,r2	/* Soft int summary register	*/
	movl	r2,*$SSR	/* is a read only register	*/
	mfpr	$SISR,r3	/* funtional test no comparison	*/
	cmpl	r2,r3
	beql	1f
	movl $17,r4				/*reg no.		*/
	jmp    *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
1:
	movl	$0x5555,r2			
	movl	r2,*$SSR 
	mfpr	$SISR,r3
	cmpl	r2,r3
	beql	2f
	movl    $17,r4				/*reg no.		*/
	jmp    *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
2:
	clrl	*$SSR
	movl	$0xfff000,r2
	movab	_iob4,r9
	mtpr	r9,$PCBB	/* Init PCBB	*/
	mtpr	r2,$USP
	mfpr	$USP,r3
	cmpl	r2,r3
	beql	2f
	movl    $20,r4				/*reg no.		*/
	jmp     *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
2:
	mfpr	$KSP,_savvec9		/* Save KSP	*/
	movl	$0xffe000,r2
	mtpr	r2,$KSP
	mfpr	$KSP,r3
	cmpl	r2,r3
	beql	2f
	movl    $19,r4				/*reg no.		*/
	jmp     *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
2:
	mtpr	_savvec9,$KSP	/* Restore KSP	*/
	movl	*$0x414,r12	/* Save original SCB value in R12	*/
	movl	$0xeee000,r2
	mtpr	r2,$SCBB
	mfpr	$SCBB,r3
	cmpl	r2,r3
	beql	2f
	movl    $18,r4				/*reg no.		*/
	jmp     *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
2:
	movl	r12,*$0x414	/* Restore original SCB 	*/
	mtpr	$0x1f,$IPL	/* Set IPL to High	*/
	movl	$0x8000,r2
	mtpr	$0xf,$SIRR	/* Set SIRR at level 15	*/
	mfpr	$SISR,r3	/* Read software int. summary register */
	cmpl	$0x8000,r3	/* Should indicate int. pending at level 15 */
	beql	2f
	movl    $16,r4				/*reg no.		*/
	jmp     *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
2:
	mtpr	$0,$SIRR	/* Clear SIRR */
	clrl	*$SSR
	movl	$0xaa,r2
	mtpr	r2,$DCK
	movl	*$TDCK,r3
	cmpl	r2,r3
	beql	2f
	movl    $12,r4				/*reg no.		*/
	jmp     *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
2:
	movl	$0xbb,r2
	mtpr	r2,$CCK
	movl	*$TCCK,r3
	cmpl	r2,r3
	beql	2f
	movl    $13,r4				/*reg no.		*/
	jmp     *badrtn			/***** - r2 & r3 contains exp	*/
				/*and observed values; r4 = prv reg no.	*/
2:

	movl	$0xffe000,r2
	movl	$KSP,_cache1
	mtpr	$0xffe000,_cache1	/* Literal to cache */
	mfpr	$KSP,r3
	cmpl	r2,r3
	beql	2f
	movl    $27,r4			/* R4 = which part of the test */
	jmp     *badrtn			/***** - r2 & r3 contains exp	*/
2:
	movl	$0xffa000,r2
	movl	r2,_cache2
	mtpr	_cache2,_cache1		/* Cache to cache */
	mfpr	$KSP,r3
	cmpl	r2,r3
	beql	2f
	movl    $28,r4			/* R4 = which part of the test */
	jmp     *badrtn			/***** - r2 & r3 contains exp	*/
2:
	movl	$0xffb000,r2
	movl	r2,_cache2
	movl	$KSP,r11
	mtpr	_cache2,r11		/* Cache to register */
	mfpr	$KSP,r3
	cmpl	r2,r3
	beql	2f
	movl    $29,r4			/* R4 = which part of the test */
	jmp     *badrtn			/***** - r2 & r3 contains exp	*/
2:
	movl	$0xffc000,r2
	movl	r2,_cache2
	mtpr	_cache2,$KSP		/* Cache to literal */
	mfpr	$KSP,r3
	cmpl	r2,r3
	beql	2f
	movl    $30,r4			/* R4 = which part of the test */
	jmp     *badrtn			/***** - r2 & r3 contains exp	*/
2:
	mtpr	$KSP,_savvec9	/* Restore KSP				*/
	mfpr	$MME,r9		/* The following MTPR/MFPR just to see  */
	mtpr	$1,$TBIA	/* if control return to program !!	*/
	mtpr	$_iob4,$TBIS
	mfpr	$DCB,r9
	mtpr	$4,$PADC
	mtpr	$_iob4,$P1DC
	mtpr	$2,$PACC
	mtpr	$0,$DCR
	mfpr	$DCR,r9
	ret			/* End of privileged registers test	*/

	.align	2
prvar:	.long	0
_cache1:
	.long	0
_cache2:
	.long	0
_sreg:	.long	0

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