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Power 6/32 Unix version 1.21

/*	privileged registers constants (addresses)			*/



	.set	SBR,0			/*system base register		*/
	.set	SLR,1			/*system length reg		*/
	.set	P0BR,2			/*p0 base reg			*/
	.set	P0LR,3			/*p0 length reg			*/
	.set	P1BR,4			/*p1 base reg			*/
	.set	P1LR,5			/*p1 length reg			*/
	.set	P2BR,6			/*p2 base reg			*/
	.set	P2LR,7			/*p2 length reg			*/
	.set	IPL,8			/*int priority level reg	*/
	.set	MME,9			/*memory mgmt enable reg	*/
	.set	TBIA,10			/*trans buf invalidate all	*/
					/*entries			*/
	.set	TBIS,11			/*trans buf invalidate single	*/
					/*entry				*/
	.set	DCK,12			/*data cache key		*/
	.set	CCK,13			/*code cache key		*/
	.set	PCBB,14			/*process control block base	*/
	.set	ISP,15			/*interrupt stack pointer	*/
	.set	SIRR,16			/*software int request reg	*/
	.set	SISR,17			/*software int summary reg	*/
	.set	SCBB,18			/*system control block base reg	*/
	.set	KSP,19			/*kernel stack pointer reg	*/
	.set	USP,20			/*user stack pointer		*/
	.set	DCB,21			/*CPU2 DCB	                */
	.set	PACC,23			/*purge (invalidate) all pages	*/
					/*of process in code cache	*/
	.set	P1DC,24			/*purge one page of data cache	*/
	.set	PADC,25			/*purge all the pages of 	*/
					/*process in data cache		*/
	.set	HISR,26			/* Hardware interrupt summary reg  */
	.set	DCR,27			/* Diagnostic control register  */
	.set	PDCS,28			/* Purge 1 data cache slot      */
	
#
#TAHOE program status longword
#

	.set  	PSL_C,0x00000001	/* carry bit                     */
	.set  	PSL_V,0x00000002	/* overflow bit                  */
	.set  	PSL_Z,0x00000004	/* zero bit                      */
	.set  	Z,0x00000004
	.set  	PSL_N,0x00000008	/* negative bit                  */
	.set  	PSL_T,0x00000010	/* trace enable bit              */
	.set  	PSL_I,0x00000020	/* integer overflow enable bit   */
	.set	PSL_EN_OVFL,0x20	/* integer overflow enable bit   */
	.set	PSL_EN_UNDFL,0x40	/* floating underflow enable     */
	.set  	PSL_DBL,0x80		/* dbl precision Accumulator bit */
	.set  	PSL_IPL,0x001f0000	/* interrupt priority level      */
	.set  	PSL_MOD,0x01000000	/* mode = 1 means user           */
	.set  	PSL_IS,0x04000000	/* interrupt stack               */
	.set  	PSL_TP,0x40000000	/* trace pending                 */

#
# TAHOE page table entry
#/
	.set  	PG_V,0x8000000
	.set  	PG_PROT,0x78000000
	.set  	PG_M,0x04000000
	.set  	PG_USED,0x02000000
	.set  	PG_NC,0x01000000
	.set  	PG_PFNUM,0x003fffff

	.set  	PG_NOACC,0
	.set  	PG_KR,0x40000000
	.set  	PG_KW,0x60000000
	.set  	PG_URKR,0x50000000
	.set  	PG_URKW,0x70000000
	.set  	PG_UW,0x78000000

#*	PCB offsets & diagnostic extension to pcb			*/
#*	PCB is at pcb0							*/


	.set	PCB_SIZE,	 24	
	.set	PCB_KSP,	 0
	.set	PCB_USP,	 4
	.set	PCB_R0,	 	 8
	.set	PCB_R1,	 	 12
	.set	PCB_R2,	 	 16
	.set	PCB_R3,	 	 20
	.set	PCB_R4,	 	 24
	.set	PCB_R5,	 	 28
	.set	PCB_R6,	 	 32
	.set	PCB_R7,	 	 36
	.set	PCB_R8,	 	 40
	.set	PCB_R9,	 	 44
	.set	PCB_R10,	 48
	.set	PCB_R11,	 52
	.set	PCB_R12,	 56
	.set	PCB_R13,	 60
	.set	PCB_PC,	 	 64
	.set	PCB_PSL,	 68
	.set	PCB_P0BR,	 72
	.set	PCB_P0LR,	 76
	.set	PCB_P1BR,	 80
	.set	PCB_P1LR,	 84
	.set	PCB_P2BR,	 88
	.set	PCB_P2LR,	 92
	.set	PCB_ACCM,	 96
	.set	PCB_ACCL,	100
#*
#	Diagnostic pcb extension
#/
	.set	PCB_STAT,	104	/*process status,statistics,id,etc*/



#*	fundamental constants						*/

#*
# fundamental constants of the implementation--
# cannot be changed easily.
#/

	.set  	NBPG,1024
	.set  	PGOFSET,(NBPG-1)	/* byte offset into page */
	.set  	PGSHIFT,10		/* LOG2(NBPG) */
	.set 	HIGH,0x1f


#*	SCB offsets							*/
#*	SCB is at scb							*/

	.set	PFVEC,1*4		/*power fail			*/
	.set	PRVEC,2*4		/*power restore			*/
	.set	CLOCKVEC,7*4		/*hard clock vector		*/
	.set	CRVEC,0xa*4		/*console receive		*/
	.set	CXVEC,44		/*console transmit		*/
	.set	SIVEC1,0x1e*4 		/*software int vec #1		*/
					/*for 2,3,..15, sub 4,8,.. 56	*/
					/*from SIVEC1			*/	
	.set	BEVEC,0x20*4		/*bus error 			*/	
	.set	SYSVEC,0x2b*4		/*system call (kcall)		*/
	.set	PINSTVEC,0x2c*4		/*privileged instruction fault	*/
	.set	PRIVSVEC,0x2c*4		/*privileged instruction fault	*/
	.set	ROVEC,0x2d*4		/*reserved operand fault	*/
	.set	RAVEC,0x2e*4		/*reserved addressing fault	*/
	.set	PROTVEC,0x2f*4		/*access control violation	*/
	.set	TRANS,0x30		/*translation fault vector	*/
	.set	TRANSVEC,0x30*4		/*translation fault vector	*/
	.set	KSPVEC,0x31*4		/*kernel stack not valid vector	*/
	.set	TRACEVEC,0x32*4		/*trace vector			*/
	.set	BPTVEC,0x33*4		/*break point fault		*/
	.set	ARITHVEC,0x34*4		/*arithmetic trap		*/
	.set	ALIGNVEC,0x35*4		/*alignment vector		*/	
	.set	FPMVEC,0x37*4		/*fpp emulation vector          */
	.set	IO14VEC,256		/*io vector, ipl #14		*/
	.set	IO15VEC,320		/*io vector, ipl #15		*/
	.set	IO16VEC,384		/*io vector, ipl #16		*/
	.set	IO17VEC,448		/*io vector, ipl #17		*/

#*	SPT (system page table) offsets					*/
#*	SPT is at Sysmap						*/

	.set	SCBPTE,8		/*system control block pte offset*/
	.set	BUFPTE,12		/*buffer pte offset		*/
	.set	ISPTE,16		/*interrupt stack page 0	*/
	.set	IS1PTE,20		/*interrupt stack page 1	*/
	.set	SPTPTE,20		/*system page table page 1	*/
	.set	SPT1PTE,20		/*system page table page 2	*/
	.set	IOMAPPTE,24		/*io map			*/
	.set	PCBPTE,28		/*process control blocks pte	*/
	.set	U0P0PTE,32		/*U0 p0pt pte			*/
	.set	U0P1PTE,36		/*U0 p1pt pte			*/
	.set	U0P2PTE,40		/*U0 p2pt pte			*/
	.set	U1P0PTE,44
	.set	U1P1PTE,48
	.set	U1P2PTE,52
	.set	U2P0PTE,56
	.set	U2P1PTE,60
	.set	U2P2PTE,64
	.set	U3P0PTE,68
	.set	U3P1PTE,72
	.set	U3P2PTE,76
	.set	U4P0PTE,80
	.set	U4P1PTE,84
	.set	U4P2PTE,88
	.set	U5P0PTE,92
	.set	U5P1PTE,96
	.set	U5P2PTE,100
	.set	U6P0PTE,104
	.set	U6P1PTE,108
	.set	U6P2PTE,112
	.set	U7P0PTE,116		/*U7 p0pt pte			*/
	.set	U7P1PTE,120		/*U7 p1pt pte			*/
	.set	U7P2PTE,124		/*U7 p2pt pte			*/
	.set	IOB0PTE,128		/*io buffer 0 pte		*/
	.set	IOB1PTE,132
	.set	IOB2PTE,136
	.set	IOB3PTE,140
	.set	IOB4PTE,144
	.set	IOB5PTE,148
	.set	IOB6PTE,152
	.set	IOB7PTE,156		/*io buffer 7 pte		*/


#*	trap.h	4.6	81/03/03	*/

#*
#* Trap type values
#/

	.set  	RESADFLT,0		/* reserved addressing fault */
	.set  	PRIVINFLT,1		/* privileged instruction fault */
	.set  	RESOPFLT,2		/* reserved operand fault */
	.set  	BPTFLT,3		/* bpt instruction fault */
	.set  	ALIGNFLT,4		/* alignment fault */
	.set  	SYSCALL,5		/* kcall instruction (syscall trap) */
	.set  	ARITHTRAP,6		/* arithmetic trap */
	.set  	PROTFLT,7		/* protection fault */
	.set  	TRCTRAP,8		/* trace trap */
	.set  	TRANSFLT,9		/* translation not valid fault */
	.set	DONE,255

#
#  Event codes
#
	.set	RTCLOCK_CODE,7		/* real time clock event */
	.set	RESOP_CODE,0x2d		/* reserved operand fault */
	.set	RESAD_CODE,0x2e		/* reserved address fault */
	.set	ARITH_CODE,0x34		/* arithmetic fault       */
	.set	FPM_CODE,0x37		/* fpp emulation trap     */
	.set	INTEGER_OVERFLOW,1	/* code for arith. fault  */

#
#  Arithmetic Event types
#
	.set	INT_OVFL_CODE,1		/* integer overflow     */
	.set	INT_0_DIV_CODE,2	/* integer divide by 0  */
	.set	FLT_0_DIV_CODE,3	/* floating divide by 0 */
	.set	FLT_OVFL_CODE,4		/* floating overflow    */
	.set	FLT_UNDFL_CODE,5	/* floating underflow   */

#
#  Floating Point Instruction Op-Codes
#
	.set  LDF_OP_CODE,0x06		/* sgl load acc. instr      */
	.set  LDD_OP_CODE,0x07		/* dbl load acc. instr      */
	.set  LNF_OP_CODE,0x16		/* sgl load-neg acc. instr  */
	.set  LND_OP_CODE,0x17		/* dbl load-neg acc. instr  */
	.set  STF_OP_CODE,0x26		/* sgl store acc. instr     */
	.set  STD_OP_CODE,0x27		/* dbl store acc. instr     */
	.set  CMPF_OP_CODE,0x36		/* sgl compare instr        */
	.set  CMPD_OP_CODE,0x37		/* dbl compare instr        */
	.set  CMPF2_OP_CODE,0x46	/* sgl compare 2 instr      */
	.set  CMPD2_OP_CODE,0x47	/* dbl compare 2 instr      */
	.set  TSTF_OP_CODE,0x56		/* sgl test acc. instr      */
	.set  TSTD_OP_CODE,0x57		/* dbl test acc. instr      */
	.set  PUSHD_OP_CODE,0x67	/* dbl push acc. instr      */
	.set  CVLF_OP_CODE,0x76		/* convert int to sgl instr */
	.set  CVLD_OP_CODE,0x77		/* convert int to dbl instr */
	.set  CVFL_OP_CODE,0x86		/* convert sgl to int instr */
	.set  CVDL_OP_CODE,0x87		/* convert dbl to int instr */
	.set  LDFD_OP_CODE,0x97		/* load sgl to dbl instr    */
	.set  CVDF_OP_CODE,0xa6		/* convert dbl to sgl instr */
	.set  NEGF_OP_CODE,0xb6		/* negate sgl acc. instr    */
	.set  NEGD_OP_CODE,0xb7		/* negate dbl acc. instr    */
	.set  ADDF_OP_CODE,0xc6		/* sgl add instr            */
	.set  ADDD_OP_CODE,0xc7		/* dbl add instr            */
	.set  SUBF_OP_CODE,0xd6		/* sgl subtract instr       */
	.set  SUBD_OP_CODE,0xd7		/* dbl subtract instr       */
	.set  MULF_OP_CODE,0xe6		/* sgl multiply instr       */
	.set  MULD_OP_CODE,0xe7		/* dbl multiply instr       */
	.set  DIVF_OP_CODE,0xf6		/* sgl divide instr         */
	.set  DIVD_OP_CODE,0xf7		/* dbl divide instr         */
	.set  SINF_OP_CODE,0x05		/* sgl sine instr           */
	.set  COSF_OP_CODE,0x15		/* sgl cosine instr         */
	.set  ATANF_OP_CODE,0x25	/* sgl arc-tangent instr    */
	.set  LOGF_OP_CODE,0x35		/* sgl natural log instr    */
	.set  SQRTF_OP_CODE,0x45	/* sgl square root instr    */
	.set  EXPF_OP_CODE,0x55		/* sgl "e to the x" instr   */
	.set  MULL2_OP_CODE,0x4c	/* integer multiply - 2 ops */
	.set  MULL3_OP_CODE,0x5c	/* integer multiply - 3 ops */


#
#  Addressing test constants - These must agree with "fpp_defs.h"
#
	.set ADR_ABSOLUTE,1	/* absolute address                 */
	.set ADR_LITERAL,2	/* literal -short immediate byte    */
	.set ADR_IM_B,3		/* immediate byte                   */
	.set ADR_IM_W,4		/* immediate word                   */
	.set ADR_IM_L,5		/* immediate long-word              */
	.set ADR_B_DSP,6	/* byte displ relative              */
	.set ADR_W_DSP,7	/* word displ relative              */
	.set ADR_L_DSP,8	/* long-word displ relative         */
	.set ADR_B_DSP_DEF,9	/* byte displ relative deferred     */
	.set ADR_W_DSP_DEF,10	/* word displ relative deferred     */
	.set ADR_L_DSP_DEF,11	/* L-word displ relative deferred   */
	.set ADR_REG,12		/* direct register                  */
	.set ADR_REG_DEF,13	/* register deferred                */
	.set ADR_FP_DEF,14	/* FP deferred                      */
	.set ADR_SP_DEF,15	/* SP deferred                      */
	.set ADR_PUSH,16	/* auto-decrement SP                */
	.set ADR_POP,17		/* auto-increment SP                */
	.set ADR_POP_DEF,18	/* auto-increment SP deferred       */
	.set ADR_REG_B,19	/* register + byte displ            */
	.set ADR_REG_W,20	/* register + word displ            */
	.set ADR_REG_L,21	/* register + long-word displ       */
	.set ADR_REG_B_DEF,22	/* register + byte displ deferred   */
	.set ADR_REG_W_DEF,23	/* register + word displ deferred   */
	.set ADR_REG_L_DEF,24	/* register + L-word displ deferred */
	.set ADR_I_FP_DEF,25	/* indexed (frame pointer deferred) */
	.set ADR_I_L,26		/* indexed (longword displacement)  */


#*************************************************************************
#
#	Stuff for the Demand Paging , Events, & Addressing Tests
#
#************************************************************************/
	.set SGL,1			/* sgl precision data           */
	.set DBL,2			/* dbl precision data           */
	.set ENABLE_EVENTS,0x60		/* enable ovfl & undfl events   */
	.set NONE,0			/* no operand flag              */
	.set LOAD,1			/* read-the-operand flag        */
	.set STORE,2			/* store-the-operand flag       */

	.set NO_EVT_HLT,1		/* halt code: did not Get event  */
	.set EVT_MSK_HLT,2		/* halt code: got masked event   */
	.set BAD_PSL_HLT,3		/* halt code: wrong PSL value    */
	.set PUSH_CNT_HLT,4		/* halt code: wrong # ops on stk */
	.set PUSH_PSL_HLT,5		/* halt code: bad PSL on stack   */
	.set PUSH_PC_HLT,6		/* halt code: bad PC on stack    */
	.set BAD_REG_HLT,7		/* halt code: bad final register */
	.set BAD_ACC_HLT,8		/* halt code: bad final Acc.     */

#
# set DMP_PG_0 to the 1st empty page
#
	.set DMP_PG_0,0x36000
	.set DMP_PG_1,DMP_PG_0+0x400
	.set DMP_PG_2,DMP_PG_1+0x400
	.set DMP_PG_3,DMP_PG_2+0x400
	.set DMP_PG_4,DMP_PG_3+0x400
	.set DMP_PG_5,DMP_PG_4+0x400
	.set DMP_PG_6,DMP_PG_5+0x400
	.set DMP_PG_7,DMP_PG_6+0x400
	.set DMP_PG_8,DMP_PG_7+0x400
	.set DMP_PG_9,DMP_PG_8+0x400
	.set DMP_PG_10,DMP_PG_9+0x400
	.set DMP_PG_11,DMP_PG_10+0x400
	.set DMP_PG_12,DMP_PG_11+0x400
	.set DMP_PG_13,DMP_PG_12+0x400

#
# test code space for the address / demand page tests
#
	.set START_OF_CODE,DMP_PG_1-20	/* 1st addr of test-code space  */
	.set CODE_BUF_SIZE,40		/* # bytes in test-code space   */
	.set END_OF_CODE,START_OF_CODE+CODE_BUF_SIZE

#
# data locations used by the event and demand page tests
#
	.set _dmp_byte_op_1,DMP_PG_1+0x30	/* 'byte offset' data */
	.set _dmp_byte_op_2,DMP_PG_1+0x50	/* 'byte offset' data */
	.set _dmp_byte_op_3,DMP_PG_1+0x70	/* 'byte offset' data */
	.set _dmp_op_1,DMP_PG_3-4		/* 1st data word      */
	.set _dmp_op_1_ptr,DMP_PG_4+0x30	/* ptr to 1st data wd */
	.set _dmp_op_2_ptr,DMP_PG_5+0x30	/* ptr to 2nd data wd */
	.set _dmp_op_2,DMP_PG_7-4		/* 2nd data word      */
	.set _dmp_op_3,DMP_PG_8			/* 3rd data word      */
	.set _dmp_op_3_ptr,DMP_PG_9+0x30	/* ptr to 3rd data wd */
	.set _dmp_op_4,DMP_PG_10		/* 4th data (for pipes) */
	.set _dmp_op_5,DMP_PG_11		/* 5th data (for pipes) */
	.set _sp_minus,DMP_PG_13-4		/* SP for POPs        */
	.set _sp_page,DMP_PG_13			/* SP page boundary   */
	.set _sp_plus,DMP_PG_13+4		/* SP for PUSHs       */

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