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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / fpevent|
Return to chk_event.lst CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / fpevent |
Power 6/32 Unix version 1.21
1 00000000 LL0:
2 00000000 .data
3 00000874 * .text
4 00000000 .align 1
5 00000000 .globl _chk_event
6 00000000 _chk_event:
7 0000D0AC 0000 .word L382
8 0000D0AE # #include "evt_defs.h"
9 0000D0AE #
10 0000D0AE # /*
11 0000D0AE # ********************************************************************
12 0000D0AE # *
13 0000D0AE # * Check the Results of a Floating Point Event
14 0000D0AE # *
15 0000D0AE # * This code will verify the following:
16 0000D0AE # * - the PSL saved after the event
17 0000D0AE # * - the # of operands pushed during the event.
18 0000D0AE # * - the PSL pushed on the stack
19 0000D0AE # * - the register values
20 0000D0AE # * - the final accumulator value
21 0000D0AE # *
22 0000D0AE # * If it was an FPP Emulation (FPM) Trap then this code will verify
23 0000D0AE # * - the data pushed onto the stack by the trap
24 0000D0AE # * - the PSL saved after the event
25 0000D0AE # * - the register values
26 0000D0AE # * - the final accumulator value
27 0000D0AE # *
28 0000D0AE # * 17-Jul-85 : added the FPM checks
29 0000D0AE # * 26-Jul-85 : don't check stack's PSL w/ no-fpp. The no-fpp firmware may
30 0000D0AE # * update the PSL before pushing it.
31 0000D0AE # ********************************************************************
32 0000D0AE # */
33 0000D0AE # chk_event()
34 0000D0AE # {
35 0000D0AE 13 0091 jbr L384
36 0000D0B1 L385:
37 0000D0B1 # error = FALSE;
38 0000D0B1 4d effffffff5 clrl _error
39 0000D0B7 # if( test_event == FPM_CODE ) { /* FPP EMULATION TRAP */
40 0000D0B7 1d efffffffef 37 cmpl _test_event,$55
41 0000D0BE 21 36 jneq L386
42 0000D0C0 # chk_fpm_trap(); /* check FPM trap data */
43 0000D0C0 fe 04 ef00000667 callf $4,_chk_fpm_trap
44 0000D0C7 # if( !error )
45 0000D0C7 5d efffffffdf tstl _error
46 0000D0CD 21 07 jneq L388
47 0000D0CF # chk_final_acc(); /* check final Acc value */
48 0000D0CF fe 04 ef000004bc callf $4,_chk_final_acc
49 0000D0D6 # if( !error )
50 0000D0D6 L388:
51 0000D0D6 5d efffffffd0 tstl _error
52 0000D0DC 21 07 jneq L390
53 0000D0DE # chk_final_psl(); /* check final PSL value */
54 0000D0DE fe 04 ef00000061 callf $4,_chk_final_psl
55 0000D0E5 # if( !error )
56 0000D0E5 L390:
57 0000D0E5 5d efffffffc1 tstl _error
58 0000D0EB 21 07 jneq L392
59 0000D0ED # chk_registers(); /* check final REG values */
60 0000D0ED fe 04 ef0000031c callf $4,_chk_registers
61 0000D0F4 # } else { /* other event type */
62 0000D0F4 L392:
63 0000D0F4 11 4b jbr L394
64 0000D0F6 L386:
65 0000D0F6 # chk_final_psl(); /* check final PSL value */
66 0000D0F6 fe 04 ef00000049 callf $4,_chk_final_psl
67 0000D0FD # if( !error )
68 0000D0FD 5d efffffffa9 tstl _error
69 0000D103 21 07 jneq L395
70 0000D105 # chk_push_cnt(); /* check # ops pushed */
71 0000D105 fe 04 ef00000120 callf $4,_chk_push_cnt
72 0000D10C # if( (!error) && (!no_fpp_wcs) )
73 0000D10C L395:
74 0000D10C 5d efffffff9a tstl _error
75 0000D112 21 0f jneq L397
76 0000D114 5d efffffff92 tstl _no_fpp_wcs
77 0000D11A 21 07 jneq L397
78 0000D11C # chk_stack_psl(); /* check PSL on the stack */
79 0000D11C fe 04 ef00000233 callf $4,_chk_stack_psl
80 0000D123 # if( !error )
81 0000D123 L397:
82 0000D123 5d efffffff83 tstl _error
83 0000D129 21 07 jneq L399
84 0000D12B # chk_registers(); /* check final REG values */
85 0000D12B fe 04 ef000002de callf $4,_chk_registers
86 0000D132 # if( !error )
87 0000D132 L399:
88 0000D132 5d efffffff74 tstl _error
89 0000D138 21 07 jneq L400
90 0000D13A # chk_final_acc(); /* check final Acc value */
91 0000D13A fe 04 ef00000451 callf $4,_chk_final_acc
92 0000D141 # }
93 0000D141 L400:
94 0000D141 L394:
95 0000D141 # }
96 0000D141 40 ret#2
97 0000D142 .set L382,0x0
98 0000D142 L384:
99 0000D142 13 ff6c jbr L385
100 0000D145 .data
101 00000874 * .text
102 0000D145 00 .align 1
103 0000D146 .globl _chk_final_psl
104 0000D146 _chk_final_psl:
105 0000D146 0000 .word L401
106 0000D148 #
107 0000D148 #
108 0000D148 #
109 0000D148 #
110 0000D148 #
111 0000D148 # /*
112 0000D148 # ***************************************************************************
113 0000D148 # *
114 0000D148 # * Check the final PSL value
115 0000D148 # *
116 0000D148 # ***************************************************************************
117 0000D148 # */
118 0000D148 # chk_final_psl()
119 0000D148 # {
120 0000D148 13 008b jbr L403
121 0000D14B L404:
122 0000D14B # if( bad_final_psl() ) {
123 0000D14B fe 04 ef00000088 callf $4,_bad_final_psl
124 0000D152 5d 50 tstl r0
125 0000D154 31 7f jeql L406
126 0000D156 # error = TRUE;
127 0000D156 0d 01 efffffff4f movl $1,_error
128 0000D15D # errcnt++;
129 0000D15D 6d efffffff49 incl _errcnt
130 0000D163 # if( prt_error ) {
131 0000D163 5d efffffff43 tstl _prt_error
132 0000D169 31 4a jeql L407
133 0000D16B # prt_evt_er_msg( bad_psl_msg );
134 0000D16B dd efffffff3b pushl _bad_psl_msg
135 0000D171 fe 08 efffffff34 callf $8,_prt_evt_er_msg
136 0000D178 # writes("final PSL = ");
137 0000D178 .data 1
138 00000874 * L410:
139 00000874 * 66696E616C2050534C203D200 .ascii "final PSL = \0"
0
140 00000881 * .text
141 0000D178 dd 8f00000874 pushl $L410
142 0000D17E fe 08 efffffff27 callf $8,_writes
143 0000D185 # write32h( psl_val );
144 0000D185 dd efffffff21 pushl _psl_val
145 0000D18B fe 08 efffffff1a callf $8,_write32h
146 0000D192 # writes(", expected PSL = ");
147 0000D192 .data 1
148 00000881 * L412:
149 00000881 * 2C20202065787065637465642 .ascii ", expected PSL = \0"
050534C203D2000
150 00000895 * .text
151 0000D192 dd 8f00000881 pushl $L412
152 0000D198 fe 08 efffffff0d callf $8,_writes
153 0000D19F # write32h( exp_psl );
154 0000D19F dd efffffff07 pushl _exp_psl
155 0000D1A5 fe 08 efffffff00 callf $8,_write32h
156 0000D1AC # writec('\n');
157 0000D1AC dd 0a pushl $10
158 0000D1AE fe 08 effffffef7 callf $8,_writec
159 0000D1B5 # }
160 0000D1B5 # if( halt_flg )
161 0000D1B5 L407:
162 0000D1B5 5d effffffef1 tstl _halt_flg
163 0000D1BB 31 09 jeql L414
164 0000D1BD # event_halt( BAD_PSL_HLT ); /* halt on the error */
165 0000D1BD dd 03 pushl $3
166 0000D1BF fe 08 effffffee6 callf $8,_event_halt
167 0000D1C6 # if( loop_on_err )
168 0000D1C6 L414:
169 0000D1C6 5d effffffee0 tstl _loop_on_err
170 0000D1CC 31 07 jeql L416
171 0000D1CE # force_loop = TRUE; /* set loop flag */
172 0000D1CE 0d 01 effffffed7 movl $1,_force_loop
173 0000D1D5 # }
174 0000D1D5 L416:
175 0000D1D5 # }
176 0000D1D5 L406:
177 0000D1D5 40 ret#2
178 0000D1D6 .set L401,0x0
179 0000D1D6 L403:
180 0000D1D6 13 ff72 jbr L404
181 0000D1D9 .data
182 00000874 * .text
183 0000D1D9 00 .align 1
184 0000D1DA .globl _bad_final_psl
185 0000D1DA _bad_final_psl:
186 0000D1DA 0000 .word L417
187 0000D1DC #
188 0000D1DC #
189 0000D1DC #
190 0000D1DC # /*
191 0000D1DC # ***************************************************************************
192 0000D1DC # *
193 0000D1DC # * Is the final PSL correct?
194 0000D1DC # *
195 0000D1DC # * 2-May-85 -stopped looking for 'V' set if the event was enabled.
196 0000D1DC # *
197 0000D1DC # ***************************************************************************
198 0000D1DC # */
199 0000D1DC # bad_final_psl()
200 0000D1DC # {
201 0000D1DC 11 4b jbr L419
202 0000D1DE L420:
203 0000D1DE # exp_psl = psl_val;
204 0000D1DE 0d effffffec8 effffffec3 movl _psl_val,_exp_psl
205 0000D1E9 # if( (test_event == ARITH_CODE) && /* the PSL overflow bit should */
206 0000D1E9 # (exp_code == INT_OVFL_CODE) && /* be set for int. overflow's */
207 0000D1E9 # ( evt_disabled ) ) /* when the event is disabled */
208 0000D1E9 1d effffffebd 34 cmpl _test_event,$52
209 0000D1F0 21 1a jneq L421
210 0000D1F2 1d effffffeb4 01 cmpl _exp_code,$1
211 0000D1F9 21 11 jneq L421
212 0000D1FB 5d effffffeab tstl _evt_disabled
213 0000D201 31 09 jeql L421
214 0000D203 # exp_psl |= PSL_V; /* expect the INTEGER OVERFLOW set */
215 0000D203 8c 02 effffffea2 orl2 $2,_exp_psl
216 0000D20A # else
217 0000D20A 11 08 jbr L422
218 0000D20C L421:
219 0000D20C # exp_psl &= ~PSL_V; /* expect INTEGER OVERFLOW reset */
220 0000D20C ac 88fd effffffe98 andl2 $-3,_exp_psl
221 0000D214 L422:
222 0000D214 # if( psl_val == exp_psl )
223 0000D214 1d effffffe92 effffffe8d cmpl _psl_val,_exp_psl
224 0000D21F 21 03 jneq L423
225 0000D221 # return( FALSE );
226 0000D221 4d 50 clrl r0
227 0000D223 40 ret#1
228 0000D224 # else
229 0000D224 L423:
230 0000D224 # return( TRUE );
231 0000D224 0d 01 50 movl $1,r0
232 0000D227 40 ret#1
233 0000D228 # }
234 0000D228 40 ret#1
235 0000D229 .set L417,0x0
236 0000D229 L419:
237 0000D229 11 b3 jbr L420
238 0000D22B .data
239 00000874 * .text
240 0000D22B 00 .align 1
241 0000D22C .globl _chk_push_cnt
242 0000D22C _chk_push_cnt:
243 0000D22C 0000 .word L424
244 0000D22E #
245 0000D22E #
246 0000D22E #
247 0000D22E #
248 0000D22E # /*
249 0000D22E # ***************************************************************************
250 0000D22E # *
251 0000D22E # * Check the # of operands pushed onto the stack
252 0000D22E # *
253 0000D22E # ***************************************************************************
254 0000D22E # */
255 0000D22E # chk_push_cnt()
256 0000D22E # {
257 0000D22E 13 0082 jbr L426
258 0000D231 L427:
259 0000D231 # if( bad_push_count() ) {
260 0000D231 fe 04 ef0000007e callf $4,_bad_push_count
261 0000D238 5d 50 tstl r0
262 0000D23A 31 76 jeql L429
263 0000D23C # error = TRUE;
264 0000D23C 0d 01 effffffe69 movl $1,_error
265 0000D243 # errcnt++;
266 0000D243 6d effffffe63 incl _errcnt
267 0000D249 # if( prt_error ) {
268 0000D249 5d effffffe5d tstl _prt_error
269 0000D24F 31 41 jeql L430
270 0000D251 # prt_evt_er_msg( push_cnt_msg );
271 0000D251 dd effffffe55 pushl _push_cnt_msg
272 0000D257 fe 08 effffffe4e callf $8,_prt_evt_er_msg
273 0000D25E # writed( push_cnt );
274 0000D25E dd effffffe48 pushl _push_cnt
275 0000D264 fe 08 effffffe41 callf $8,_writed
276 0000D26B # writes(" longwords pushed, ");
277 0000D26B .data 1
278 00000895 * L432:
279 00000895 * 206C6F6E67776F72647320707 .ascii " longwords pushed, \0"
5736865642C20202000
280 000008ab * .text
281 0000D26B dd 8f00000895 pushl $L432
282 0000D271 fe 08 effffffe34 callf $8,_writes
283 0000D278 # writed( exp_push_cnt );
284 0000D278 dd effffffe2e pushl _exp_push_cnt
285 0000D27E fe 08 effffffe27 callf $8,_writed
286 0000D285 # writes(" longwords expected\n");
287 0000D285 .data 1
288 000008ab * L433:
289 000008ab * 206C6F6E67776F72647320657 .ascii " longwords expected\12\0"
87065637465640A00
290 000008c0 * .text
291 0000D285 dd 8f000008ab pushl $L433
292 0000D28B fe 08 effffffe1a callf $8,_writes
293 0000D292 # }
294 0000D292 # if( halt_flg )
295 0000D292 L430:
296 0000D292 5d effffffe14 tstl _halt_flg
297 0000D298 31 09 jeql L434
298 0000D29A # event_halt( PUSH_CNT_HLT ); /* halt on the error */
299 0000D29A dd 08 pushl $8
300 0000D29C fe 08 effffffe09 callf $8,_event_halt
301 0000D2A3 # if( loop_on_err )
302 0000D2A3 L434:
303 0000D2A3 5d effffffe03 tstl _loop_on_err
304 0000D2A9 31 07 jeql L435
305 0000D2AB # force_loop = TRUE; /* set loop flag */
306 0000D2AB 0d 01 effffffdfa movl $1,_force_loop
307 0000D2B2 # }
308 0000D2B2 L435:
309 0000D2B2 # }
310 0000D2B2 L429:
311 0000D2B2 40 ret#2
312 0000D2B3 .set L424,0x0
313 0000D2B3 L426:
314 0000D2B3 13 ff7b jbr L427
315 0000D2B6 .data
316 00000874 * .text
317 0000D2B6 .align 1
318 0000D2B6 .globl _bad_push_count
319 0000D2B6 _bad_push_count:
320 0000D2B6 0000 .word L436
321 0000D2B8 #
322 0000D2B8 #
323 0000D2B8 #
324 0000D2B8 # /*
325 0000D2B8 # ***************************************************************************
326 0000D2B8 # *
327 0000D2B8 # * Were the right number of longwords pushed onto the stack?
328 0000D2B8 # *
329 0000D2B8 # * Get the number of longwords pushed by the change in stack pointer.
330 0000D2B8 # * The only special case is with CMPF2: If the addressing mode is POP
331 0000D2B8 # * and a Reserved Operand fault happens with the 2nd operand then the
332 0000D2B8 # * CMPF2 will pop 2 operands and then the fault will push 2.
333 0000D2B8 # ***************************************************************************
334 0000D2B8 # */
335 0000D2B8 # bad_push_count()
336 0000D2B8 # {
337 0000D2B8 13 0097 jbr L438
338 0000D2BB L439:
339 0000D2BB # push_cnt = (int) pre_event_sp - (int) post_event_sp;
340 0000D2BB 3c effffffdeb effffffde6 subl3 _post_event_sp,_pre_event_sp,r0
50
341 0000D2C7 0d 50 effffffdde movl r0,_push_cnt
342 0000D2CE # push_cnt /= 4; /* get # longwords pushed */
343 0000D2CE 6c 04 effffffdd7 divl2 $4,_push_cnt
344 0000D2D5 # if( test_event == ARITH_CODE )
345 0000D2D5 1d effffffdd1 34 cmpl _test_event,$52
346 0000D2DC 21 09 jneq L440
347 0000D2DE # exp_push_cnt = 3; /* ARITHMETIC faults push 3 longwords */
348 0000D2DE 0d 03 effffffdc7 movl $3,_exp_push_cnt
349 0000D2E5 # else if( test_event == RESOP_CODE ) {
350 0000D2E5 11 56 jbr L441
351 0000D2E7 L440:
352 0000D2E7 1d effffffdbf 2d cmpl _test_event,$45
353 0000D2EE 21 46 jneq L442
354 0000D2F0 # if( (op_code == CMPF2_OP_CODE) &&
355 0000D2F0 # ( (addr_code == 0x8e) || (addr_code == 0x9e) ) &&
356 0000D2F0 # ( (dbl_value_1.m & 0xff800000) != 0x80000000 ) )
357 0000D2F0 1d effffffdb6 8846 cmpl _op_code,$70
358 0000D2F8 21 33 jneq L443
359 0000D2FA 1d effffffdac 89008e cmpl _addr_code,$142
360 0000D303 31 0b jeql L9999
361 0000D305 1d effffffda1 89009e cmpl _addr_code,$158
362 0000D30E 21 1d jneq L443
363 0000D310 L9999:
364 0000D310 bc 8fff800000 effffffd91 andl3 $-8388608,_dbl_value_1,r0
50
365 0000D31C 1d 50 8f80000000 cmpl r0,$-2147483648
366 0000D323 31 08 jeql L443
367 0000D325 # exp_push_cnt = 0; /* special case with POPs */
368 0000D325 4d effffffd81 clrl _exp_push_cnt
369 0000D32B # else
370 0000D32B 11 07 jbr L444
371 0000D32D L443:
372 0000D32D # exp_push_cnt = 2; /* reserved ops push 2 longwords */
373 0000D32D 0d 02 effffffd78 movl $2,_exp_push_cnt
374 0000D334 L444:
375 0000D334 # } else
376 0000D334 11 07 jbr L445
377 0000D336 L442:
378 0000D336 # exp_push_cnt = 2;
379 0000D336 0d 02 effffffd6f movl $2,_exp_push_cnt
380 0000D33D L445:
381 0000D33D L441:
382 0000D33D # if( push_cnt != exp_push_cnt )
383 0000D33D 1d effffffd69 effffffd64 cmpl _push_cnt,_exp_push_cnt
384 0000D348 31 04 jeql L446
385 0000D34A # return( TRUE );
386 0000D34A 0d 01 50 movl $1,r0
387 0000D34D 40 ret#1
388 0000D34E # else
389 0000D34E L446:
390 0000D34E # return( FALSE );
391 0000D34E 4d 50 clrl r0
392 0000D350 40 ret#1
393 0000D351 # }
394 0000D351 40 ret#1
395 0000D352 .set L436,0x0
396 0000D352 L438:
397 0000D352 13 ff66 jbr L439
398 0000D355 .data
399 00000874 * .text
400 0000D355 00 .align 1
401 0000D356 .globl _chk_stack_psl
402 0000D356 _chk_stack_psl:
403 0000D356 0000 .word L447
404 0000D358 #
405 0000D358 #
406 0000D358 #
407 0000D358 #
408 0000D358 # /*
409 0000D358 # ***************************************************************************
410 0000D358 # *
411 0000D358 # * Check the PSL pushed onto the stack
412 0000D358 # *
413 0000D358 # * 22-Jul-85 : don't worry about the N or Z bits in the PSL. The interrupt
414 0000D358 # * handler can store a Zero and update the status.
415 0000D358 # * 23-Jul-85 : don't expect the DBL bit set after a CVDF instruction.
416 0000D358 # ***************************************************************************
417 0000D358 # */
418 0000D358 # chk_stack_psl()
419 0000D358 # {
420 0000D358 13 00ae jbr L449
421 0000D35B L450:
422 0000D35B # int mask;
423 0000D35B # if( op_code == CVDF_OP_CODE )
424 0000D35B 1d effffffd4b 8900a6 cmpl _op_code,$166
425 0000D364 21 08 jneq L451
426 0000D366 # mask = 0xffffff73; /* don't look at the DBL bit */
427 0000D366 0d 89ff73 adc8 movl $-141,-56(fp)
428 0000D36C # else
429 0000D36C 11 04 jbr L452
430 0000D36E L451:
431 0000D36E # mask = 0xfffffff3; /* look at the DBL bit */
432 0000D36E ec 0d adc8 mnegl $13,-56(fp)
433 0000D372 L452:
434 0000D372 # if( (event_psl & mask) != (init_psl & mask) ) {
435 0000D372 bc adc8 effffffd32 50 andl3 -56(fp),_event_psl,r0
436 0000D37B bc adc8 effffffd29 51 andl3 -56(fp),_init_psl,r1
437 0000D384 1d 50 51 cmpl r0,r1
438 0000D387 31 7f jeql L453
439 0000D389 # error = TRUE;
440 0000D389 0d 01 effffffd1c movl $1,_error
441 0000D390 # errcnt++;
442 0000D390 6d effffffd16 incl _errcnt
443 0000D396 # if( prt_error ) {
444 0000D396 5d effffffd10 tstl _prt_error
445 0000D39C 31 4a jeql L454
446 0000D39E # prt_evt_er_msg( psl_pushed_msg );
447 0000D39E dd effffffd08 pushl _psl_pushed_msg
448 0000D3A4 fe 08 effffffd01 callf $8,_prt_evt_er_msg
449 0000D3AB # writes("PSL on stack = ");
450 0000D3AB .data 1
451 000008c0 * L455:
452 000008c0 * 50534C206F6E20737461636B2 .ascii "PSL on stack = \0"
03D2000
453 000008d0 * .text
454 0000D3AB dd 8f000008c0 pushl $L455
455 0000D3B1 fe 08 effffffcf4 callf $8,_writes
456 0000D3B8 # write32h( event_psl );
457 0000D3B8 dd effffffcee pushl _event_psl
458 0000D3BE fe 08 effffffce7 callf $8,_write32h
459 0000D3C5 # writes(", expected = ");
460 0000D3C5 .data 1
461 000008d0 * L456:
462 000008d0 * 2C20206578706563746564203 .ascii ", expected = \0"
D2000
463 000008df * .text
464 0000D3C5 dd 8f000008d0 pushl $L456
465 0000D3CB fe 08 effffffcda callf $8,_writes
466 0000D3D2 # write32h( init_psl );
467 0000D3D2 dd effffffcd4 pushl _init_psl
468 0000D3D8 fe 08 effffffccd callf $8,_write32h
469 0000D3DF # writec('\n');
470 0000D3DF dd 0a pushl $10
471 0000D3E1 fe 08 effffffcc4 callf $8,_writec
472 0000D3E8 # }
473 0000D3E8 # if( halt_flg )
474 0000D3E8 L454:
475 0000D3E8 5d effffffcbe tstl _halt_flg
476 0000D3EE 31 09 jeql L457
477 0000D3F0 # event_halt( PUSH_PSL_HLT ); /* halt on the error */
478 0000D3F0 dd 06 pushl $6
479 0000D3F2 fe 08 effffffcb3 callf $8,_event_halt
480 0000D3F9 # if( loop_on_err )
481 0000D3F9 L457:
482 0000D3F9 5d effffffcad tstl _loop_on_err
483 0000D3FF 31 07 jeql L458
484 0000D401 # force_loop = TRUE; /* set loop flag */
485 0000D401 0d 01 effffffca4 movl $1,_force_loop
486 0000D408 # }
487 0000D408 L458:
488 0000D408 # }
489 0000D408 L453:
490 0000D408 40 ret#2
491 0000D409 .set L447,0x0
492 0000D409 L449:
493 0000D409 3c 38 5d 5e subl3 $56,fp,sp
494 0000D40D 13 ff4b jbr L450
495 0000D410 .data
496 00000874 * .text
497 0000D410 .align 1
498 0000D410 .globl _chk_registers
499 0000D410 _chk_registers:
500 0000D410 0000 .word L459
501 0000D412 #
502 0000D412 #
503 0000D412 #
504 0000D412 # /*
505 0000D412 # ***************************************************************************
506 0000D412 # *
507 0000D412 # * Check the final register values
508 0000D412 # *
509 0000D412 # * 23-Jul-85 : If we are running MULL2 or MULL3 with register addressing
510 0000D412 # * then don't check the final operand's register.
511 0000D412 # ***************************************************************************
512 0000D412 # */
513 0000D412 # chk_registers()
514 0000D412 # {
515 0000D412 13 017a jbr L461
516 0000D415 L462:
517 0000D415 # if( (op_code == MULL2_OP_CODE) && (addr_mode == ADR_REG) ) {
518 0000D415 1d effffffc91 884c cmpl _op_code,$76
519 0000D41D 21 33 jneq L463
520 0000D41F 1d effffffc87 0c cmpl _addr_mode,$12
521 0000D426 21 2a jneq L463
522 0000D428 # reg_no = addr_code2 & 0xf; /* get operand 2's reg # */
523 0000D428 bc 0f effffffc7d 50 andl3 $15,_addr_code2,r0
524 0000D430 0d 50 effffffc75 movl r0,_reg_no
525 0000D437 # exp_regs[reg_no] = store_regs[reg_no];
526 0000D437 0d effffffc6f 50 movl _reg_no,r0
527 0000D43E 0d effffffc68 51 movl _reg_no,r1
528 0000D445 0d 40effffffc60 movl _store_regs[r0],_exp_regs[r1]
41effffffc5a
529 0000D452 # }
530 0000D452 # if( (op_code == MULL3_OP_CODE) && (addr_mode == ADR_REG) ) {
531 0000D452 L463:
532 0000D452 1d effffffc54 885c cmpl _op_code,$92
533 0000D45A 21 33 jneq L464
534 0000D45C 1d effffffc4a 0c cmpl _addr_mode,$12
535 0000D463 21 2a jneq L464
536 0000D465 # reg_no = addr_code3 & 0xf; /* get operand 3's reg # */
537 0000D465 bc 0f effffffc40 50 andl3 $15,_addr_code3,r0
538 0000D46D 0d 50 effffffc38 movl r0,_reg_no
539 0000D474 # exp_regs[reg_no] = store_regs[reg_no];
540 0000D474 0d effffffc32 50 movl _reg_no,r0
541 0000D47B 0d effffffc2b 51 movl _reg_no,r1
542 0000D482 0d 40effffffc23 movl _store_regs[r0],_exp_regs[r1]
41effffffc1d
543 0000D48F # }
544 0000D48F # reg_no = 0; /* check regs 0 - 12 */
545 0000D48F L464:
546 0000D48F 4d effffffc17 clrl _reg_no
547 0000D495 # regs_ok = TRUE;
548 0000D495 0d 01 effffffc10 movl $1,_regs_ok
549 0000D49C # while( (reg_no < 13) && (regs_ok) )
550 0000D49C L465:
551 0000D49C 1d effffffc0a 0d cmpl _reg_no,$13
552 0000D4A3 81 35 jgeq L466
553 0000D4A5 5d effffffc01 tstl _regs_ok
554 0000D4AB 31 2d jeql L466
555 0000D4AD # if( store_regs[reg_no] == exp_regs[reg_no] )
556 0000D4AD 0d effffffbf9 50 movl _reg_no,r0
557 0000D4B4 0d effffffbf2 51 movl _reg_no,r1
558 0000D4BB 1d 40effffffbea cmpl _store_regs[r0],_exp_regs[r1]
41effffffbe4
559 0000D4C8 21 08 jneq L467
560 0000D4CA # reg_no++;
561 0000D4CA 6d effffffbdc incl _reg_no
562 0000D4D0 # else
563 0000D4D0 11 06 jbr L468
564 0000D4D2 L467:
565 0000D4D2 # regs_ok = FALSE;
566 0000D4D2 4d effffffbd4 clrl _regs_ok
567 0000D4D8 L468:
568 0000D4D8 11 c2 jbr L465
569 0000D4DA L466:
570 0000D4DA # if( !regs_ok ) {
571 0000D4DA 5d effffffbcc tstl _regs_ok
572 0000D4E0 31 03 13 00a9 jneq L469
573 0000D4E5 # error = TRUE;
574 0000D4E5 0d 01 effffffbc0 movl $1,_error
575 0000D4EC # errcnt++;
576 0000D4EC 6d effffffbba incl _errcnt
577 0000D4F2 # if( prt_error ) {
578 0000D4F2 5d effffffbb4 tstl _prt_error
579 0000D4F8 31 74 jeql L470
580 0000D4FA # prt_evt_er_msg( reg_modified_msg );
581 0000D4FA dd effffffbac pushl _reg_modified_msg
582 0000D500 fe 08 effffffba5 callf $8,_prt_evt_er_msg
583 0000D507 # writes("Register ");
584 0000D507 .data 1
585 000008df * L471:
586 000008df * 52656769737465722000 .ascii "Register \0"
587 000008e9 * .text
588 0000D507 dd 8f000008df pushl $L471
589 0000D50D fe 08 effffffb98 callf $8,_writes
590 0000D514 # writeh( reg_no );
591 0000D514 dd effffffb92 pushl _reg_no
592 0000D51A fe 08 effffffb8b callf $8,_writeh
593 0000D521 # writes(" = ");
594 0000D521 .data 1
595 000008e9 * L473:
596 000008e9 * 203D2000 .ascii " = \0"
597 000008ed * .text
598 0000D521 dd 8f000008e9 pushl $L473
599 0000D527 fe 08 effffffb7e callf $8,_writes
600 0000D52E # write32h( store_regs[reg_no] );
601 0000D52E 0d effffffb78 50 movl _reg_no,r0
602 0000D535 dd 40effffffb70 pushl _store_regs[r0]
603 0000D53C fe 08 effffffb69 callf $8,_write32h
604 0000D543 # writes(", expected = ");
605 0000D543 .data 1
606 000008ed * L474:
607 000008ed * 2C20206578706563746564203 .ascii ", expected = \0"
D2000
608 000008fc * .text
609 0000D543 dd 8f000008ed pushl $L474
610 0000D549 fe 08 effffffb5c callf $8,_writes
611 0000D550 # write32h( exp_regs[reg_no] );
612 0000D550 0d effffffb56 50 movl _reg_no,r0
613 0000D557 dd 40effffffb4e pushl _exp_regs[r0]
614 0000D55E fe 08 effffffb47 callf $8,_write32h
615 0000D565 # writec('\n');
616 0000D565 dd 0a pushl $10
617 0000D567 fe 08 effffffb3e callf $8,_writec
618 0000D56E # }
619 0000D56E # if( halt_flg )
620 0000D56E L470:
621 0000D56E 5d effffffb38 tstl _halt_flg
622 0000D574 31 09 jeql L475
623 0000D576 # event_halt( BAD_REG_HLT ); /* halt on the error */
624 0000D576 dd 02 pushl $2
625 0000D578 fe 08 effffffb2d callf $8,_event_halt
626 0000D57F # if( loop_on_err )
627 0000D57F L475:
628 0000D57F 5d effffffb27 tstl _loop_on_err
629 0000D585 31 07 jeql L476
630 0000D587 # force_loop = TRUE; /* set loop flag */
631 0000D587 0d 01 effffffb1e movl $1,_force_loop
632 0000D58E # }
633 0000D58E L476:
634 0000D58E # }
635 0000D58E L469:
636 0000D58E 40 ret#2
637 0000D58F .set L459,0x0
638 0000D58F L461:
639 0000D58F 13 fe83 jbr L462
640 0000D592 .data
641 00000874 * .text
642 0000D592 .align 1
643 0000D592 .globl _chk_final_acc
644 0000D592 _chk_final_acc:
645 0000D592 0000 .word L477
646 0000D594 #
647 0000D594 #
648 0000D594 #
649 0000D594 #
650 0000D594 # /*
651 0000D594 # ***************************************************************************
652 0000D594 # *
653 0000D594 # * Check the final Accumulator value
654 0000D594 # *
655 0000D594 # ***************************************************************************
656 0000D594 # */
657 0000D594 # chk_final_acc()
658 0000D594 # {
659 0000D594 13 00a7 jbr L479
660 0000D597 L480:
661 0000D597 # if( acc_trashed() ) {
662 0000D597 fe 04 ef000000a4 callf $4,_acc_trashed
663 0000D59E 5d 50 tstl r0
664 0000D5A0 21 03 13 0098 jeql L482
665 0000D5A5 # error = TRUE;
666 0000D5A5 0d 01 effffffb00 movl $1,_error
667 0000D5AC # errcnt++;
668 0000D5AC 6d effffffafa incl _errcnt
669 0000D5B2 # if( prt_error ) {
670 0000D5B2 5d effffffaf4 tstl _prt_error
671 0000D5B8 31 4f jeql L483
672 0000D5BA # prt_evt_er_msg( bad_acc_msg );
673 0000D5BA dd effffffaec pushl _bad_acc_msg
674 0000D5C0 fe 08 effffffae5 callf $8,_prt_evt_er_msg
675 0000D5C7 # writes(" expected = ");
676 0000D5C7 .data 1
677 000008fc * L484:
678 000008fc * 2020202065787065637465642 .ascii " expected = \0"
03D2000
679 0000090c * .text
680 0000D5C7 dd 8f000008fc pushl $L484
681 0000D5CD fe 08 effffffad8 callf $8,_writes
682 0000D5D4 # write32h( dbl_expected.m );
683 0000D5D4 dd effffffad2 pushl _dbl_expected
684 0000D5DA fe 08 effffffacb callf $8,_write32h
685 0000D5E1 # if( precision == DBL ) {
686 0000D5E1 1d effffffac5 02 cmpl _precision,$2
687 0000D5E8 21 16 jneq L485
688 0000D5EA # writec(' ');
689 0000D5EA dd 20 pushl $32
690 0000D5EC fe 08 effffffab9 callf $8,_writec
691 0000D5F3 # write32h( dbl_expected.l );
692 0000D5F3 dd effffffab7 pushl _dbl_expected+4
693 0000D5F9 fe 08 effffffaac callf $8,_write32h
694 0000D600 # }
695 0000D600 # writec('\n');
696 0000D600 L485:
697 0000D600 dd 0a pushl $10
698 0000D602 fe 08 effffffaa3 callf $8,_writec
699 0000D609 # }
700 0000D609 # if( halt_flg ) {
701 0000D609 L483:
702 0000D609 5d effffffa9d tstl _halt_flg
703 0000D60F 31 1d jeql L486
704 0000D611 # if( test_event == FPM_CODE )
705 0000D611 1d effffffa95 37 cmpl _test_event,$55
706 0000D618 21 0b jneq L487
707 0000D61A # fpm_halt( BAD_ACC_HLT ); /* use the FPM halt */
708 0000D61A dd 01 pushl $1
709 0000D61C fe 08 effffffa89 callf $8,_fpm_halt
710 0000D623 # else
711 0000D623 11 09 jbr L489
712 0000D625 L487:
713 0000D625 # event_halt( BAD_ACC_HLT ); /* use normal halt */
714 0000D625 dd 01 pushl $1
715 0000D627 fe 08 effffffa7e callf $8,_event_halt
716 0000D62E L489:
717 0000D62E # }
718 0000D62E # if( loop_on_err )
719 0000D62E L486:
720 0000D62E 5d effffffa78 tstl _loop_on_err
721 0000D634 31 07 jeql L490
722 0000D636 # force_loop = TRUE; /* set loop flag */
723 0000D636 0d 01 effffffa6f movl $1,_force_loop
724 0000D63D # }
725 0000D63D L490:
726 0000D63D # }
727 0000D63D L482:
728 0000D63D 40 ret#2
729 0000D63E .set L477,0x0
730 0000D63E L479:
731 0000D63E 13 ff56 jbr L480
732 0000D641 .data
733 00000874 * .text
734 0000D641 00 .align 1
735 0000D642 .globl _acc_trashed
736 0000D642 _acc_trashed:
737 0000D642 0000 .word L491
738 0000D644 #
739 0000D644 #
740 0000D644 #
741 0000D644 # /*
742 0000D644 # ***************************************************************************
743 0000D644 # *
744 0000D644 # * Check to see if the accumulator has the correct value in it
745 0000D644 # *
746 0000D644 # * The final accumulator should either be the original value loaded or '0'.
747 0000D644 # *
748 0000D644 # * Bad 0's are numbers with a exponent of zero and a non-zero fraction. These
749 0000D644 # * are any hex number between 00000001 and 007fffff. Bad 0's are changed to
750 0000D644 # * good 0's by the store instruction unless we are using the "no-fpp" WCS
751 0000D644 # * and the most significant longword of a double precision accumulator isn't
752 0000D644 # * all 0's. If the most significant longword of the accumulator is '0' then
753 0000D644 # * the least significant longword will get cleared anyway. (I didn't write
754 0000D644 # * the micro-code folks - I just test it).
755 0000D644 # *
756 0000D644 # * The accumulator will be cleared to '0' by the firmware if there is
757 0000D644 # * a floating Underflow fault, if there is a floating Overflow fault, or
758 0000D644 # * if there is a floating Reserved Operand fault (except for the compare
759 0000D644 # * instructions -CMPF, CMPF2, CMPD, CMPD2). If we are using the "no-fpp" WCS
760 0000D644 # * then the accumulator will not be changed for any Reserved Operands.
761 0000D644 # *
762 0000D644 # * The accumulator should not be changed by either the Integer Overflow or
763 0000D644 # * the Divide By Zero faults.
764 0000D644 # *
765 0000D644 # * SUMMARY: the final accumulator will be zero if:
766 0000D644 # * A: the most significant accumulator longword is '0'.
767 0000D644 # * B: the accumulator's exponent was zero AND either:
768 0000D644 # * b1: the accumulator is single precision OR
769 0000D644 # * b2: we're using the FPP WCS
770 0000D644 # * C: We are using the fpp-hardware wcs AND either:
771 0000D644 # * c1: the event was either floating Overflow or floating Underflow OR
772 0000D644 # * c2: the event was Reserved Operand and the instruction was not
773 0000D644 # * one of the 'compare' instructions.
774 0000D644 # *
775 0000D644 # ***************************************************************************
776 0000D644 # */
777 0000D644 # acc_trashed()
778 0000D644 # {
779 0000D644 13 00df jbr L493
780 0000D647 L494:
781 0000D647 # int clear_acc;
782 0000D647 # clear_acc = FALSE; /* initialize the clear flag */
783 0000D647 4d adc8 clrl -56(fp)
784 0000D64A # if( !dbl_ld_acc.m ) /* case A: */
785 0000D64A 5d effffffa5c tstl _dbl_ld_acc
786 0000D650 21 06 jneq L495
787 0000D652 # clear_acc = TRUE;
788 0000D652 0d 01 adc8 movl $1,-56(fp)
789 0000D656 # else
790 0000D656 11 7a jbr L496
791 0000D658 L495:
792 0000D658 # if( (!(dbl_ld_acc.m & 0x7f800000)) && /* case B: */
793 0000D658 # ( (precision == SGL) || (!no_fpp_wcs)) ) /* case b1, b2 */
794 0000D658 3d 8f7f800000 effffffa49 bitl $2139095040,_dbl_ld_acc
795 0000D663 21 17 jneq L497
796 0000D665 1d effffffa41 01 cmpl _precision,$1
797 0000D66C 31 08 jeql L9998
798 0000D66E 5d effffffa38 tstl _no_fpp_wcs
799 0000D674 21 06 jneq L497
800 0000D676 L9998:
801 0000D676 # clear_acc = TRUE;
802 0000D676 0d 01 adc8 movl $1,-56(fp)
803 0000D67A # else
804 0000D67A 11 56 jbr L498
805 0000D67C L497:
806 0000D67C # if( (!no_fpp_wcs) && /* case C: */
807 0000D67C # ( ( (test_event == ARITH_CODE) && /* case c1 */
808 0000D67C # ( (exp_code == FLT_OVFL_CODE) ||
809 0000D67C # (exp_code == FLT_UNDFL_CODE) ) ) ||
810 0000D67C # ( (test_event == RESOP_CODE) && /* case c2 */
811 0000D67C # ( (op_code != CMPF_OP_CODE) &&
812 0000D67C # (op_code != CMPF2_OP_CODE) &&
813 0000D67C # (op_code != CMPD_OP_CODE) &&
814 0000D67C # (op_code != CMPD2_OP_CODE) ) ) ) )
815 0000D67C 5d effffffa2a tstl _no_fpp_wcs
816 0000D682 21 4e jneq L499
817 0000D684 1d effffffa22 34 cmpl _test_event,$52
818 0000D68B 21 12 jneq L9996
819 0000D68D 1d effffffa19 04 cmpl _exp_code,$4
820 0000D694 31 38 jeql L9997
821 0000D696 1d effffffa10 05 cmpl _exp_code,$5
822 0000D69D 31 2f jeql L9997
823 0000D69F L9996:
824 0000D69F 1d effffffa07 2d cmpl _test_event,$45
825 0000D6A6 21 2a jneq L499
826 0000D6A8 1d effffff9fe 36 cmpl _op_code,$54
827 0000D6AF 31 21 jeql L499
828 0000D6B1 1d effffff9f5 8846 cmpl _op_code,$70
829 0000D6B9 31 17 jeql L499
830 0000D6BB 1d effffff9eb 37 cmpl _op_code,$55
831 0000D6C2 31 0e jeql L499
832 0000D6C4 1d effffff9e2 8847 cmpl _op_code,$71
833 0000D6CC 31 04 jeql L499
834 0000D6CE L9997:
835 0000D6CE # clear_acc = TRUE;
836 0000D6CE 0d 01 adc8 movl $1,-56(fp)
837 0000D6D2 # if( clear_acc ) {
838 0000D6D2 L499:
839 0000D6D2 L498:
840 0000D6D2 L496:
841 0000D6D2 5d adc8 tstl -56(fp)
842 0000D6D5 31 0e jeql L500
843 0000D6D7 # dbl_expected.m = 0; /* the Acc. s/b cleared */
844 0000D6D7 4d effffff9cf clrl _dbl_expected
845 0000D6DD # dbl_expected.l = 0;
846 0000D6DD 4d effffff9cd clrl _dbl_expected+4
847 0000D6E3 # } else {
848 0000D6E3 11 16 jbr L501
849 0000D6E5 L500:
850 0000D6E5 # dbl_expected.m = dbl_ld_acc.m; /* the Acc. s/b unchanged */
851 0000D6E5 0d effffff9c1 effffff9bc movl _dbl_ld_acc,_dbl_expected
852 0000D6F0 # dbl_expected.l = dbl_ld_acc.l;
853 0000D6F0 0d effffff9ba effffff9b5 movl _dbl_ld_acc+4,_dbl_expected+4
854 0000D6FB # }
855 0000D6FB L501:
856 0000D6FB # if( (dbl_expected.m != dbl_st_acc.m) ||
857 0000D6FB # ( (precision == DBL) && (dbl_expected.l != dbl_st_acc.l) ) )
858 0000D6FB 1d effffff9ab effffff9a6 cmpl _dbl_expected,_dbl_st_acc
859 0000D706 21 16 jneq L9995
860 0000D708 1d effffff99e 02 cmpl _precision,$2
861 0000D70F 21 11 jneq L502
862 0000D711 1d effffff999 effffff994 cmpl _dbl_expected+4,_dbl_st_acc+4
863 0000D71C 31 04 jeql L502
864 0000D71E L9995:
865 0000D71E # return( TRUE );
866 0000D71E 0d 01 50 movl $1,r0
867 0000D721 40 ret#1
868 0000D722 # else
869 0000D722 L502:
870 0000D722 # return( FALSE );
871 0000D722 4d 50 clrl r0
872 0000D724 40 ret#1
873 0000D725 # }
874 0000D725 40 ret#1
875 0000D726 .set L491,0x0
876 0000D726 L493:
877 0000D726 3c 38 5d 5e subl3 $56,fp,sp
878 0000D72A 13 ff1a jbr L494
879 0000D72D .data
880 00000874 * .text
881 0000D72D 00 .align 1
882 0000D72E .globl _chk_fpm_trap
883 0000D72E _chk_fpm_trap:
884 0000D72E 0000 .word L503
885 0000D730 #
886 0000D730 #
887 0000D730 #
888 0000D730 # /*
889 0000D730 # ***************************************************************************
890 0000D730 # *
891 0000D730 # * Check the results of an FPP Emulation Trap.
892 0000D730 # *
893 0000D730 # * Check the stack data, the final accumulator, and the registers. The data
894 0000D730 # * was saved by the FPM trap handler.
895 0000D730 # * The stack data is:
896 0000D730 # * - the PSL
897 0000D730 # * - the PC of the next instruction
898 0000D730 # * - the op-code
899 0000D730 # * - the operand's LS longword { for double precision instructions }
900 0000D730 # * - the operand's MS longword
901 0000D730 # *
902 0000D730 # ***************************************************************************
903 0000D730 # */
904 0000D730 # chk_fpm_trap()
905 0000D730 # {
906 0000D730 13 01e9 jbr L505
907 0000D733 L506:
908 0000D733 # exp_pc = code_addr + inst_size; /* expected PC on stack */
909 0000D733 1c effffff973 effffff96e addl3 _inst_size,_code_addr,r0
50
910 0000D73F 0d 50 effffff966 movl r0,_exp_pc
911 0000D746 # /*
912 0000D746 # * check the FPM variables pushed onto the stack
913 0000D746 # */
914 0000D746 # if( !no_ops ) /* if no operands then */
915 0000D746 5d effffff960 tstl _no_ops
916 0000D74C 21 0b jneq L507
917 0000D74E # dbl_value_1.m = fpm_ms_op; /* expect whatever was */
918 0000D74E 0d effffff958 effffff953 movl _fpm_ms_op,_dbl_value_1
919 0000D759 # dbl_value_1.l = fpm_ls_op; /* put on the stack */
920 0000D759 L507:
921 0000D759 0d effffff94d effffff94c movl _fpm_ls_op,_dbl_value_1+4
922 0000D764 # if( precision != DBL ) /* if single operand then */
923 0000D764 1d effffff942 02 cmpl _precision,$2
924 0000D76B 31 0b jeql L508
925 0000D76D # dbl_value_1.l = fpm_ls_op; /* no LS op. errors */
926 0000D76D 0d effffff939 effffff938 movl _fpm_ls_op,_dbl_value_1+4
927 0000D778 # if((fpm_ms_op != dbl_value_1.m) || /* check stack's MS op */
928 0000D778 L508:
929 0000D778 # (fpm_ls_op != dbl_value_1.l) || /* check stack's LS op */
930 0000D778 # (fpm_op_code != op_code) || /* check stack's op-code */
931 0000D778 # (fpm_pc != exp_pc) || /* check stack's PC */
932 0000D778 # (fpm_psl != init_psl) ) { /* check stack's PSL */
933 0000D778 1d effffff92e effffff929 cmpl _fpm_ms_op,_dbl_value_1
934 0000D783 21 37 jneq L9994
935 0000D785 1d effffff921 effffff920 cmpl _fpm_ls_op,_dbl_value_1+4
936 0000D790 21 2a jneq L9994
937 0000D792 1d effffff914 effffff90f cmpl _fpm_op_code,_op_code
938 0000D79D 21 1d jneq L9994
939 0000D79F 1d effffff907 effffff902 cmpl _fpm_pc,_exp_pc
940 0000D7AA 21 10 jneq L9994
941 0000D7AC 1d effffff8fa effffff8f5 cmpl _fpm_psl,_init_psl
942 0000D7B7 21 03 13 015f jeql L509
943 0000D7BC L9994:
944 0000D7BC # error = TRUE;
945 0000D7BC 0d 01 effffff8e9 movl $1,_error
946 0000D7C3 # errcnt++;
947 0000D7C3 6d effffff8e3 incl _errcnt
948 0000D7C9 # if( prt_error ) {
949 0000D7C9 5d effffff8dd tstl _prt_error
950 0000D7CF 21 03 13 0127 jeql L510
951 0000D7D4 # prt_evt_er_msg( bad_fpm_stack_msg );
952 0000D7D4 dd effffff8d2 pushl _bad_fpm_stack_msg
953 0000D7DA fe 08 effffff8cb callf $8,_prt_evt_er_msg
954 0000D7E1 # writes(" data on the stack expected\n");
955 0000D7E1 .data 1
956 0000090c * L511:
957 0000090c * 202064617461206F6E2074686 .ascii " data on the stack expected\12\0"
520737461636B202020202020
2065787065637465640A00
958 00000930 * .text
959 0000D7E1 dd 8f0000090c pushl $L511
960 0000D7E7 fe 08 effffff8be callf $8,_writes
961 0000D7EE # writes(" MS operand = ");
962 0000D7EE .data 1
963 00000930 * L512:
964 00000930 * 20204D53206F706572616E642 .ascii " MS operand = \0"
03D2000
965 00000940 * .text
966 0000D7EE dd 8f00000930 pushl $L512
967 0000D7F4 fe 08 effffff8b1 callf $8,_writes
968 0000D7FB # write32h( fpm_ms_op ); /* MS operand */
969 0000D7FB dd effffff8ab pushl _fpm_ms_op
970 0000D801 fe 08 effffff8a4 callf $8,_write32h
971 0000D808 # writes(", ");
972 0000D808 .data 1
973 00000940 * L513:
974 00000940 * 2C202000 .ascii ", \0"
975 00000944 * .text
976 0000D808 dd 8f00000940 pushl $L513
977 0000D80E fe 08 effffff897 callf $8,_writes
978 0000D815 # write32h( dbl_value_1.m );
979 0000D815 dd effffff891 pushl _dbl_value_1
980 0000D81B fe 08 effffff88a callf $8,_write32h
981 0000D822 # writes("\n LS operand = ");
982 0000D822 .data 1
983 00000944 * L514:
984 00000944 * 0A20204C53206F706572616E6 .ascii "\12 LS operand = \0"
4203D2000
985 00000955 * .text
986 0000D822 dd 8f00000944 pushl $L514
987 0000D828 fe 08 effffff87d callf $8,_writes
988 0000D82F # write32h( fpm_ls_op ); /* LS operand */
989 0000D82F dd effffff877 pushl _fpm_ls_op
990 0000D835 fe 08 effffff870 callf $8,_write32h
991 0000D83C # writes(", ");
992 0000D83C .data 1
993 00000955 * L515:
994 00000955 * 2C202000 .ascii ", \0"
995 00000959 * .text
996 0000D83C dd 8f00000955 pushl $L515
997 0000D842 fe 08 effffff863 callf $8,_writes
998 0000D849 # write32h( dbl_value_1.l );
999 0000D849 dd effffff861 pushl _dbl_value_1+4
1000 0000D84F fe 08 effffff856 callf $8,_write32h
1001 0000D856 # writes("\n op-code = ");
1002 0000D856 .data 1
1003 00000959 * L516:
1004 00000959 * 0A20202020206F702D636F646 .ascii "\12 op-code = \0"
5203D2000
1005 0000096a * .text
1006 0000D856 dd 8f00000959 pushl $L516
1007 0000D85C fe 08 effffff849 callf $8,_writes
1008 0000D863 # write32h( fpm_op_code ); /* op-code */
1009 0000D863 dd effffff843 pushl _fpm_op_code
1010 0000D869 fe 08 effffff83c callf $8,_write32h
1011 0000D870 # writes(", ");
1012 0000D870 .data 1
1013 0000096a * L517:
1014 0000096a * 2C202000 .ascii ", \0"
1015 0000096e * .text
1016 0000D870 dd 8f0000096a pushl $L517
1017 0000D876 fe 08 effffff82f callf $8,_writes
1018 0000D87D # write32h( op_code );
1019 0000D87D dd effffff829 pushl _op_code
1020 0000D883 fe 08 effffff822 callf $8,_write32h
1021 0000D88A # writes("\n PC = ");
1022 0000D88A .data 1
1023 0000096e * L518:
1024 0000096e * 0A20202020202020202050432 .ascii "\12 PC = \0"
0203D2000
1025 0000097f * .text
1026 0000D88A dd 8f0000096e pushl $L518
1027 0000D890 fe 08 effffff815 callf $8,_writes
1028 0000D897 # write32h( fpm_pc ); /* PC */
1029 0000D897 dd effffff80f pushl _fpm_pc
1030 0000D89D fe 08 effffff808 callf $8,_write32h
1031 0000D8A4 # writes(", ");
1032 0000D8A4 .data 1
1033 0000097f * L519:
1034 0000097f * 2C202000 .ascii ", \0"
1035 00000983 * .text
1036 0000D8A4 dd 8f0000097f pushl $L519
1037 0000D8AA fe 08 effffff7fb callf $8,_writes
1038 0000D8B1 # write32h( exp_pc );
1039 0000D8B1 dd effffff7f5 pushl _exp_pc
1040 0000D8B7 fe 08 effffff7ee callf $8,_write32h
1041 0000D8BE # writes("\n PSL = ");
1042 0000D8BE .data 1
1043 00000983 * L520:
1044 00000983 * 0A20202020202020202050534 .ascii "\12 PSL = \0"
C203D2000
1045 00000994 * .text
1046 0000D8BE dd 8f00000983 pushl $L520
1047 0000D8C4 fe 08 effffff7e1 callf $8,_writes
1048 0000D8CB # write32h( fpm_psl ); /* PSL */
1049 0000D8CB dd effffff7db pushl _fpm_psl
1050 0000D8D1 fe 08 effffff7d4 callf $8,_write32h
1051 0000D8D8 # writes(", ");
1052 0000D8D8 .data 1
1053 00000994 * L521:
1054 00000994 * 2C202000 .ascii ", \0"
1055 00000998 * .text
1056 0000D8D8 dd 8f00000994 pushl $L521
1057 0000D8DE fe 08 effffff7c7 callf $8,_writes
1058 0000D8E5 # write32h( init_psl );
1059 0000D8E5 dd effffff7c1 pushl _init_psl
1060 0000D8EB fe 08 effffff7ba callf $8,_write32h
1061 0000D8F2 # writec('\n');
1062 0000D8F2 dd 0a pushl $10
1063 0000D8F4 fe 08 effffff7b1 callf $8,_writec
1064 0000D8FB # }
1065 0000D8FB # if( halt_flg )
1066 0000D8FB L510:
1067 0000D8FB 5d effffff7ab tstl _halt_flg
1068 0000D901 31 09 jeql L522
1069 0000D903 # fpm_halt( BAD_FPM_STK_HLT ); /* halt on the error */
1070 0000D903 dd 07 pushl $7
1071 0000D905 fe 08 effffff7a0 callf $8,_fpm_halt
1072 0000D90C # if( loop_on_err )
1073 0000D90C L522:
1074 0000D90C 5d effffff79a tstl _loop_on_err
1075 0000D912 31 07 jeql L523
1076 0000D914 # force_loop = TRUE; /* set loop flag */
1077 0000D914 0d 01 effffff791 movl $1,_force_loop
1078 0000D91B # }
1079 0000D91B L523:
1080 0000D91B # }
1081 0000D91B L509:
1082 0000D91B 40 ret#2
1083 0000D91C .set L503,0x0
1084 0000D91C L505:
1085 0000D91C 13 fe14 jbr L506
1086 0000D91F .data
1086 0001A9CB .data
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.