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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / fpevent|
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1.1 root 1:
2: #include "evt_defs.h"
3:
4: /***********************************************************************
5: *
6: * COMMON ROUTINES FOR THE DEMAND PAGING TESTS
7: *
8: ***********************************************************************/
9:
10:
11:
12: /*
13: ***********************************************************************
14: * Print an FPP Events Test Error Message
15: *
16: * cycle: xx. EVT test xx. < your message here >
17: * instr: <inst name> <event type> {( disabled )} -data index = xx
18: * addressing mode: <addressing mode description>
19: * { piped entry test #x. <instruction buffer description> }
20: * inst_buf = xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
21: * initial ACC. = xxxxxxxx xxxxxxxx, operand 1 = xxxxxxxx xxxxxxxxx
22: * final ACC. = xxxxxxxx xxxxxxxx, operand 2 = xxxxxxxx xxxxxxxxx
23: ***********************************************************************
24: */
25: prt_evt_er_msg( msg )
26: char *msg;
27: {
28: writes("\ncycle: ");
29: writed( cycle ); /* print the cycle # */
30: writes(". EVT test ");
31: writeh( test_no ); /* print the test # */
32: writes(". ");
33: writes( msg ); /* print the error msg */
34: writes("\ninstr: ");
35: writes( op_name ); /* print the inst name */
36: writes(" Event: ");
37: writes( event_msg ); /* print the event type */
38: if( evt_disabled )
39: writes(" ( disabled )");
40: writes(" -data index = "); /* print the data index */
41: writed( index );
42: if( no_ops ) {
43: writes("\naddressing mode: ");
44: writes( addressing_modes[ addr_mode ] );
45: }
46: if( pipe_test ) {
47: writes("\npiped entry test #");
48: writed( pipe_test ); /* print the pipe test # */
49: writes(". ");
50: if( pipe_inst1 == LDD_OP_CODE )
51: writes("LDD (initial acc), ");
52: else if( pipe_inst1 == LDF_OP_CODE )
53: writes("LDF (initial acc), ");
54: else if( pipe_inst1 == MULD_OP_CODE )
55: writes("MULD (1.0), ");
56: else if( pipe_inst1 == MULF_OP_CODE )
57: writes("MULF (1.0), ");
58: writes( op_name );
59: if( no_ops == 1 )
60: writes(" (operand)");
61: else if( no_ops == 2 )
62: writes(" (op #1, op #2)");
63: }
64: print_inst_buf(); /* print the inst buf contents */
65: writes("initial ACC. = ");
66: write32h( dbl_ld_acc.m );
67: if( precision == DBL ) {
68: writec(' ');
69: write32h( dbl_ld_acc.l );
70: }
71: if( no_ops ) {
72: if( (op_code == CVFL_OP_CODE) || (op_code == CVDL_OP_CODE) )
73: writes(", stored value = ");
74: else
75: writes(", operand 1 = ");
76: write32h( dbl_value_1.m );
77: if( precision == DBL ) {
78: writec(' ');
79: write32h( dbl_value_1.l );
80: }
81: writec('\n');
82: } else
83: writes(", ");
84: writes(" final ACC. = ");
85: write32h( dbl_st_acc.m );
86: if( precision == DBL ) {
87: writec(' ');
88: write32h( dbl_st_acc.l );
89: }
90: if( no_ops == 2) {
91: writes(", operand 2 = ");
92: write32h( dbl_value_2.m );
93: if( precision == DBL ) {
94: writec(' ');
95: write32h( dbl_value_2.l );
96: }
97: }
98: writec('\n');
99: }
100:
101:
102:
103: /*
104: *******************************************************************
105: * print the contents of the instruction buffer
106: *******************************************************************
107: */
108: print_inst_buf()
109: {
110: writes("\ninst buf=");
111: write_lw_bytes( inst_buf[0] ); /* print word 0 as bytes */
112: write_lw_bytes( inst_buf[1] ); /* print word 1 as bytes */
113: write_lw_bytes( inst_buf[2] ); /* print word 2 as bytes */
114: write_lw_bytes( inst_buf[3] ); /* print word 2 as bytes */
115: write_lw_bytes( inst_buf[4] ); /* print word 2 as bytes */
116: writec('\n');
117: }
118:
119:
120:
121: /*
122: *******************************************************************
123: * print a longword a byte at a time
124: *******************************************************************
125: */
126: write_lw_bytes( lw )
127: int lw;
128: {
129: writec(' ');
130: writeh( (lw >> 28) & 0xf );
131: writeh( (lw >> 24) & 0xf );
132: writec(' ');
133: writeh( (lw >> 20) & 0xf );
134: writeh( (lw >> 16) & 0xf );
135: writec(' ');
136: writeh( (lw >> 12) & 0xf );
137: writeh( (lw >> 8) & 0xf );
138: writec(' ');
139: writeh( (lw >> 4) & 0xf );
140: writeh( (lw & 0xf) );
141: }
142:
143:
144:
145:
146: /*
147: ********************************************************************
148: *
149: * ERROR HALT ROUTINE ( for non-FPM event halts )
150: *
151: ********************************************************************
152: */
153: event_halt(halt_code)
154: int halt_code;
155: {
156: sgl_value_1 = halt_code;
157: asm("movl _test_no,r0"); /* r0 = test number */
158: asm("movl _op_code,r1"); /* r1 = instr's op-code */
159: asm("movl _sgl_value_1,r2"); /* r2 = error code */
160: asm("movl _cycle,r3"); /* r3 = cycle */
161: asm("movl _addr_code,r4"); /* r4 = addressing mode */
162: asm("movl _index,r5"); /* r5 = data pattern index */
163: /*
164: * put the operands used in regs 6 - 9
165: */
166: if( no_ops == 2 ) {
167: asm("movl _dbl_value_1,r6"); /* r6 = operand 1's MSW */
168: asm("movl _dbl_value_1+4,r7"); /* r7 = operand 1's LSW */
169: asm("movl _dbl_value_2,r8"); /* r8 = operand 2's MSW */
170: asm("movl _dbl_value_2+4,r9"); /* r9 = operand 2's LSW */
171: } else {
172: asm("movl _dbl_ld_acc,r6"); /* r6 = initial Acc's MSW */
173: asm("movl _dbl_ld_acc+4,r7"); /* r7 = initial Acc's LSW */
174: asm("movl _dbl_value_1,r8"); /* r8 = the operand's MSW */
175: asm("movl _dbl_value_1+4,r9"); /* r9 = the operand's LSW */
176: };
177: /*
178: * now set the type specific data in regs 10 - 12
179: */
180: if( halt_code == BAD_PSL_HLT ) {
181: asm("movl _init_psl,r10"); /* r10 = initial PSL value */
182: asm("movl _psl_val,r11"); /* r11 = final PSL value */
183: asm("movl _exp_psl,r12"); /* r12 = expected PSL value */
184: }
185: else if( halt_code == PUSH_PSL_HLT ) {
186: asm("movl _init_psl,r10"); /* r10 = initial PSL value */
187: asm("movl _event_psl,r11"); /* r11 = PSL on the stack */
188: }
189: else if( halt_code == BAD_REG_HLT ) {
190: sgl_value_1 = store_regs[reg_no];
191: sgl_value_2 = exp_regs[reg_no];
192: asm("movl _reg_no,r10"); /* r10 = register # */
193: asm("movl _sgl_value_1,r11"); /* r11 = actual reg value */
194: asm("movl _sgl_value_2,r12"); /* r12 = expected reg value */
195: }
196: else if( halt_code == BAD_ACC_HLT ) {
197: sgl_value_1 = dbl_expected.l;
198: asm("movl _dbl_st_acc,r10"); /* r10 = final Acc's MSW */
199: asm("movl _dbl_st_acc+4,r11"); /* r11 = final Acc's LSW */
200: asm("movl _dbl_expected,r12"); /* r12 = exp Acc's MSW */
201: asm("movl _sgl_value_1,r13"); /* r13 = exp Acc's LSW */
202: };
203: asm("halt");
204: }
205:
206:
207:
208:
209:
210: /*
211: ********************************************************************
212: *
213: * ERROR HALT ROUTINE FOR FPM EVENT HALTS
214: *
215: ********************************************************************
216: */
217: fpm_halt(halt_code)
218: int halt_code;
219: {
220: sgl_value_1 = halt_code;
221: asm("movl _test_no,r0"); /* r0 = test number */
222: asm("movl _op_code,r1"); /* r1 = instr's op-code */
223: asm("movl _sgl_value_1,r2"); /* r2 = error code */
224: asm("movl _cycle,r3"); /* r3 = cycle */
225: asm("movl _fpm_psl,r4"); /* r4 = PSL on the stack */
226: if( halt_code == BAD_FPM_STK_HLT ) { /* if bad FPM stack */
227: sgl_value_2 = dbl_value_1.l; /* LS op. expected */
228: asm("movl _init_psl,r5"); /* r5 = PSL expected */
229: asm("movl _fpm_pc,r6"); /* r6 = PC on the stack */
230: asm("movl _exp_pc,r7"); /* r7 = PC expected */
231: asm("movl _fpm_op_code,r8"); /* r8 = op-code on stack */
232: asm("movl _op_code,r9"); /* r9 = op-code expected */
233: asm("movl _fpm_ls_op,r10"); /* r10 = LS op. on stack */
234: asm("movl _sgl_value_2,r11"); /* r11 = LS op. expected */
235: asm("movl _fpm_ms_op,r12"); /* r12 = MS op. on stack */
236: asm("movl _dbl_value_1,r13"); /* r13 = MS op. expected */
237: asm("movl _index,r14"); /* r14 = data pattern index */
238: } else {
239: sgl_value_2 = dbl_st_acc.l; /* LS of final ACC */
240: sgl_value_3 = dbl_expected.l; /* LS of exp'd ACC */
241: asm("movl _fpm_pc,r5"); /* r5 = PC on the stack */
242: asm("movl _fpm_op_code,r6"); /* r6 = op-code on stack */
243: asm("movl _fpm_ls_op,r7"); /* r7 = LS op. on stack */
244: asm("movl _fpm_ms_op,r8"); /* r8 = LS op. on stack */
245: asm("movl _dbl_st_acc,r9"); /* r9 = MS of final ACC. */
246: asm("movl _sgl_value_2,r10"); /* r10 = LS of final ACC. */
247: asm("movl _dbl_expected,r11"); /* r11 = MS of exp'd ACC. */
248: asm("movl _sgl_value_3,r12"); /* r12 = LS of exp'd ACC. */
249: asm("movl _index,r13"); /* r13 = data pattern index */
250: }
251: asm("halt");
252: }
253:
254:
255:
256:
257: /*
258: ***********************************************************************
259: * fill a register buffer with known patterns
260: ***********************************************************************
261: */
262: fill_reg_buf( buffer )
263: int *buffer;
264: {
265: buffer[0] = 0x10101010; /* register '0' data */
266: buffer[1] = 0x11111111;
267: buffer[2] = 0x12121212;
268: buffer[3] = 0x13131313;
269: buffer[4] = 0x14141414;
270: buffer[5] = 0x15151515;
271: buffer[6] = 0x16161616;
272: buffer[7] = 0x17171717;
273: buffer[8] = 0x18181818;
274: buffer[9] = 0x19191919;
275: buffer[10] = 0x1a1a1a1a;
276: buffer[11] = 0x1b1b1b1b;
277: buffer[12] = 0x1c1c1c1c;
278: buffer[13] = 0x1d1d1d1d;
279: }
280:
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