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Power 6/32 Unix version 1.21

#include "evt_defs.h"

/***********************************************************************
*
*	COMMON ROUTINES FOR THE DEMAND PAGING TESTS
*
***********************************************************************/



/*
 ***********************************************************************
 *		Print an FPP Events Test Error Message
 *
 * cycle: xx. EVT test xx. < your message here >
 * instr: <inst name> <event type> {( disabled )}  -data index = xx
 * addressing mode: <addressing mode description>
 * { piped entry test #x.  <instruction buffer description> }
 * inst_buf = xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
 * initial ACC. = xxxxxxxx xxxxxxxx,  operand 1 = xxxxxxxx xxxxxxxxx
 *   final ACC. = xxxxxxxx xxxxxxxx,  operand 2 = xxxxxxxx xxxxxxxxx
 ***********************************************************************
*/
prt_evt_er_msg( msg )
char *msg;
{
	writes("\ncycle: ");
	writed( cycle );			/* print the cycle #     */
	writes(". EVT test ");
	writeh( test_no );			/* print the test #      */
	writes(". ");
	writes( msg );				/* print the error msg   */
	writes("\ninstr: ");
	writes( op_name );			/* print the inst name   */
	writes("  Event: ");
	writes( event_msg );			/* print the event type  */
	if( evt_disabled )
	    writes(" ( disabled )");
	writes("   -data index = ");		/* print the data index  */
	writed( index );
	if( no_ops ) {
	    writes("\naddressing mode: ");
	    writes( addressing_modes[ addr_mode ] );
	}
	if( pipe_test ) {
	     writes("\npiped entry test #");
	     writed( pipe_test );		/* print the pipe test # */
	     writes(".  ");
	     if( pipe_inst1 == LDD_OP_CODE )
		   writes("LDD (initial acc), ");
	       else if( pipe_inst1 == LDF_OP_CODE )
		   writes("LDF (initial acc), ");
	       else if( pipe_inst1 == MULD_OP_CODE )
		   writes("MULD (1.0), ");
	       else if( pipe_inst1 == MULF_OP_CODE )
		   writes("MULF (1.0), ");
	     writes( op_name );
	     if( no_ops == 1 )
		 writes(" (operand)");
	     else if( no_ops == 2 )
		 writes(" (op #1, op #2)");
	}
	print_inst_buf();		/* print the inst buf contents   */
	writes("initial ACC. = ");
	write32h( dbl_ld_acc.m );
	if( precision == DBL ) {
	     writec(' ');
	     write32h( dbl_ld_acc.l );
	}
	if( no_ops ) {
	     if( (op_code == CVFL_OP_CODE) || (op_code == CVDL_OP_CODE) )
	          writes(",   stored value = ");
	     else
	          writes(",   operand 1 = ");
	     write32h( dbl_value_1.m );
	     if( precision == DBL ) {
	          writec(' ');
	          write32h( dbl_value_1.l );
	     }
	     writec('\n');
	} else 
	     writes(", ");
	writes("  final ACC. = ");
	write32h( dbl_st_acc.m );
	if( precision == DBL ) {
	     writec(' ');
	     write32h( dbl_st_acc.l );
	}
	if( no_ops == 2) {
	     writes(",   operand 2 = ");
	     write32h( dbl_value_2.m );
	     if( precision == DBL ) {
	          writec(' ');
	          write32h( dbl_value_2.l );
	     }
	}
	writec('\n');
}



/*
 *******************************************************************
 *	print the contents of the instruction buffer
 *******************************************************************
*/
print_inst_buf()
{
	writes("\ninst buf=");
	write_lw_bytes( inst_buf[0] );	  /* print word 0 as bytes */
	write_lw_bytes( inst_buf[1] );	  /* print word 1 as bytes */
	write_lw_bytes( inst_buf[2] );	  /* print word 2 as bytes */
	write_lw_bytes( inst_buf[3] );	  /* print word 2 as bytes */
	write_lw_bytes( inst_buf[4] );	  /* print word 2 as bytes */
	writec('\n');
}



/*
 *******************************************************************
 *	print a longword a byte at a time
 *******************************************************************
*/
write_lw_bytes( lw )
int lw;
{
	writec(' ');
	writeh( (lw >> 28) & 0xf );
	writeh( (lw >> 24) & 0xf );
	writec(' ');
	writeh( (lw >> 20) & 0xf );
	writeh( (lw >> 16) & 0xf );
	writec(' ');
	writeh( (lw >> 12) & 0xf );
	writeh( (lw >> 8) & 0xf );
	writec(' ');
	writeh( (lw >> 4) & 0xf );
	writeh( (lw & 0xf) );
}
		 



/*
 ********************************************************************
 *
 *		ERROR HALT ROUTINE  ( for non-FPM event halts )
 *
 ********************************************************************
*/
event_halt(halt_code)
int halt_code;
{
	sgl_value_1 = halt_code;
	asm("movl _test_no,r0");	    /* r0  = test number        */
	asm("movl _op_code,r1");	    /* r1  = instr's op-code    */
	asm("movl _sgl_value_1,r2");	    /* r2  = error code         */
	asm("movl _cycle,r3");		    /* r3  = cycle              */
	asm("movl _addr_code,r4");	    /* r4  = addressing mode    */
	asm("movl _index,r5");		    /* r5  = data pattern index */
/*
 * put the operands used in regs 6 - 9
*/
	if( no_ops == 2 ) {
	     asm("movl _dbl_value_1,r6");   /* r6  = operand 1's MSW    */
	     asm("movl _dbl_value_1+4,r7"); /* r7  = operand 1's LSW    */
	     asm("movl _dbl_value_2,r8");   /* r8  = operand 2's MSW    */
	     asm("movl _dbl_value_2+4,r9"); /* r9  = operand 2's LSW    */
	} else {
	     asm("movl _dbl_ld_acc,r6");    /* r6  = initial Acc's MSW  */
	     asm("movl _dbl_ld_acc+4,r7");  /* r7  = initial Acc's LSW  */
	     asm("movl _dbl_value_1,r8");   /* r8  = the operand's MSW  */
	     asm("movl _dbl_value_1+4,r9"); /* r9  = the operand's LSW  */
	};
/*
 * now set the type specific data in regs 10 - 12
*/
	if( halt_code == BAD_PSL_HLT ) {
	     asm("movl _init_psl,r10");	    /* r10 = initial PSL value  */
	     asm("movl _psl_val,r11");	    /* r11 = final PSL value    */
	     asm("movl _exp_psl,r12");	    /* r12 = expected PSL value */
	}
	else if( halt_code == PUSH_PSL_HLT ) {
	     asm("movl _init_psl,r10");	    /* r10 = initial PSL value  */
	     asm("movl _event_psl,r11");    /* r11 = PSL on the stack   */
	}
	else if( halt_code == BAD_REG_HLT ) {
	     sgl_value_1 = store_regs[reg_no];
	     sgl_value_2 = exp_regs[reg_no];
	     asm("movl _reg_no,r10");	    /* r10 = register #         */
	     asm("movl _sgl_value_1,r11");  /* r11 = actual reg value   */
	     asm("movl _sgl_value_2,r12");  /* r12 = expected reg value */
	}
	else if( halt_code == BAD_ACC_HLT ) {
	     sgl_value_1 = dbl_expected.l;
	     asm("movl _dbl_st_acc,r10");   /* r10 = final Acc's MSW    */
	     asm("movl _dbl_st_acc+4,r11"); /* r11 = final Acc's LSW    */
	     asm("movl _dbl_expected,r12"); /* r12 = exp Acc's MSW      */
	     asm("movl _sgl_value_1,r13");  /* r13 = exp Acc's LSW      */
	};
	asm("halt");
}





/*
 ********************************************************************
 *
 *		ERROR HALT ROUTINE FOR FPM EVENT HALTS 
 *
 ********************************************************************
*/
fpm_halt(halt_code)
int halt_code;
{
	sgl_value_1 = halt_code;
	asm("movl _test_no,r0");		/* r0  = test number        */
	asm("movl _op_code,r1");		/* r1  = instr's op-code    */
	asm("movl _sgl_value_1,r2");		/* r2  = error code         */
	asm("movl _cycle,r3");			/* r3  = cycle              */
	asm("movl _fpm_psl,r4");		/* r4  = PSL on the stack   */
	if( halt_code == BAD_FPM_STK_HLT ) {		/* if bad FPM stack */
	     sgl_value_2 = dbl_value_1.l;		/* LS op. expected */
	     asm("movl _init_psl,r5");		/* r5  = PSL expected       */
	     asm("movl _fpm_pc,r6");		/* r6  = PC on the stack    */
	     asm("movl _exp_pc,r7");		/* r7  = PC expected        */
	     asm("movl _fpm_op_code,r8");	/* r8  = op-code on stack   */
	     asm("movl _op_code,r9");		/* r9  = op-code expected   */
	     asm("movl _fpm_ls_op,r10");	/* r10 = LS op. on stack    */
	     asm("movl _sgl_value_2,r11");	/* r11 = LS op. expected    */
	     asm("movl _fpm_ms_op,r12");	/* r12 = MS op. on stack    */
	     asm("movl _dbl_value_1,r13");	/* r13 = MS op. expected    */
	     asm("movl _index,r14");		/* r14 = data pattern index */
	} else {
	     sgl_value_2 = dbl_st_acc.l;		/* LS of final ACC */
	     sgl_value_3 = dbl_expected.l;		/* LS of exp'd ACC */
	     asm("movl _fpm_pc,r5");		/* r5  = PC on the stack    */
	     asm("movl _fpm_op_code,r6");	/* r6  = op-code on stack   */
	     asm("movl _fpm_ls_op,r7");		/* r7  = LS op. on stack    */
	     asm("movl _fpm_ms_op,r8");		/* r8  = LS op. on stack    */
	     asm("movl _dbl_st_acc,r9");	/* r9  = MS of final ACC.   */
	     asm("movl _sgl_value_2,r10");	/* r10 = LS of final ACC.   */
	     asm("movl _dbl_expected,r11");	/* r11 = MS of exp'd ACC.   */
	     asm("movl _sgl_value_3,r12");	/* r12 = LS of exp'd ACC.   */
	     asm("movl _index,r13");		/* r13 = data pattern index */
	}
	asm("halt");
}




/*
 ***********************************************************************
 *	fill a register buffer with known patterns
 ***********************************************************************
*/
fill_reg_buf( buffer )
int *buffer;
{
	buffer[0]  = 0x10101010;	/* register '0' data */
	buffer[1]  = 0x11111111;
	buffer[2]  = 0x12121212;
	buffer[3]  = 0x13131313;
	buffer[4]  = 0x14141414;
	buffer[5]  = 0x15151515;
	buffer[6]  = 0x16161616;
	buffer[7]  = 0x17171717;
	buffer[8]  = 0x18181818;
	buffer[9]  = 0x19191919;
	buffer[10] = 0x1a1a1a1a;
	buffer[11] = 0x1b1b1b1b;
	buffer[12] = 0x1c1c1c1c;
	buffer[13] = 0x1d1d1d1d;
}

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