|
|
Power 6/32 Unix version 1.21
1 00000000 LL0:
2 00000000 .data
3 00000190 * .text
4 00000000 .align 1
5 00000000 .globl _div_by_0_test
6 00000000 _div_by_0_test:
7 0000D920 0000 .word L381
8 0000D922 #
9 0000D922 # #include "evt_defs.h"
10 0000D922 #
11 0000D922 # /*
12 0000D922 # ********************************************************************
13 0000D922 # *
14 0000D922 # * MONITOR FOR THE FPP DIVIDE BY ZERO EVENT TEST
15 0000D922 # *
16 0000D922 # * 26-Mar-85 JJM: written
17 0000D922 # *
18 0000D922 # ********************************************************************
19 0000D922 # */
20 0000D922 # div_by_0_test()
21 0000D922 # {
22 0000D922 13 00a1 jbr L383
23 0000D925 L384:
24 0000D925 # event_msg = "Divide By ZERO";
25 0000D925 .data 1
26 00000190 * L385:
27 00000190 * 446976696465204279205A455 .ascii "Divide By ZERO\0"
24F00
28 0000019f * .text
29 0000D925 0d 8f00000190 effffffff0 movl $L385,_event_msg
30 0000D930 # test_event = ARITH_CODE; /* expect an arithmetic fault */
31 0000D930 0d 34 efffffffe9 movl $52,_test_event
32 0000D937 # exp_code = FLT_0_DIV_CODE; /* -specificly divide by 0 */
33 0000D937 0d 03 efffffffe2 movl $3,_exp_code
34 0000D93E # disable_mask = 0; /* don't disable any events */
35 0000D93E 4b efffffffdc clrw _disable_mask
36 0000D944 # evt_disabled = FALSE; /* expected event is enabled */
37 0000D944 4d efffffffd6 clrl _evt_disabled
38 0000D94A # if( evt_inst ) /* was the op-code specified? */
39 0000D94A 5d efffffffd0 tstl _evt_inst
40 0000D950 31 65 jeql L386
41 0000D952 # {
42 0000D952 # if( evt_inst == DIVF_OP_CODE )
43 0000D952 1d efffffffc8 8900f6 cmpl _evt_inst,$246
44 0000D95B 21 09 jneq L387
45 0000D95D # run_divf(); /* test the DIVF instruction */
46 0000D95D fe 04 ef00000066 callf $4,_run_divf
47 0000D964 # else if( evt_inst == DIVD_OP_CODE )
48 0000D964 11 4f jbr L389
49 0000D966 L387:
50 0000D966 1d efffffffb4 8900f7 cmpl _evt_inst,$247
51 0000D96F 21 09 jneq L390
52 0000D971 # run_divd(); /* test the DIVD instruction */
53 0000D971 fe 04 ef000000c4 callf $4,_run_divd
54 0000D978 # else if( (prt_hdrs) && (cycle == 1) )
55 0000D978 11 3b jbr L392
56 0000D97A L390:
57 0000D97A 5d efffffffa0 tstl _prt_hdrs
58 0000D980 31 33 jeql L393
59 0000D982 1d efffffff98 01 cmpl _cycle,$1
60 0000D989 21 2a jneq L393
61 0000D98B # {
62 0000D98B # writes("There are no DIVIDE BY ZERO faults with op-code ");
63 0000D98B .data 1
64 0000019f * L395:
65 0000019f * 546865726520617265206E6F2 .ascii "There are no DIVIDE BY ZERO faults with op-code \0"
0444956494445204259205A45
524F206661756C74732077697
468206F702D636F64652000
66 000001d0 * .text
67 0000D98B dd 8f0000019f pushl $L395
68 0000D991 fe 08 efffffff88 callf $8,_writes
69 0000D998 # writeh( evt_inst ); /* print the ersatz op-code */
70 0000D998 dd efffffff82 pushl _evt_inst
71 0000D99E fe 08 efffffff7b callf $8,_writeh
72 0000D9A5 # writec('\n');
73 0000D9A5 dd 0a pushl $10
74 0000D9A7 fe 08 efffffff72 callf $8,_writec
75 0000D9AE # error = TRUE; /* needed for line feed control */
76 0000D9AE 0d 01 efffffff6b movl $1,_error
77 0000D9B5 # }
78 0000D9B5 # }
79 0000D9B5 L393:
80 0000D9B5 L392:
81 0000D9B5 L389:
82 0000D9B5 # else /* test both DIVF and DIVD */
83 0000D9B5 11 0e jbr L398
84 0000D9B7 L386:
85 0000D9B7 # {
86 0000D9B7 # run_divf(); /* test the DIVF instruction */
87 0000D9B7 fe 04 ef0000000c callf $4,_run_divf
88 0000D9BE # run_divd(); /* test the DIVD instruction */
89 0000D9BE fe 04 ef00000077 callf $4,_run_divd
90 0000D9C5 # }
91 0000D9C5 L398:
92 0000D9C5 # }
93 0000D9C5 40 ret#2
94 0000D9C6 .set L381,0x0
95 0000D9C6 L383:
96 0000D9C6 13 ff5c jbr L384
97 0000D9C9 .data
98 00000190 * .text
99 0000D9C9 00 .align 1
100 0000D9CA .globl _run_divf
101 0000D9CA _run_divf:
102 0000D9CA 0000 .word L399
103 0000D9CC #
104 0000D9CC #
105 0000D9CC #
106 0000D9CC #
107 0000D9CC # /*
108 0000D9CC # **********************************************************************
109 0000D9CC # *
110 0000D9CC # * SET UP TO TEST DIVIDE BY ZERO WITH THE DIVF INSTRUCTION
111 0000D9CC # *
112 0000D9CC # **********************************************************************
113 0000D9CC # */
114 0000D9CC # run_divf()
115 0000D9CC # {
116 0000D9CC 11 6c jbr L401
117 0000D9CE L402:
118 0000D9CE # op_code = DIVF_OP_CODE; /* set the inst's op_code */
119 0000D9CE 0d 8900f6 efffffff49 movl $246,_op_code
120 0000D9D7 # op_name = "DIVF "; /* set the inst's name */
121 0000D9D7 .data 1
122 000001d0 * L403:
123 000001d0 * 444956462000 .ascii "DIVF \0"
124 000001d6 * .text
125 0000D9D7 0d 8f000001d0 efffffff3e movl $L403,_op_name
126 0000D9E2 # precision = SGL;
127 0000D9E2 0d 01 efffffff37 movl $1,_precision
128 0000D9E9 # acc_ld_size = SGL; /* load a single precision Acc. */
129 0000D9E9 0d 01 efffffff30 movl $1,_acc_ld_size
130 0000D9F0 # sgl_op = TRUE;
131 0000D9F0 0d 01 efffffff29 movl $1,_sgl_op
132 0000D9F7 # valid_test = TRUE; /* we're running a test */
133 0000D9F7 0d 01 efffffff22 movl $1,_valid_test
134 0000D9FE # data_ptr = zero_divide_data; /* set the data ptr */
135 0000D9FE 0d 8f00000000 efffffff17 movl $_zero_divide_data,_data_ptr
136 0000DA09 # max_index = zero_divide_cnt; /* set the max index */
137 0000DA09 0d efffffff11 efffffff0c movl _zero_divide_cnt,_max_index
138 0000DA14 # if( (prt_hdrs) && (cycle == 1) )
139 0000DA14 5d efffffff06 tstl _prt_hdrs
140 0000DA1A 31 16 jeql L404
141 0000DA1C 1d effffffefe 01 cmpl _cycle,$1
142 0000DA23 21 0d jneq L404
143 0000DA25 # writes( op_name );
144 0000DA25 dd effffffef5 pushl _op_name
145 0000DA2B fe 08 effffffeee callf $8,_writes
146 0000DA32 # test_inst();
147 0000DA32 L404:
148 0000DA32 fe 04 effffffee7 callf $4,_test_inst
149 0000DA39 # }
150 0000DA39 40 ret#2
151 0000DA3A .set L399,0x0
152 0000DA3A L401:
153 0000DA3A 11 92 jbr L402
154 0000DA3C .data
155 00000190 * .text
156 0000DA3C .align 1
157 0000DA3C .globl _run_divd
158 0000DA3C _run_divd:
159 0000DA3C 0000 .word L406
160 0000DA3E #
161 0000DA3E #
162 0000DA3E #
163 0000DA3E # /*
164 0000DA3E # **********************************************************************
165 0000DA3E # *
166 0000DA3E # * SET UP TO TEST DIVIDE BY ZERO WITH THE DIVD INSTRUCTION
167 0000DA3E # *
168 0000DA3E # **********************************************************************
169 0000DA3E # */
170 0000DA3E # run_divd()
171 0000DA3E # {
172 0000DA3E 11 6b jbr L408
173 0000DA40 L409:
174 0000DA40 # op_code = DIVD_OP_CODE; /* set the inst's op_code */
175 0000DA40 0d 8900f7 effffffed7 movl $247,_op_code
176 0000DA49 # op_name = "DIVD "; /* set the inst's name */
177 0000DA49 .data 1
178 000001d6 * L410:
179 000001d6 * 444956442000 .ascii "DIVD \0"
180 000001dc * .text
181 0000DA49 0d 8f000001d6 effffffecc movl $L410,_op_name
182 0000DA54 # precision = DBL;
183 0000DA54 0d 02 effffffec5 movl $2,_precision
184 0000DA5B # acc_ld_size = DBL; /* load a double precision Acc. */
185 0000DA5B 0d 02 effffffebe movl $2,_acc_ld_size
186 0000DA62 # sgl_op = FALSE;
187 0000DA62 4d effffffeb8 clrl _sgl_op
188 0000DA68 # valid_test = TRUE; /* we're running a test */
189 0000DA68 0d 01 effffffeb1 movl $1,_valid_test
190 0000DA6F # data_ptr = zero_divide_data; /* set the data ptr */
191 0000DA6F 0d 8f00000000 effffffea6 movl $_zero_divide_data,_data_ptr
192 0000DA7A # max_index = zero_divide_cnt; /* set the max index */
193 0000DA7A 0d effffffea0 effffffe9b movl _zero_divide_cnt,_max_index
194 0000DA85 # if( (prt_hdrs) && (cycle == 1) )
195 0000DA85 5d effffffe95 tstl _prt_hdrs
196 0000DA8B 31 16 jeql L411
197 0000DA8D 1d effffffe8d 01 cmpl _cycle,$1
198 0000DA94 21 0d jneq L411
199 0000DA96 # writes( op_name );
200 0000DA96 dd effffffe84 pushl _op_name
201 0000DA9C fe 08 effffffe7d callf $8,_writes
202 0000DAA3 # test_inst();
203 0000DAA3 L411:
204 0000DAA3 fe 04 effffffe76 callf $4,_test_inst
205 0000DAAA # }
206 0000DAAA 40 ret#2
207 0000DAAB .set L406,0x0
208 0000DAAB L408:
209 0000DAAB 11 93 jbr L409
210 0000DAAD .data
210 0001B3CD .data
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.