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1.1 root 1: 1 00000000 LL0:
2: 2 00000000 .data
3: 3 000001e0 * .text
4: 4 00000000 .align 1
5: 5 00000000 .globl _fpm_test
6: 6 00000000 _fpm_test:
7: 7 0000E430 0000 .word L381
8: 8 0000E432 #
9: 9 0000E432 # #include "evt_defs.h"
10: 10 0000E432 #
11: 11 0000E432 # /*
12: 12 0000E432 # ********************************************************************
13: 13 0000E432 # *
14: 14 0000E432 # * MONITOR FOR THE FPP EMULATION TRAP INTERFACE TEST
15: 15 0000E432 # *
16: 16 0000E432 # ********************************************************************
17: 17 0000E432 # */
18: 18 0000E432 # fpm_test()
19: 19 0000E432 # {
20: 20 0000E432 13 00ab jbr L383
21: 21 0000E435 L384:
22: 22 0000E435 # event_msg = "FPP Emulation";
23: 23 0000E435 .data 1
24: 24 000001e0 * L385:
25: 25 000001e0 * 46505020456D756C6174696F6 .ascii "FPP Emulation\0"
26: E00
27: 26 000001ee * .text
28: 27 0000E435 0d 8f000001e0 effffffff0 movl $L385,_event_msg
29: 28 0000E440 # test_event = FPM_CODE;
30: 29 0000E440 0d 37 efffffffe9 movl $55,_test_event
31: 30 0000E447 # disable_mask = 0; /* don't disable any events */
32: 31 0000E447 4b efffffffe3 clrw _disable_mask
33: 32 0000E44D # evt_disabled = FALSE; /* expected event is enabled */
34: 33 0000E44D 4d efffffffdd clrl _evt_disabled
35: 34 0000E453 # if( evt_inst ) /* was the op-code specified? */
36: 35 0000E453 5d efffffffd7 tstl _evt_inst
37: 36 0000E459 31 62 jeql L386
38: 37 0000E45B # {
39: 38 0000E45B # inst_index = get_fpm_index( evt_inst );
40: 39 0000E45B dd efffffffcf pushl _evt_inst
41: 40 0000E461 fe 08 ef00000164 callf $8,_get_fpm_index
42: 41 0000E468 0d 50 efffffffc1 movl r0,_inst_index
43: 42 0000E46F # if( inst_index < 0 ) {
44: 43 0000E46F 5d efffffffbb tstl _inst_index
45: 44 0000E475 81 3d jgeq L388
46: 45 0000E477 # if( (prt_hdrs) && (cycle == 1) ) /* no reserved ops */
47: 46 0000E477 5d efffffffb3 tstl _prt_hdrs
48: 47 0000E47D 31 33 jeql L389
49: 48 0000E47F 1d efffffffab 01 cmpl _cycle,$1
50: 49 0000E486 21 2a jneq L389
51: 50 0000E488 # {
52: 51 0000E488 # writes(
53: 52 0000E488 # "There is no FLOATING POINT EMULATION with op-code" );
54: 53 0000E488 .data 1
55: 54 000001ee * L391:
56: 55 000001ee * 5468657265206973206E6F204 .ascii "There is no FLOATING POINT EMULATION with op-code\0"
57: 64C4F4154494E4720504F494E
58: 5420454D554C4154494F4E207
59: 7697468206F702D636F646500
60: 56 00000220 * .text
61: 57 0000E488 dd 8f000001ee pushl $L391
62: 58 0000E48E fe 08 efffffff9b callf $8,_writes
63: 59 0000E495 # writeh( evt_inst ); /* print the ersatz op-code */
64: 60 0000E495 dd efffffff95 pushl _evt_inst
65: 61 0000E49B fe 08 efffffff8e callf $8,_writeh
66: 62 0000E4A2 # writec('\n');
67: 63 0000E4A2 dd 0a pushl $10
68: 64 0000E4A4 fe 08 efffffff85 callf $8,_writec
69: 65 0000E4AB # error = TRUE; /* needed for line feed control */
70: 66 0000E4AB 0d 01 efffffff7e movl $1,_error
71: 67 0000E4B2 # }
72: 68 0000E4B2 # } else
73: 69 0000E4B2 L389:
74: 70 0000E4B2 11 07 jbr L394
75: 71 0000E4B4 L388:
76: 72 0000E4B4 # test_fpm_inst(); /* test the instruction */
77: 73 0000E4B4 fe 04 ef00000029 callf $4,_test_fpm_inst
78: 74 0000E4BB L394:
79: 75 0000E4BB # } else /* test all applicable op-codes */
80: 76 0000E4BB 11 22 jbr L396
81: 77 0000E4BD L386:
82: 78 0000E4BD # for(inst_index=0; inst_index < size_fpm_tbl; inst_index++)
83: 79 0000E4BD 4d efffffff6d clrl _inst_index
84: 80 0000E4C3 L399:
85: 81 0000E4C3 1d efffffff67 efffffff62 cmpl _inst_index,_size_fpm_tbl
86: 82 0000E4CE 81 0f jgeq L398
87: 83 0000E4D0 # test_fpm_inst();
88: 84 0000E4D0 fe 04 ef0000000d callf $4,_test_fpm_inst
89: 85 0000E4D7 L397:
90: 86 0000E4D7 6d efffffff53 incl _inst_index
91: 87 0000E4DD 11 e4 jbr L399
92: 88 0000E4DF L398:
93: 89 0000E4DF L396:
94: 90 0000E4DF # }
95: 91 0000E4DF 40 ret#2
96: 92 0000E4E0 .set L381,0x0
97: 93 0000E4E0 L383:
98: 94 0000E4E0 13 ff52 jbr L384
99: 95 0000E4E3 .data
100: 96 000001e0 * .text
101: 97 0000E4E3 00 .align 1
102: 98 0000E4E4 .globl _test_fpm_inst
103: 99 0000E4E4 _test_fpm_inst:
104: 100 0000E4E4 0000 .word L400
105: 101 0000E4E6 #
106: 102 0000E4E6 #
107: 103 0000E4E6 #
108: 104 0000E4E6 # /*
109: 105 0000E4E6 # ***************************************************************************
110: 106 0000E4E6 # *
111: 107 0000E4E6 # * Run the Reserved Operand Fault on one instruction
112: 108 0000E4E6 # *
113: 109 0000E4E6 # ***************************************************************************
114: 110 0000E4E6 # */
115: 111 0000E4E6 # test_fpm_inst()
116: 112 0000E4E6 # {
117: 113 0000E4E6 13 00df jbr L402
118: 114 0000E4E9 L403:
119: 115 0000E4E9 # valid_test = TRUE; /* a test is being run */
120: 116 0000E4E9 0d 01 efffffff40 movl $1,_valid_test
121: 117 0000E4F0 # op_code = fpm_tbl[ inst_index ].inst_code;
122: 118 0000E4F0 0d efffffff3a 50 movl _inst_index,r0
123: 119 0000E4F7 48 04 50 50 shll $4,r0,r0
124: 120 0000E4FB 0d e000000000 efffffff2a movl _fpm_tbl(r0),_op_code
125: 121 0000E506 # op_name = fpm_tbl[ inst_index ].name;
126: 122 0000E506 0d efffffff24 50 movl _inst_index,r0
127: 123 0000E50D 48 04 50 50 shll $4,r0,r0
128: 124 0000E511 0d e000000004 efffffff14 movl _fpm_tbl+4(r0),_op_name
129: 125 0000E51C # precision = fpm_tbl[ inst_index ].precision;
130: 126 0000E51C 0d efffffff0e 50 movl _inst_index,r0
131: 127 0000E523 48 04 50 50 shll $4,r0,r0
132: 128 0000E527 0d e00000000c effffffefe movl _fpm_tbl+12(r0),_precision
133: 129 0000E532 # no_ops = fpm_tbl[ inst_index ].no_operands;
134: 130 0000E532 0d effffffef8 50 movl _inst_index,r0
135: 131 0000E539 48 04 50 50 shll $4,r0,r0
136: 132 0000E53D 0d e000000008 effffffee8 movl _fpm_tbl+8(r0),_no_ops
137: 133 0000E548 # data_ptr = fpm_data;
138: 134 0000E548 0d 8f00000000 effffffedd movl $_fpm_data,_data_ptr
139: 135 0000E553 # max_index = fpm_data_cnt;
140: 136 0000E553 0d effffffed7 effffffed2 movl _fpm_data_cnt,_max_index
141: 137 0000E55E # if( precision == SGL ) {
142: 138 0000E55E 1d effffffecc 01 cmpl _precision,$1
143: 139 0000E565 21 10 jneq L404
144: 140 0000E567 # sgl_op = TRUE;
145: 141 0000E567 0d 01 effffffec2 movl $1,_sgl_op
146: 142 0000E56E # acc_ld_size = SGL; /* use a sgl precision Acc. */
147: 143 0000E56E 0d 01 effffffebb movl $1,_acc_ld_size
148: 144 0000E575 # } else {
149: 145 0000E575 11 0d jbr L405
150: 146 0000E577 L404:
151: 147 0000E577 # sgl_op = FALSE;
152: 148 0000E577 4d effffffeb3 clrl _sgl_op
153: 149 0000E57D # acc_ld_size = DBL; /* use a dbl precision Acc. */
154: 150 0000E57D 0d 02 effffffeac movl $2,_acc_ld_size
155: 151 0000E584 # }
156: 152 0000E584 L405:
157: 153 0000E584 # if( (prt_hdrs) && (cycle == 1) ) {
158: 154 0000E584 5d effffffea6 tstl _prt_hdrs
159: 155 0000E58A 31 34 jeql L406
160: 156 0000E58C 1d effffffe9e 01 cmpl _cycle,$1
161: 157 0000E593 21 2b jneq L406
162: 158 0000E595 # if( (!evt_inst) && /* print a line feed if */
163: 159 0000E595 # (op_code == LOGF_OP_CODE) ) /* the 1st line is full */
164: 160 0000E595 5d effffffe95 tstl _evt_inst
165: 161 0000E59B 21 16 jneq L407
166: 162 0000E59D 1d effffffe8d 35 cmpl _op_code,$53
167: 163 0000E5A4 21 0d jneq L407
168: 164 0000E5A6 # writes("\n ");
169: 165 0000E5A6 .data 1
170: 166 00000220 * L408:
171: 167 00000220 * 0A20202020202020202020202 .ascii "\12 \0"
172: 0202020202020202020202000
173: 168 00000239 * .text
174: 169 0000E5A6 dd 8f00000220 pushl $L408
175: 170 0000E5AC fe 08 effffffe7d callf $8,_writes
176: 171 0000E5B3 # writes( op_name ); /* print the instruction's name */
177: 172 0000E5B3 L407:
178: 173 0000E5B3 dd effffffe77 pushl _op_name
179: 174 0000E5B9 fe 08 effffffe70 callf $8,_writes
180: 175 0000E5C0 # }
181: 176 0000E5C0 # test_inst();
182: 177 0000E5C0 L406:
183: 178 0000E5C0 fe 04 effffffe69 callf $4,_test_inst
184: 179 0000E5C7 # }
185: 180 0000E5C7 40 ret#2
186: 181 0000E5C8 .set L400,0x0
187: 182 0000E5C8 L402:
188: 183 0000E5C8 13 ff1e jbr L403
189: 184 0000E5CB .data
190: 185 000001e0 * .text
191: 186 0000E5CB 00 .align 1
192: 187 0000E5CC .globl _get_fpm_index
193: 188 0000E5CC _get_fpm_index:
194: 189 0000E5CC 0000 .word L410
195: 190 0000E5CE #
196: 191 0000E5CE #
197: 192 0000E5CE #
198: 193 0000E5CE # /*
199: 194 0000E5CE # ***************************************************************************
200: 195 0000E5CE # *
201: 196 0000E5CE # * GET THE INSTRUCTION TABLE INDEX FOR AN OP-CODE
202: 197 0000E5CE # *
203: 198 0000E5CE # * Given the op_code of an instruction, return the instruction's index in
204: 199 0000E5CE # * the FPM instruction table. Return a negative number if the op-code isn't
205: 200 0000E5CE # * in the table.
206: 201 0000E5CE # *
207: 202 0000E5CE # **************************************************************************
208: 203 0000E5CE # */
209: 204 0000E5CE # get_fpm_index( op_code )
210: 205 0000E5CE # {
211: 206 0000E5CE 11 38 jbr L412
212: 207 0000E5D0 L413:
213: 208 0000E5D0 # int x;
214: 209 0000E5D0 # x = 0;
215: 210 0000E5D0 4d adc8 clrl -56(fp)
216: 211 0000E5D3 # while( (fpm_tbl[x].inst_code != op_code) && (x < size_fpm_tbl) )
217: 212 0000E5D3 L414:
218: 213 0000E5D3 0d adc8 50 movl -56(fp),r0
219: 214 0000E5D7 48 04 50 50 shll $4,r0,r0
220: 215 0000E5DB 1d e000000000 ad04 cmpl _fpm_tbl(r0),4(fp)
221: 216 0000E5E3 31 0f jeql L415
222: 217 0000E5E5 1d adc8 effffffe43 cmpl -56(fp),_size_fpm_tbl
223: 218 0000E5ED 81 05 jgeq L415
224: 219 0000E5EF # x++;
225: 220 0000E5EF 6d adc8 incl -56(fp)
226: 221 0000E5F2 11 df jbr L414
227: 222 0000E5F4 L415:
228: 223 0000E5F4 # if( x == size_fpm_tbl )
229: 224 0000E5F4 1d adc8 effffffe34 cmpl -56(fp),_size_fpm_tbl
230: 225 0000E5FC 21 04 jneq L416
231: 226 0000E5FE # x = -1;
232: 227 0000E5FE ec 01 adc8 mnegl $1,-56(fp)
233: 228 0000E602 # return( x );
234: 229 0000E602 L416:
235: 230 0000E602 0d adc8 50 movl -56(fp),r0
236: 231 0000E606 40 ret#1
237: 232 0000E607 # }
238: 233 0000E607 40 ret#1
239: 234 0000E608 .set L410,0x0
240: 235 0000E608 L412:
241: 236 0000E608 3c 38 5d 5e subl3 $56,fp,sp
242: 237 0000E60C 11 c2 jbr L413
243: 238 0000E60E .data
244: 239 000001e0 * #
245: 240 000001e0 * #
246: 240 000001e0 * #
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