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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / fpevent|
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1.1 root 1: 1 00000000 # 1 ""
2: 1 00000000
3: 2 00000000
4: 3 00000000
5: 4 00000000
6: 5 00000000
7: 6 00000000 .set SBR,0
8: 7 00000000 .set SLR,1
9: 8 00000000 .set P0BR,2
10: 9 00000000 .set P0LR,3
11: 10 00000000 .set P1BR,4
12: 11 00000000 .set P1LR,5
13: 12 00000000 .set P2BR,6
14: 13 00000000 .set P2LR,7
15: 14 00000000 .set IPL,8
16: 15 00000000 .set MME,9
17: 16 00000000 .set TBIA,10
18: 17 00000000
19: 18 00000000 .set TBIS,11
20: 19 00000000
21: 20 00000000 .set DCK,12
22: 21 00000000 .set CCK,13
23: 22 00000000 .set PCBB,14
24: 23 00000000 .set ISP,15
25: 24 00000000 .set SIRR,16
26: 25 00000000 .set SISR,17
27: 26 00000000 .set SCBB,18
28: 27 00000000 .set KSP,19
29: 28 00000000 .set USP,20
30: 29 00000000 .set DCB,21
31: 30 00000000 .set PACC,23
32: 31 00000000
33: 32 00000000 .set P1DC,24
34: 33 00000000 .set PADC,25
35: 34 00000000
36: 35 00000000 .set HISR,26
37: 36 00000000 .set DCR,27
38: 37 00000000 .set PDCS,28
39: 38 00000000
40: 39 00000000
41: 40 00000000 #TAHOE program status longword
42: 41 00000000
43: 42 00000000
44: 43 00000000 .set PSL_C,0x00000001
45: 44 00000000 .set PSL_V,0x00000002
46: 45 00000000 .set PSL_Z,0x00000004
47: 46 00000000 .set Z,0x00000004
48: 47 00000000 .set PSL_N,0x00000008
49: 48 00000000 .set PSL_T,0x00000010
50: 49 00000000 .set PSL_I,0x00000020
51: 50 00000000 .set PSL_EN_OVFL,0x20
52: 51 00000000 .set PSL_EN_UNDFL,0x40
53: 52 00000000 .set PSL_DBL,0x80
54: 53 00000000 .set PSL_IPL,0x001f0000
55: 54 00000000 .set PSL_MOD,0x01000000
56: 55 00000000 .set PSL_IS,0x04000000
57: 56 00000000 .set PSL_TP,0x40000000
58: 57 00000000
59: 58 00000000
60: 59 00000000 # TAHOE page table entry
61: 60 00000000 #/
62: 61 00000000 .set PG_V,0x8000000
63: 62 00000000 .set PG_PROT,0x78000000
64: 63 00000000 .set PG_M,0x04000000
65: 64 00000000 .set PG_USED,0x02000000
66: 65 00000000 .set PG_NC,0x01000000
67: 66 00000000 .set PG_PFNUM,0x003fffff
68: 67 00000000
69: 68 00000000 .set PG_NOACC,0
70: 69 00000000 .set PG_KR,0x40000000
71: 70 00000000 .set PG_KW,0x60000000
72: 71 00000000 .set PG_URKR,0x50000000
73: 72 00000000 .set PG_URKW,0x70000000
74: 73 00000000 .set PG_UW,0x78000000
75: 74 00000000
76: 75 00000000 #* PCB offsets & diagnostic extension to pcb */
77: 76 00000000 #* PCB is at pcb0 */
78: 77 00000000
79: 78 00000000
80: 79 00000000 .set PCB_SIZE, 24
81: 80 00000000 .set PCB_KSP, 0
82: 81 00000000 .set PCB_USP, 4
83: 82 00000000 .set PCB_R0, 8
84: 83 00000000 .set PCB_R1, 12
85: 84 00000000 .set PCB_R2, 16
86: 85 00000000 .set PCB_R3, 20
87: 86 00000000 .set PCB_R4, 24
88: 87 00000000 .set PCB_R5, 28
89: 88 00000000 .set PCB_R6, 32
90: 89 00000000 .set PCB_R7, 36
91: 90 00000000 .set PCB_R8, 40
92: 91 00000000 .set PCB_R9, 44
93: 92 00000000 .set PCB_R10, 48
94: 93 00000000 .set PCB_R11, 52
95: 94 00000000 .set PCB_R12, 56
96: 95 00000000 .set PCB_R13, 60
97: 96 00000000 .set PCB_PC, 64
98: 97 00000000 .set PCB_PSL, 68
99: 98 00000000 .set PCB_P0BR, 72
100: 99 00000000 .set PCB_P0LR, 76
101: 100 00000000 .set PCB_P1BR, 80
102: 101 00000000 .set PCB_P1LR, 84
103: 102 00000000 .set PCB_P2BR, 88
104: 103 00000000 .set PCB_P2LR, 92
105: 104 00000000 .set PCB_ACCM, 96
106: 105 00000000 .set PCB_ACCL, 100
107: 106 00000000 #*
108: 107 00000000 # Diagnostic pcb extension
109: 108 00000000 #/
110: 109 00000000 .set PCB_STAT, 104
111: 110 00000000
112: 111 00000000
113: 112 00000000
114: 113 00000000 #* fundamental constants */
115: 114 00000000
116: 115 00000000 #*
117: 116 00000000 # fundamental constants of the implementation--
118: 117 00000000 # cannot be changed easily.
119: 118 00000000 #/
120: 119 00000000
121: 120 00000000 .set NBPG,1024
122: 121 00000000 .set PGOFSET,(NBPG-1)
123: 122 00000000 .set PGSHIFT,10
124: 123 00000000 .set HIGH,0x1f
125: 124 00000000
126: 125 00000000
127: 126 00000000 #* SCB offsets */
128: 127 00000000 #* SCB is at scb */
129: 128 00000000
130: 129 00000000 .set PFVEC,1*4
131: 130 00000000 .set PRVEC,2*4
132: 131 00000000 .set CLOCKVEC,7*4
133: 132 00000000 .set CRVEC,0xa*4
134: 133 00000000 .set CXVEC,44
135: 134 00000000 .set SIVEC1,0x1e*4
136: 135 00000000
137: 136 00000000
138: 137 00000000 .set BEVEC,0x20*4
139: 138 00000000 .set SYSVEC,0x2b*4
140: 139 00000000 .set PINSTVEC,0x2c*4
141: 140 00000000 .set PRIVSVEC,0x2c*4
142: 141 00000000 .set ROVEC,0x2d*4
143: 142 00000000 .set RAVEC,0x2e*4
144: 143 00000000 .set PROTVEC,0x2f*4
145: 144 00000000 .set TRANS,0x30
146: 145 00000000 .set TRANSVEC,0x30*4
147: 146 00000000 .set KSPVEC,0x31*4
148: 147 00000000 .set TRACEVEC,0x32*4
149: 148 00000000 .set BPTVEC,0x33*4
150: 149 00000000 .set ARITHVEC,0x34*4
151: 150 00000000 .set ALIGNVEC,0x35*4
152: 151 00000000 .set FPMVEC,0x37*4
153: 152 00000000 .set IO14VEC,256
154: 153 00000000 .set IO15VEC,320
155: 154 00000000 .set IO16VEC,384
156: 155 00000000 .set IO17VEC,448
157: 156 00000000
158: 157 00000000 #* SPT (system page table) offsets */
159: 158 00000000 #* SPT is at Sysmap */
160: 159 00000000
161: 160 00000000 .set SCBPTE,8
162: 161 00000000 .set BUFPTE,12
163: 162 00000000 .set ISPTE,16
164: 163 00000000 .set IS1PTE,20
165: 164 00000000 .set SPTPTE,20
166: 165 00000000 .set SPT1PTE,20
167: 166 00000000 .set IOMAPPTE,24
168: 167 00000000 .set PCBPTE,28
169: 168 00000000 .set U0P0PTE,32
170: 169 00000000 .set U0P1PTE,36
171: 170 00000000 .set U0P2PTE,40
172: 171 00000000 .set U1P0PTE,44
173: 172 00000000 .set U1P1PTE,48
174: 173 00000000 .set U1P2PTE,52
175: 174 00000000 .set U2P0PTE,56
176: 175 00000000 .set U2P1PTE,60
177: 176 00000000 .set U2P2PTE,64
178: 177 00000000 .set U3P0PTE,68
179: 178 00000000 .set U3P1PTE,72
180: 179 00000000 .set U3P2PTE,76
181: 180 00000000 .set U4P0PTE,80
182: 181 00000000 .set U4P1PTE,84
183: 182 00000000 .set U4P2PTE,88
184: 183 00000000 .set U5P0PTE,92
185: 184 00000000 .set U5P1PTE,96
186: 185 00000000 .set U5P2PTE,100
187: 186 00000000 .set U6P0PTE,104
188: 187 00000000 .set U6P1PTE,108
189: 188 00000000 .set U6P2PTE,112
190: 189 00000000 .set U7P0PTE,116
191: 190 00000000 .set U7P1PTE,120
192: 191 00000000 .set U7P2PTE,124
193: 192 00000000 .set IOB0PTE,128
194: 193 00000000 .set IOB1PTE,132
195: 194 00000000 .set IOB2PTE,136
196: 195 00000000 .set IOB3PTE,140
197: 196 00000000 .set IOB4PTE,144
198: 197 00000000 .set IOB5PTE,148
199: 198 00000000 .set IOB6PTE,152
200: 199 00000000 .set IOB7PTE,156
201: 200 00000000
202: 201 00000000
203: 202 00000000 #* trap.h 4.6 81/03/03 */
204: 203 00000000
205: 204 00000000 #*
206: 205 00000000 #* Trap type values
207: 206 00000000 #/
208: 207 00000000
209: 208 00000000 .set RESADFLT,0
210: 209 00000000 .set PRIVINFLT,1
211: 210 00000000 .set RESOPFLT,2
212: 211 00000000 .set BPTFLT,3
213: 212 00000000 .set ALIGNFLT,4
214: 213 00000000 .set SYSCALL,5
215: 214 00000000 .set ARITHTRAP,6
216: 215 00000000 .set PROTFLT,7
217: 216 00000000 .set TRCTRAP,8
218: 217 00000000 .set TRANSFLT,9
219: 218 00000000 .set DONE,255
220: 219 00000000
221: 220 00000000
222: 221 00000000 # Event codes
223: 222 00000000
224: 223 00000000 .set RTCLOCK_CODE,7
225: 224 00000000 .set RESOP_CODE,0x2d
226: 225 00000000 .set RESAD_CODE,0x2e
227: 226 00000000 .set ARITH_CODE,0x34
228: 227 00000000 .set FPM_CODE,0x37
229: 228 00000000 .set INTEGER_OVERFLOW,1
230: 229 00000000
231: 230 00000000
232: 231 00000000 # Arithmetic Event types
233: 232 00000000
234: 233 00000000 .set INT_OVFL_CODE,1
235: 234 00000000 .set INT_0_DIV_CODE,2
236: 235 00000000 .set FLT_0_DIV_CODE,3
237: 236 00000000 .set FLT_OVFL_CODE,4
238: 237 00000000 .set FLT_UNDFL_CODE,5
239: 238 00000000
240: 239 00000000
241: 240 00000000 # Floating Point Instruction Op-Codes
242: 241 00000000
243: 242 00000000 .set LDF_OP_CODE,0x06
244: 243 00000000 .set LDD_OP_CODE,0x07
245: 244 00000000 .set LNF_OP_CODE,0x16
246: 245 00000000 .set LND_OP_CODE,0x17
247: 246 00000000 .set STF_OP_CODE,0x26
248: 247 00000000 .set STD_OP_CODE,0x27
249: 248 00000000 .set CMPF_OP_CODE,0x36
250: 249 00000000 .set CMPD_OP_CODE,0x37
251: 250 00000000 .set CMPF2_OP_CODE,0x46
252: 251 00000000 .set CMPD2_OP_CODE,0x47
253: 252 00000000 .set TSTF_OP_CODE,0x56
254: 253 00000000 .set TSTD_OP_CODE,0x57
255: 254 00000000 .set PUSHD_OP_CODE,0x67
256: 255 00000000 .set CVLF_OP_CODE,0x76
257: 256 00000000 .set CVLD_OP_CODE,0x77
258: 257 00000000 .set CVFL_OP_CODE,0x86
259: 258 00000000 .set CVDL_OP_CODE,0x87
260: 259 00000000 .set LDFD_OP_CODE,0x97
261: 260 00000000 .set CVDF_OP_CODE,0xa6
262: 261 00000000 .set NEGF_OP_CODE,0xb6
263: 262 00000000 .set NEGD_OP_CODE,0xb7
264: 263 00000000 .set ADDF_OP_CODE,0xc6
265: 264 00000000 .set ADDD_OP_CODE,0xc7
266: 265 00000000 .set SUBF_OP_CODE,0xd6
267: 266 00000000 .set SUBD_OP_CODE,0xd7
268: 267 00000000 .set MULF_OP_CODE,0xe6
269: 268 00000000 .set MULD_OP_CODE,0xe7
270: 269 00000000 .set DIVF_OP_CODE,0xf6
271: 270 00000000 .set DIVD_OP_CODE,0xf7
272: 271 00000000 .set SINF_OP_CODE,0x05
273: 272 00000000 .set COSF_OP_CODE,0x15
274: 273 00000000 .set ATANF_OP_CODE,0x25
275: 274 00000000 .set LOGF_OP_CODE,0x35
276: 275 00000000 .set SQRTF_OP_CODE,0x45
277: 276 00000000 .set EXPF_OP_CODE,0x55
278: 277 00000000 .set MULL2_OP_CODE,0x4c
279: 278 00000000 .set MULL3_OP_CODE,0x5c
280: 279 00000000
281: 280 00000000
282: 281 00000000
283: 282 00000000 # Addressing test constants - These must agree with "fpp_defs.h"
284: 283 00000000
285: 284 00000000 .set ADR_ABSOLUTE,1
286: 285 00000000 .set ADR_LITERAL,2
287: 286 00000000 .set ADR_IM_B,3
288: 287 00000000 .set ADR_IM_W,4
289: 288 00000000 .set ADR_IM_L,5
290: 289 00000000 .set ADR_B_DSP,6
291: 290 00000000 .set ADR_W_DSP,7
292: 291 00000000 .set ADR_L_DSP,8
293: 292 00000000 .set ADR_B_DSP_DEF,9
294: 293 00000000 .set ADR_W_DSP_DEF,10
295: 294 00000000 .set ADR_L_DSP_DEF,11
296: 295 00000000 .set ADR_REG,12
297: 296 00000000 .set ADR_REG_DEF,13
298: 297 00000000 .set ADR_FP_DEF,14
299: 298 00000000 .set ADR_SP_DEF,15
300: 299 00000000 .set ADR_PUSH,16
301: 300 00000000 .set ADR_POP,17
302: 301 00000000 .set ADR_POP_DEF,18
303: 302 00000000 .set ADR_REG_B,19
304: 303 00000000 .set ADR_REG_W,20
305: 304 00000000 .set ADR_REG_L,21
306: 305 00000000 .set ADR_REG_B_DEF,22
307: 306 00000000 .set ADR_REG_W_DEF,23
308: 307 00000000 .set ADR_REG_L_DEF,24
309: 308 00000000 .set ADR_I_FP_DEF,25
310: 309 00000000 .set ADR_I_L,26
311: 310 00000000
312: 311 00000000
313: 312 00000000 #*************************************************************************
314: 313 00000000
315: 314 00000000 # Stuff for the Demand Paging , Events, & Addressing Tests
316: 315 00000000
317: 316 00000000 #************************************************************************/
318: 317 00000000 .set SGL,1
319: 318 00000000 .set DBL,2
320: 319 00000000 .set ENABLE_EVENTS,0x60
321: 320 00000000 .set NONE,0
322: 321 00000000 .set LOAD,1
323: 322 00000000 .set STORE,2
324: 323 00000000
325: 324 00000000 .set NO_EVT_HLT,1
326: 325 00000000 .set EVT_MSK_HLT,2
327: 326 00000000 .set BAD_PSL_HLT,3
328: 327 00000000 .set PUSH_CNT_HLT,4
329: 328 00000000 .set PUSH_PSL_HLT,5
330: 329 00000000 .set PUSH_PC_HLT,6
331: 330 00000000 .set BAD_REG_HLT,7
332: 331 00000000 .set BAD_ACC_HLT,8
333: 332 00000000
334: 333 00000000
335: 334 00000000 # set DMP_PG_0 to the 1st empty page
336: 335 00000000
337: 336 00000000 .set DMP_PG_0,0x36000
338: 337 00000000 .set DMP_PG_1,DMP_PG_0+0x400
339: 338 00000000 .set DMP_PG_2,DMP_PG_1+0x400
340: 339 00000000 .set DMP_PG_3,DMP_PG_2+0x400
341: 340 00000000 .set DMP_PG_4,DMP_PG_3+0x400
342: 341 00000000 .set DMP_PG_5,DMP_PG_4+0x400
343: 342 00000000 .set DMP_PG_6,DMP_PG_5+0x400
344: 343 00000000 .set DMP_PG_7,DMP_PG_6+0x400
345: 344 00000000 .set DMP_PG_8,DMP_PG_7+0x400
346: 345 00000000 .set DMP_PG_9,DMP_PG_8+0x400
347: 346 00000000 .set DMP_PG_10,DMP_PG_9+0x400
348: 347 00000000 .set DMP_PG_11,DMP_PG_10+0x400
349: 348 00000000 .set DMP_PG_12,DMP_PG_11+0x400
350: 349 00000000 .set DMP_PG_13,DMP_PG_12+0x400
351: 350 00000000
352: 351 00000000
353: 352 00000000 # test code space for the address / demand page tests
354: 353 00000000
355: 354 00000000 .set START_OF_CODE,DMP_PG_1-20
356: 355 00000000 .set CODE_BUF_SIZE,40
357: 356 00000000 .set END_OF_CODE,START_OF_CODE+CODE_BUF_SIZE
358: 357 00000000
359: 358 00000000
360: 359 00000000 # data locations used by the event and demand page tests
361: 360 00000000
362: 361 00000000 .set _dmp_byte_op_1,DMP_PG_1+0x30
363: 362 00000000 .set _dmp_byte_op_2,DMP_PG_1+0x50
364: 363 00000000 .set _dmp_byte_op_3,DMP_PG_1+0x70
365: 364 00000000 .set _dmp_op_1,DMP_PG_3-4
366: 365 00000000 .set _dmp_op_1_ptr,DMP_PG_4+0x30
367: 366 00000000 .set _dmp_op_2_ptr,DMP_PG_5+0x30
368: 367 00000000 .set _dmp_op_2,DMP_PG_7-4
369: 368 00000000 .set _dmp_op_3,DMP_PG_8
370: 369 00000000 .set _dmp_op_3_ptr,DMP_PG_9+0x30
371: 370 00000000 .set _dmp_op_4,DMP_PG_10
372: 371 00000000 .set _dmp_op_5,DMP_PG_11
373: 372 00000000 .set _sp_minus,DMP_PG_13-4
374: 373 00000000 .set _sp_page,DMP_PG_13
375: 374 00000000 .set _sp_plus,DMP_PG_13+4
376: 375 00000000
377: 376 00000000
378: 377 00000000
379: 378 00000000
380: 379 00000000
381: 380 00000000
382: 381 00000000
383: 382 00000000
384: 383 00000000
385: 384 00000000
386: 385 00000000
387: 386 00000000 # INIT.X for the FPP Events Tests
388: 387 00000000
389: 388 00000000 # This file is a diagnostic version of locore.s.
390: 389 00000000 # It contains the following:
391: 390 00000000 # *system data area = scb, dump buffer, interrupt stack,
392: 391 00000000 # *system page table,user page tables,pcbs,iomap, & io buffers.
393: 392 00000000 #
394: 393 00000000 # *system code = interrupt vectors, initialization of system data,
395: 394 00000000 # *memory size calculation,initialization of SPT, zeroing of
396: 395 00000000 # *unused memory, & loading of SBR & SLR.
397: 396 00000000 # *
398: 397 00000000 # *at the end of this code, you are ready to go to virtual mode.
399: 398 00000000 # * --- GOOD LUCK!
400: 399 00000000
401: 400 00000000 ##########################################################################
402: 401 00000000
403: 402 00000000 # 22-Mar-85 : Stole the code from the Demand Paging Test directory
404: 403 00000000 # 16-Jul-85 : Added the test for the FPP WCS / NO-FPP WCS
405: 404 00000000
406: 405 00000000 ##########################################################################
407: 406 00000000
408: 407 00000000
409: 408 00000000
410: 409 00000000
411: 410 00000000 # 1 "./prvreg.h"
412: 1 00000000
413: 2 00000000
414: 3 00000000
415: 4 00000000
416: 5 00000000
417: 6 00000000
418: 7 00000000
419: 8 00000000 .set SBR,0
420: 9 00000000 .set SLR,1
421: 10 00000000 .set P0BR,2
422: 11 00000000 .set P0LR,3
423: 12 00000000 .set P1BR,4
424: 13 00000000 .set P1LR,5
425: 14 00000000 .set P2BR,6
426: 15 00000000 .set P2LR,7
427: 16 00000000 .set IPL,8
428: 17 00000000 .set MME,9
429: 18 00000000 .set TBIA,10
430: 19 00000000
431: 20 00000000 .set TBIS,11
432: 21 00000000
433: 22 00000000 .set DCK,12
434: 23 00000000 .set CCK,13
435: 24 00000000
436: 25 00000000
437: 26 00000000 .set PCBB,14
438: 27 00000000 .set ISP,15
439: 28 00000000 .set SIRR,16
440: 29 00000000 .set SISR,17
441: 30 00000000 .set SCBB,18
442: 31 00000000 .set KSP,19
443: 32 00000000 .set USP,20
444: 33 00000000 .set DCB,21
445: 34 00000000 .set PACC,23
446: 35 00000000
447: 36 00000000 .set P1DC,24
448: 37 00000000 .set PADC,25
449: 38 00000000
450: 39 00000000 .set HISR,26
451: 40 00000000 .set DCR,27
452: 41 00000000 .set PDCS,28
453: 42 00000000 # 410 ""
454: 410 00000000
455: 411 00000000
456: 412 00000000
457: 413 00000000 # 1 "./psl.h"
458: 1 00000000
459: 2 00000000
460: 3 00000000
461: 4 00000000
462: 5 00000000
463: 6 00000000
464: 7 00000000
465: 8 00000000
466: 9 00000000
467: 10 00000000
468: 11 00000000
469: 12 00000000
470: 13 00000000
471: 14 00000000
472: 15 00000000
473: 16 00000000
474: 17 00000000
475: 18 00000000
476: 19 00000000
477: 20 00000000
478: 21 00000000
479: 22 00000000
480: 23 00000000
481: 24 00000000
482: 25 00000000
483: 26 00000000 # 413 ""
484: 413 00000000
485: 414 00000000
486: 415 00000000
487: 416 00000000 # 1 "./pte.h"
488: 1 00000000
489: 2 00000000
490: 3 00000000
491: 4 00000000
492: 5 00000000
493: 6 00000000
494: 7 00000000
495: 8 00000000
496: 9 00000000
497: 10 00000000
498: 11 00000000
499: 12 00000000
500: 13 00000000
501: 14 00000000
502: 15 00000000
503: 16 00000000
504: 17 00000000
505: 18 00000000
506: 19 00000000
507: 20 00000000
508: 21 00000000
509: 22 00000000
510: 23 00000000
511: 24 00000000
512: 25 00000000
513: 26 00000000
514: 27 00000000
515: 28 00000000
516: 29 00000000
517: 30 00000000 # 416 ""
518: 416 00000000
519: 417 00000000
520: 418 00000000
521: 419 00000000 # 1 "./pcboffset.h"
522: 1 00000000
523: 2 00000000
524: 3 00000000
525: 4 00000000
526: 5 00000000
527: 6 00000000 .set PCB_KSP, 0
528: 7 00000000 .set PCB_USP, 4
529: 8 00000000 .set PCB_R0, 8
530: 9 00000000 .set PCB_R1, 12
531: 10 00000000 .set PCB_R2, 16
532: 11 00000000 .set PCB_R3, 20
533: 12 00000000 .set PCB_R4, 24
534: 13 00000000 .set PCB_R5, 28
535: 14 00000000 .set PCB_R6, 32
536: 15 00000000 .set PCB_R7, 36
537: 16 00000000 .set PCB_R8, 40
538: 17 00000000 .set PCB_R9, 44
539: 18 00000000 .set PCB_R10, 48
540: 19 00000000 .set PCB_R11, 52
541: 20 00000000 .set PCB_R12, 56
542: 21 00000000 .set PCB_R13, 60
543: 22 00000000 .set PCB_PC, 64
544: 23 00000000 .set PCB_PSL, 68
545: 24 00000000 .set PCB_P0BR, 72
546: 25 00000000 .set PCB_P0LR, 76
547: 26 00000000 .set PCB_P1BR, 80
548: 27 00000000 .set PCB_P1LR, 84
549: 28 00000000 .set PCB_P2BR, 88
550: 29 00000000 .set PCB_P2LR, 92
551: 30 00000000
552: 31 00000000
553: 32 00000000
554: 33 00000000 .set PCB_STAT, 96
555: 34 00000000
556: 35 00000000
557: 36 00000000 # 419 ""
558: 419 00000000
559: 420 00000000
560: 421 00000000
561: 422 00000000 # 1 "./const.h"
562: 1 00000000
563: 2 00000000
564: 3 00000000
565: 4 00000000
566: 5 00000000
567: 6 00000000
568: 7 00000000
569: 8 00000000
570: 9 00000000
571: 10 00000000
572: 11 00000000
573: 12 00000000
574: 13 00000000
575: 14 00000000
576: 15 00000000
577: 16 00000000
578: 17 00000000
579: 18 00000000
580: 19 00000000
581: 20 00000000
582: 21 00000000
583: 22 00000000
584: 23 00000000
585: 24 00000000
586: 25 00000000
587: 26 00000000
588: 27 00000000
589: 28 00000000
590: 29 00000000
591: 30 00000000
592: 31 00000000
593: 32 00000000
594: 33 00000000
595: 34 00000000
596: 35 00000000
597: 36 00000000
598: 37 00000000
599: 38 00000000
600: 39 00000000
601: 40 00000000
602: 41 00000000
603: 42 00000000
604: 43 00000000
605: 44 00000000
606: 45 00000000
607: 46 00000000
608: 47 00000000
609: 48 00000000
610: 49 00000000
611: 50 00000000
612: 51 00000000 # 422 ""
613: 422 00000000
614: 423 00000000
615: 424 00000000
616: 425 00000000 # 1 "./scboffset.h"
617: 1 00000000
618: 2 00000000
619: 3 00000000
620: 4 00000000
621: 5 00000000 .set PFVEC,4
622: 6 00000000 .set CLOCKVEC,28
623: 7 00000000 .set CRVEC,40
624: 8 00000000 .set CXVEC,44
625: 9 00000000 .set SIVEC1,120
626: 10 00000000
627: 11 00000000
628: 12 00000000 .set BEVEC,128
629: 13 00000000 .set SYSVEC,172
630: 14 00000000 .set PINSTVEC,176
631: 15 00000000 .set ROVEC,180
632: 16 00000000 .set RAVEC,184
633: 17 00000000 .set PROTVEC,188
634: 18 00000000
635: 19 00000000 .set TRANS,0x30
636: 20 00000000 .set TRANSVEC,192
637: 21 00000000
638: 22 00000000 .set KSPVEC,196
639: 23 00000000 .set TRACEVEC,200
640: 24 00000000 .set BPTVEC,204
641: 25 00000000 .set ARITHVEC,208
642: 26 00000000 .set ALIGNVEC,212
643: 27 00000000 .set FPMVEC,220
644: 28 00000000 .set IO14VEC,256
645: 29 00000000 .set IO15VEC,320
646: 30 00000000 .set IO16VEC,384
647: 31 00000000 .set IO17VEC,448
648: 32 00000000
649: 33 00000000 # 425 ""
650: 425 00000000
651: 426 00000000
652: 427 00000000 # 1 "./sptoffset.h"
653: 1 00000000
654: 2 00000000
655: 3 00000000
656: 4 00000000
657: 5 00000000
658: 6 00000000
659: 7 00000000
660: 8 00000000
661: 9 00000000 .set SCBPTE,8
662: 10 00000000 .set BUFPTE,12
663: 11 00000000 .set ISPTE,16
664: 12 00000000 .set IS1PTE,20
665: 13 00000000 .set SPTPTE,20
666: 14 00000000 .set SPT1PTE,20
667: 15 00000000 .set IOMAPPTE,24
668: 16 00000000 .set PCBPTE,28
669: 17 00000000 .set U0P0PTE,32
670: 18 00000000 .set U0P1PTE,36
671: 19 00000000 .set U0P2PTE,40
672: 20 00000000 .set U1P0PTE,44
673: 21 00000000 .set U1P1PTE,48
674: 22 00000000 .set U1P2PTE,52
675: 23 00000000 .set U2P0PTE,56
676: 24 00000000 .set U2P1PTE,60
677: 25 00000000 .set U2P2PTE,64
678: 26 00000000 .set U3P0PTE,68
679: 27 00000000 .set U3P1PTE,72
680: 28 00000000 .set U3P2PTE,76
681: 29 00000000 .set U4P0PTE,80
682: 30 00000000 .set U4P1PTE,84
683: 31 00000000 .set U4P2PTE,88
684: 32 00000000 .set U5P0PTE,92
685: 33 00000000 .set U5P1PTE,96
686: 34 00000000 .set U5P2PTE,100
687: 35 00000000 .set U6P0PTE,104
688: 36 00000000 .set U6P1PTE,108
689: 37 00000000 .set U6P2PTE,112
690: 38 00000000 .set U7P0PTE,116
691: 39 00000000 .set U7P1PTE,120
692: 40 00000000 .set U7P2PTE,124
693: 41 00000000 .set IOB0PTE,128
694: 42 00000000 .set IOB1PTE,132
695: 43 00000000 .set IOB2PTE,136
696: 44 00000000 .set IOB3PTE,140
697: 45 00000000 .set IOB4PTE,144
698: 46 00000000 .set IOB5PTE,148
699: 47 00000000 .set IOB6PTE,152
700: 48 00000000 .set IOB7PTE,156
701: 49 00000000
702: 50 00000000
703: 51 00000000 # 427 ""
704: 427 00000000
705: 428 00000000
706: 429 00000000
707: 430 00000000 # 1 "./trap.h"
708: 1 00000000
709: 2 00000000
710: 3 00000000
711: 4 00000000
712: 5 00000000
713: 6 00000000
714: 7 00000000
715: 8 00000000
716: 9 00000000
717: 10 00000000
718: 11 00000000
719: 12 00000000
720: 13 00000000
721: 14 00000000
722: 15 00000000
723: 16 00000000
724: 17 00000000 # 430 ""
725: 430 00000000
726: 431 00000000
727: 432 00000000
728: 433 00000000
729: 434 00000000
730: 435 00000000 .set HIGH,0x1f
731: 436 00000000 .set MCKVEC,4
732: 437 00000000 .set NISP,2
733: 438 00000000 .set DONE,255
734: 439 00000000 .set TTRAP,0x32
735: 440 00000000 .set TRANS,0x30
736: 441 00000000 .set PRIVS,0x2c
737: 442 00000000
738: 443 00000000 .text
739: 444 00000000
740: 445 00000000
741: 446 00000000
742: 447 00000000 # 1 "./pstorage.s"
743: 1 00000000 #
744: 2 00000000
745: 3 00000000
746: 4 00000000
747: 5 00000000
748: 6 00000000
749: 7 00000000
750: 8 00000000
751: 9 00000000
752: 10 00000000
753: 11 00000000
754: 12 00000000
755: 13 00000000
756: 14 00000000
757: 15 00000000
758: 16 00000000
759: 17 00000000
760: 18 00000000
761: 19 00000000
762: 20 00000000 _pstore:
763: 21 00000000 .globl _pstore
764: 22 00000000 **** .space 1024
765: 23 00000400
766: 24 00000400 _pstore1:
767: 25 00000400 .globl _pstore1
768: 26 00000400
769: 27 00000400 **** _pcbb: .space 4
770: 28 00000404 .globl _isp
771: 29 00000404 **** _isp: .space 4
772: 30 00000408 **** _sirr: .space 4
773: 31 0000040C .globl _sisr
774: 32 0000040C **** _sisr: .space 4
775: 33 00000410
776: 34 00000410 **** .space 4
777: 35 00000414 **** .space 4
778: 36 00000418 **** .space 4
779: 37 0000041C
780: 38 0000041C **** _cpmdcb: .space 4
781: 39 00000420 **** _cpfdcb: .space 4
782: 40 00000424 **** _cpcdcb: .space 4
783: 41 00000428 **** _cpidcb: .space 4
784: 42 0000042C **** _cpstat: .space 4
785: 43 00000430 **** _cpctl: .space 4
786: 44 00000434
787: 45 00000434 .globl _hisr
788: 46 00000434 **** _hisr: .space 4
789: 47 00000438 **** _dcr: .space 4
790: 48 0000043C
791: 49 0000043C **** .space 4*48
792: 50 000004FC
793: 51 000004FC _pstemp:
794: 52 000004FC .globl _pstemp
795: 53 000004FC
796: 54 000004FC **** _tr0: .space 16
797: 55 0000050C
798: 56 0000050C **** _tpc: .space 4
799: 57 00000510 **** _tpsl: .space 4
800: 58 00000514 **** _tsp: .space 4
801: 59 00000518 **** _tksp: .space 4
802: 60 0000051C **** _tusp: .space 4
803: 61 00000520 **** _tcck: .space 4
804: 62 00000524 **** _tdck: .space 4
805: 63 00000528 **** _ttbk: .space 4
806: 64 0000052C **** _tsbr: .space 4
807: 65 00000530 **** _tslr: .space 4
808: 66 00000534 **** _tp0br: .space 4
809: 67 00000538 **** _tp0lr: .space 4
810: 68 0000053C **** _tp1br: .space 4
811: 69 00000540 **** _tp1lr: .space 4
812: 70 00000544 **** _tp2br: .space 4
813: 71 00000548 **** _tp2lr: .space 4
814: 72 0000054C **** _tipl: .space 4
815: 73 00000550 **** _tmme: .space 4
816: 74 00000554 **** _ttbia: .space 4
817: 75 00000558 **** _ttbis: .space 4
818: 76 0000055C
819: 77 0000055C
820: 78 0000055C **** _tpcbb: .space 4
821: 79 00000560 **** _tisp: .space 4
822: 80 00000564 **** _tsirr: .space 4
823: 81 00000568 **** _tsisr: .space 4
824: 82 0000056C **** _tscbb: .space 4
825: 83 00000570 **** _tp1cc: .space 4
826: 84 00000574
827: 85 00000574 **** _tpacc: .space 4
828: 86 00000578
829: 87 00000578 **** _tp1dc: .space 4
830: 88 0000057C **** _tpadc: .space 4
831: 89 00000580 _tcpmdcb:
832: 90 00000580 **** .space 4
833: 91 00000584 _tcpfdcb:
834: 92 00000584 **** .space 4
835: 93 00000588 _tcpcdcb:
836: 94 00000588 **** .space 4
837: 95 0000058C _tcpidcb:
838: 96 0000058C **** .space 4
839: 97 00000590 _tcpstat:
840: 98 00000590 **** .space 4
841: 99 00000594 _tcpctl:
842: 100 00000594 **** .space 4
843: 101 00000598
844: 102 00000598 _probflag:
845: 103 00000598 **** .space 4
846: 104 0000059C _inexcflg:
847: 105 0000059C **** .space 4
848: 106 000005A0
849: 107 000005A0 **** .space 4*10
850: 108 000005C8 _psend: .globl _psend
851: 109 000005C8 .set MM,(_psend - _pstore1)
852: 110 000005C8 **** .space 1024 - MM
853: 111 00000800
854: 112 00000800
855: 113 00000800 #
856: 114 00000800
857: 115 00000800
858: 116 00000800
859: 117 00000800
860: 118 00000800
861: 119 00000800 .set PCBB,0x400 #process control block base
862: 120 00000800
863: 121 00000800 .globl INTSP
864: 122 00000800 .set INTSP,0x404 #Interrupt stack pointer
865: 123 00000800 .set SIRR,0x408 #Software interrupt request
866: 124 00000800
867: 125 00000800 .globl SSR
868: 126 00000800 .set SSR,0x40C #Software interrupt summary
869: 127 00000800
870: 128 00000800 .globl HSR
871: 129 00000800 .set HSR,0x410 #Hardware interrupt summary
872: 130 00000800
873: 131 00000800 .set SBB,0x414 #Pointer to system control block base
874: 132 00000800 .set TBCR,0x418 #Current value of hardware TBCR
875: 133 00000800 .set CPMDCB,0x420 #pointer to CP master DCB
876: 134 00000800 .set CPCTL,0x424 #CPU control word
877: 135 00000800 .set CPREQ,0x428 #CPU request
878: 136 00000800 .set CPRUN,0x42C #CPU run status (8 = step mode)
879: 137 00000800 .set CPRSW,0x430 #CP interrupt request word
880: 138 00000800 .set PSL,0x434 #Software Process Status Longword
881: 139 00000800 .set TVAPR,0x5E8 #saved vapr register
882: 140 00000800 .set TRA,0x5EC #
883: 141 00000800 .set TLSP,0x5F0 #
884: 142 00000800 .set TIAR,0x5F4 #
885: 143 00000800 .set TLIA,0x5F8 #
886: 144 00000800 .set TQ,0x5FC #
887: 145 00000800 .set TR0,0x600 #decellerated processor registers
888: 146 00000800 .set TR1,0x604 #decellerated processor registers
889: 147 00000800 .set TR2,0x608 #decellerated processor registers
890: 148 00000800 .set TR3,0x60C #decellerated processor registers
891: 149 00000800 .set TR4,0x610 #decellerated processor registers
892: 150 00000800 .set TR5,0x614 #decellerated processor registers
893: 151 00000800 .set TR6,0x618 #decellerated processor registers
894: 152 00000800 .set TR7,0x61C #decellerated processor registers
895: 153 00000800 .set TR8,0x620 #decellerated processor registers
896: 154 00000800 .set TR9,0x624 #decellerated processor registers
897: 155 00000800 .set TR10,0x628 #decellerated processor registers
898: 156 00000800 .set TR11,0x62C #decellerated processor registers
899: 157 00000800 .set TR12,0x630 #decellerated processor registers
900: 158 00000800 .set TR13,0x634 #decellerated processor registers
901: 159 00000800 .set TR14,0x638 #decellerated processor registers
902: 160 00000800 .set TR15,0x63C #decellerated processor registers
903: 161 00000800 .set TPC,0x640 #decellerated program counter
904: 162 00000800 .set TPSL,0x644 #decellerated process status longword
905: 163 00000800 .set TSP,0x648 #decellerated stack pointer
906: 164 00000800 .set TKSP,0x64C #decellerated kernel stack pointer
907: 165 00000800 .set TUSP,0x650 #decellerated user stack pointer
908: 166 00000800 .globl TCCK
909: 167 00000800 .set TCCK,0x654 #decellerated Code cache key
910: 168 00000800 .globl TDCK
911: 169 00000800 .set TDCK,0x658 #decellerated data cache key
912: 170 00000800 .set TTBK,0x65C #decellerated translation buffer key
913: 171 00000800 .set TSBR,0x660 #decellerated System Base Register
914: 172 00000800 .set TSLR,0x664 #decellerated System length register
915: 173 00000800 .set TP0BR,0x668 #decellerated P0 base register
916: 174 00000800 .set TP0LR,0x66C #decellerated P0 length register
917: 175 00000800 .set TP1BR,0x670 #decellerated P1 base register
918: 176 00000800 .set TP1LR,0x674 #decellerated P1 length register
919: 177 00000800 .set TP2BR,0x678 #decellerated P2 base register
920: 178 00000800 .set TP2LR,0x67C #decellerated P1 length register
921: 179 00000800 .set TIPL,0x680 #decellerated Interrupt priority level
922: 180 00000800 .set TMME,0x684 #decellerated Memory management enable
923: 181 00000800 .set TTBIA,0x68C #decellerated translation buffer invalid
924: 182 00000800 .set TTBIS,0x68C #decellerated transl buffer invalid single
925: 183 00000800 .set TPCBB,0x690 #decellerated Process control block base
926: 184 00000800 .set TISP,0x694 #decellerated Interrupt stack pointer
927: 185 00000800 .set TSIRR,0x698 #decellerated Software interrupt request
928: 186 00000800 .set TSISR,0x69C #decellerated Software interrupt summary
929: 187 00000800 .set TSCBB,0x6A0 #decellerated System control block base
930: 188 00000800 .set TP1CC,0x6A4 #decellerated
931: 189 00000800 .set TPACC,0x6A8 #decellerated
932: 190 00000800 .set TP1DC,0x6AC #decellerated
933: 191 00000800 .set TPADC,0x6B0 #decellerated
934: 192 00000800 .set TCPMDCB,0x6B4 #decellerated address of master DCB
935: 193 00000800 .set PROBFLG,0x6B8 #decellerated
936: 194 00000800 .set INEXCFLG,0x6BC #decellerated
937: 195 00000800 .set PCTYPFLG,0x6C0 #
938: 196 00000800 .set NOOFPARS,0x6C4 #
939: 197 00000800 .set STKPAR1,0x6C8 #
940: 198 00000800 .set STKPAR2,0x6CC #
941: 199 00000800 .set JMPVEC,0x6D0 #
942: 200 00000800 .set PSEND,0x7FC #
943: 201 00000800 # 447 ""
944: 447 00000800
945: 448 00000800 .globl _Entry
946: 449 00000800 _Entry:
947: 450 00000800 71 ef0000a34c jmp start
948: 451 00000806 **** .space (1024-6)
949: 452 00000C00
950: 453 00000C00
951: 454 00000C00
952: 455 00000C00
953: 456 00000C00
954: 457 00000C00
955: 458 00000C00
956: 459 00000C00 .set NLWU,35
957: 460 00000C00
958: 461 00000C00
959: 462 00000C00
960: 463 00000C00 .globl _Codek
961: 464 00000C00 00000000 _Codek: .long 0
962: 465 00000C04
963: 466 00000C04 .globl _restart
964: 467 00000C04 _restart:
965: 468 00000C04 **** .space 4
966: 469 00000C08
967: 470 00000C08
968: 471 00000C08
969: 472 00000C08 .globl _maxmem
970: 473 00000C08 _maxmem:
971: 474 00000C08 **** .space 4
972: 475 00000C0C
973: 476 00000C0C .globl _maxpages
974: 477 00000C0C _maxpages:
975: 478 00000C0C **** .space 4
976: 479 00000C10
977: 480 00000C10 .globl _lastadd
978: 481 00000C10 _lastadd:
979: 482 00000C10 **** .space 4
980: 483 00000C14
981: 484 00000C14 .globl _unused
982: 485 00000C14 _unused:
983: 486 00000C14 **** .space 4
984: 487 00000C18
985: 488 00000C18 .globl _ctlblk
986: 489 00000C18 _ctlblk:
987: 490 00000C18 00000000 .long 0
988: 491 00000C1C
989: 492 00000C1C .globl _savvec0
990: 493 00000C1C _savvec0:
991: 494 00000C1C **** .space 4
992: 495 00000C20
993: 496 00000C20 .globl _savvec1
994: 497 00000C20 _savvec1:
995: 498 00000C20 **** .space 4
996: 499 00000C24
997: 500 00000C24 .globl _savvec2
998: 501 00000C24 _savvec2:
999: 502 00000C24 **** .space 4
1000: 503 00000C28
1001: 504 00000C28 .globl _savvec3
1002: 505 00000C28 _savvec3:
1003: 506 00000C28 **** .space 4
1004: 507 00000C2C
1005: 508 00000C2C .globl _savvec4
1006: 509 00000C2C _savvec4:
1007: 510 00000C2C **** .space 4
1008: 511 00000C30
1009: 512 00000C30 .globl _savvec5
1010: 513 00000C30 _savvec5:
1011: 514 00000C30 **** .space 4
1012: 515 00000C34 .globl _savvec6
1013: 516 00000C34 _savvec6:
1014: 517 00000C34 **** .space 4
1015: 518 00000C38 .globl _savvec7
1016: 519 00000C38 _savvec7:
1017: 520 00000C38 **** .space 4
1018: 521 00000C3C
1019: 522 00000C3C .globl _savvec8
1020: 523 00000C3C _savvec8:
1021: 524 00000C3C **** .space 4
1022: 525 00000C40
1023: 526 00000C40 .globl _r_no
1024: 527 00000C40 _r_no:
1025: 528 00000C40 00000000 .long 0
1026: 529 00000C44 .globl _pt_base
1027: 530 00000C44 _pt_base:
1028: 531 00000C44 00000000 .long 0
1029: 532 00000C48 .globl _saved_psl
1030: 533 00000C48 _saved_psl:
1031: 534 00000C48 00000000 .long 0
1032: 535 00000C4C .globl _saved_sp
1033: 536 00000C4C _saved_sp:
1034: 537 00000C4C 00000000 .long 0
1035: 538 00000C50 .globl _saved_fp
1036: 539 00000C50 _saved_fp:
1037: 540 00000C50 00000000 .long 0
1038: 541 00000C54 .globl _ret_adr
1039: 542 00000C54 _ret_adr:
1040: 543 00000C54 00000000 .long 0
1041: 544 00000C58 .globl _exp_par0
1042: 545 00000C58 _exp_par0:
1043: 546 00000C58 00000000 .long 0
1044: 547 00000C5C .globl _exp_par1
1045: 548 00000C5C _exp_par1:
1046: 549 00000C5C 00000000 .long 0
1047: 550 00000C60 .globl _f_vaddr
1048: 551 00000C60 _f_vaddr:
1049: 552 00000C60 00000000 .long 0
1050: 553 00000C64
1051: 554 00000C64 .globl _f_ptr
1052: 555 00000C64 _f_ptr:
1053: 556 00000C64 00000000 .long 0
1054: 557 00000C68 .globl _df_cnt
1055: 558 00000C68 _df_cnt:
1056: 559 00000C68 00000000 .long 0
1057: 560 00000C6C
1058: 561 00000C6C .globl _if_cnt
1059: 562 00000C6C _if_cnt:
1060: 563 00000C6C 00000000 .long 0
1061: 564 00000C70
1062: 565 00000C70 .globl _newepc
1063: 566 00000C70 _newepc:
1064: 567 00000C70 00000000 .long 0
1065: 568 00000C74
1066: 569 00000C74 .globl _errcnt
1067: 570 00000C74 _errcnt:
1068: 571 00000C74 00000000 .long 0
1069: 572 00000C78
1070: 573 00000C78 .globl _clk_cnt
1071: 574 00000C78 _clk_cnt:
1072: 575 00000C78 00000000 .long 0
1073: 576 00000C7C
1074: 577 00000C7C .globl _ttcnt
1075: 578 00000C7C _ttcnt:
1076: 579 00000C7C 00000000 .long 0
1077: 580 00000C80 .globl _trcnt
1078: 581 00000C80 _trcnt:
1079: 582 00000C80 00000000 .long 0
1080: 583 00000C84
1081: 584 00000C84 .globl _Ufpte
1082: 585 00000C84 00000000 _Ufpte: .long 0
1083: 586 00000C88 .globl _Ulpte
1084: 587 00000C88 00000000 _Ulpte: .long 0
1085: 588 00000C8C
1086: 589 00000C8C .globl _dbuf
1087: 590 00000C8C _dbuf:
1088: 591 00000C8C **** .space 1024 - (NLWU *4)
1089: 592 00001000 edbuf:
1090: 593 00001000
1091: 594 00001000
1092: 595 00001000 .globl _intstack
1093: 596 00001000 _intstack:
1094: 597 00001000 **** .space NISP* 1024
1095: 598 00001800 eintstack:
1096: 599 00001800
1097: 600 00001800
1098: 601 00001800 .set SYSPTSIZE,512
1099: 602 00001800
1100: 603 00001800
1101: 604 00001800
1102: 605 00001800
1103: 606 00001800 .align 2
1104: 607 00001800 .globl _Sysmap
1105: 608 00001800 _Sysmap:
1106: 609 00001800 **** .space SYSPTSIZE*4
1107: 610 00002000 eSysmap:
1108: 611 00002000 .globl _Syssize
1109: 612 00002000 .set _Syssize,(eSysmap-_Sysmap)/4
1110: 613 00002000
1111: 614 00002000 .globl _iomap
1112: 615 00002000 **** _iomap: .space 1024
1113: 616 00002400 .globl _eiomap
1114: 617 00002400 _eiomap:
1115: 618 00002400
1116: 619 00002400 .globl _pcb0
1117: 620 00002400 **** _pcb0: .space 128
1118: 621 00002480 .globl _pcb1
1119: 622 00002480 **** _pcb1: .space 128
1120: 623 00002500 .globl _pcb2
1121: 624 00002500 **** _pcb2: .space 128
1122: 625 00002580 .globl _pcb3
1123: 626 00002580 **** _pcb3: .space 128
1124: 627 00002600 .globl _pcb4
1125: 628 00002600 **** _pcb4: .space 128
1126: 629 00002680 .globl _pcb5
1127: 630 00002680 **** _pcb5: .space 128
1128: 631 00002700 .globl _pcb6
1129: 632 00002700 **** _pcb6: .space 128
1130: 633 00002780 .globl _pcb7
1131: 634 00002780 **** _pcb7: .space 128
1132: 635 00002800
1133: 636 00002800
1134: 637 00002800
1135: 638 00002800
1136: 639 00002800
1137: 640 00002800 .align 2
1138: 641 00002800 .globl _u0p0pt
1139: 642 00002800 _u0p0pt:
1140: 643 00002800 **** .space 1024
1141: 644 00002C00 .globl _u0p1pt
1142: 645 00002C00 _u0p1pt:
1143: 646 00002C00 **** .space 1024
1144: 647 00003000 .globl _u0p2pt
1145: 648 00003000 _u0p2pt:
1146: 649 00003000 **** .space 1020
1147: 650 000033FC eu0p2pt:
1148: 651 000033FC **** .space 4
1149: 652 00003400
1150: 653 00003400
1151: 654 00003400
1152: 655 00003400
1153: 656 00003400
1154: 657 00003400 .align 2
1155: 658 00003400 .globl _u1p0pt
1156: 659 00003400 _u1p0pt:
1157: 660 00003400 **** .space 1024
1158: 661 00003800 .globl _u1p1pt
1159: 662 00003800 _u1p1pt:
1160: 663 00003800 **** .space 1024
1161: 664 00003C00 .globl _u1p2pt
1162: 665 00003C00 _u1p2pt:
1163: 666 00003C00 **** .space 1020
1164: 667 00003FFC eu1p2pt:
1165: 668 00003FFC **** .space 4
1166: 669 00004000
1167: 670 00004000
1168: 671 00004000
1169: 672 00004000
1170: 673 00004000
1171: 674 00004000
1172: 675 00004000 .align 2
1173: 676 00004000 .globl _u2p0pt
1174: 677 00004000 _u2p0pt:
1175: 678 00004000 **** .space 1024
1176: 679 00004400 .globl _u2p1pt
1177: 680 00004400 _u2p1pt:
1178: 681 00004400 **** .space 1024
1179: 682 00004800 .globl _u2p2pt
1180: 683 00004800 _u2p2pt:
1181: 684 00004800 **** .space 1020
1182: 685 00004BFC eu2p2pt:
1183: 686 00004BFC **** .space 4
1184: 687 00004C00
1185: 688 00004C00
1186: 689 00004C00
1187: 690 00004C00
1188: 691 00004C00
1189: 692 00004C00
1190: 693 00004C00 .align 2
1191: 694 00004C00 .globl _u3p0pt
1192: 695 00004C00 _u3p0pt:
1193: 696 00004C00 **** .space 1024
1194: 697 00005000 .globl _u3p1pt
1195: 698 00005000 _u3p1pt:
1196: 699 00005000 **** .space 1024
1197: 700 00005400 .globl _u3p2pt
1198: 701 00005400 _u3p2pt:
1199: 702 00005400 **** .space 1020
1200: 703 000057FC eu3p2pt:
1201: 704 000057FC **** .space 4
1202: 705 00005800
1203: 706 00005800
1204: 707 00005800
1205: 708 00005800
1206: 709 00005800
1207: 710 00005800 .globl _u4p0pt
1208: 711 00005800 _u4p0pt:
1209: 712 00005800 **** .space (9* 1024) - 4
1210: 713 00007BFC eu6p2pt:
1211: 714 00007BFC **** .space 4
1212: 715 00007C00
1213: 716 00007C00
1214: 717 00007C00
1215: 718 00007C00
1216: 719 00007C00
1217: 720 00007C00
1218: 721 00007C00 .align 2
1219: 722 00007C00 .globl _Kstack
1220: 723 00007C00 _Kstack:
1221: 724 00007C00 **** .space 3* 1024
1222: 725 00008800 .globl ekstack
1223: 726 00008800 ekstack:
1224: 727 00008800
1225: 728 00008800
1226: 729 00008800 .globl _iob0
1227: 730 00008800 **** _iob0: .space 1024
1228: 731 00008C00 .globl _iob1
1229: 732 00008C00 **** _iob1: .space 1024
1230: 733 00009000 .globl _iob2
1231: 734 00009000 **** _iob2: .space 1024
1232: 735 00009400 .globl _iob3
1233: 736 00009400 **** _iob3: .space 1024
1234: 737 00009800 .globl _iob4
1235: 738 00009800 **** _iob4: .space 1024
1236: 739 00009C00 .globl _iob5
1237: 740 00009C00 **** _iob5: .space 1024
1238: 741 0000A000 .globl _iob6
1239: 742 0000A000 **** _iob6: .space 1024
1240: 743 0000A400 esysdata:
1241: 744 0000A400
1242: 745 0000A400
1243: 746 0000A400
1244: 747 0000A400 # 1 "./scblock.s"
1245: 1 0000A400
1246: 2 0000A400 #
1247: 3 0000A400
1248: 4 0000A400
1249: 5 0000A400 .align 2
1250: 6 0000A400 .globl _scb
1251: 7 0000A400 _scb:
1252: 8 0000A400
1253: 9 0000A400
1254: 10 0000A400
1255: 11 0000A400
1256: 12 0000A400
1257: 13 0000A400
1258: 14 0000A400
1259: 15 0000A400 0000a800 0000a80c .long _Xunknown; .long _Xpowerfail;
1260: 16 0000A408 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
1261: 17 0000A410 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
1262: 18 0000A418 0000a800 0000a818 .long _Xunknown; .long _Xhardclock;
1263: 19 0000A420 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
1264: 20 0000A428 0000a820 0000a82c .long _Xcnrint; .long _Xcnxint;
1265: 21 0000A430 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
1266: 22 0000A438 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
1267: 23 0000A440 0000a830 0000a83c .long _Xs15; .long _Xs14;
1268: 24 0000A448 0000a848 0000a854 .long _Xs13; .long _Xs12;
1269: 25 0000A450 0000a860 0000a86c .long _Xs11; .long _Xs10;
1270: 26 0000A458 0000a878 0000a884 .long _Xs9; .long _Xs8;
1271: 27 0000A460 0000a890 0000a89c .long _Xs7; .long _Xs6;
1272: 28 0000A468 0000a8a8 0000a8b4 .long _Xs5; .long _Xs4;
1273: 29 0000A470 0000a8c0 0000a8cc .long _Xs3; .long _Xs2;
1274: 30 0000A478 0000a8d8 0000a800 .long _Xs1; .long _Xunknown;
1275: 31 0000A480 0000a8f4 0000a800 .long _Xbuserror; .long _Xunknown;
1276: 32 0000A488 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
1277: 33 0000A490 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
1278: 34 0000A498 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
1279: 35 0000A4A0 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
1280: 36 0000A4A8 0000a800 0000ab48 .long _Xunknown; .long _Xkcall;
1281: 37 0000A4B0 0000a90c 0000a950 .long _Xprvinflt; .long _Xresopflt;
1282: 38 0000A4B8 0000a99c 0000aa70 .long _Xresadflt; .long _Xprotflt;
1283: 39 0000A4C0 0000aa88 0000a900 .long _Xtransflt; .long _Xkspnotval;
1284: 40 0000A4C8 0000a9ec 0000a9e0 .long _Xtracep; .long _Xbptflt;
1285: 41 0000A4D0 0000aa24 0000aa94 .long _Xarithtrap; .long _Xalignflt;
1286: 42 0000A4D8 0000a800 0000aacc .long _Xunknown; .long _Xfpp_emulate;
1287: 43 0000A4E0 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
1288: 44 0000A4E8 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
1289: 45 0000A4F0 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
1290: 46 0000A4F8 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
1291: 47 0000A500 0000a8e4 0000a800 .long _Xiovec14; .long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xun000177C0 ng _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;
1292: 0000a800 0000a800
1293: 0000a800 0000a800
1294: 0000a800 0000a800
1295: 0000a800 0000a800
1296: 0000a800 0000a800
1297: 0000a800 0000a800
1298: 0000a800 0000a800
1299: 48 0000A540 0000a8e8 0000a800 .long _Xiovec15; .long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xu000177C0 ong _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;
1300: 0000a800 0000a800
1301: 0000a800 0000a800
1302: 0000a800 0000a800
1303: 0000a800 0000a800
1304: 0000a800 0000a800
1305: 0000a800 0000a800
1306: 0000a800 0000a800
1307: 49 0000A580 0000a8ec 0000a800 .long _Xiovec16; .long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xu000177C0 ong _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;
1308: 0000a800 0000a800
1309: 0000a800 0000a800
1310: 0000a800 0000a800
1311: 0000a800 0000a800
1312: 0000a800 0000a800
1313: 0000a800 0000a800
1314: 0000a800 0000a800
1315: 50 0000A5C0 0000a8f0 0000a800 .long _Xiovec17; .long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xu000177C0 ong _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;
1316: 0000a800 0000a800
1317: 0000a800 0000a800
1318: 0000a800 0000a800
1319: 0000a800 0000a800
1320: 0000a800 0000a800
1321: 0000a800 0000a800
1322: 0000a800 0000a800
1323: 51 0000A600
1324: 52 0000A600 **** .space 512
1325: 53 0000A800
1326: 54 0000A800
1327: 55 0000A800 # 747 ""
1328: 747 0000A800
1329: 748 0000A800
1330: 749 0000A800
1331: 750 0000A800
1332: 751 0000A800 # 1 "./evthandlers.s"
1333: 1 0000A800
1334: 2 0000A800
1335: 3 0000A800
1336: 4 0000A800
1337: 5 0000A800
1338: 6 0000A800
1339: 7 0000A800
1340: 8 0000A800
1341: 9 0000A800
1342: 10 0000A800
1343: 11 0000A800
1344: 12 0000A800
1345: 13 0000A800
1346: 14 0000A800
1347: 15 0000A800
1348: 16 0000A800
1349: 17 0000A800
1350: 18 0000A800
1351: 19 0000A800
1352: 20 0000A800
1353: 21 0000A800
1354: 22 0000A800
1355: 23 0000A800
1356: 24 0000A800
1357: 25 0000A800
1358: 26 0000A800
1359: 27 0000A800
1360: 28 0000A800
1361: 29 0000A800
1362: 30 0000A800
1363: 31 0000A800
1364: 32 0000A800
1365: 33 0000A800
1366: 34 0000A800
1367: 35 0000A800
1368: 36 0000A800
1369: 37 0000A800
1370: 38 0000A800
1371: 39 0000A800 .align 2 .globl _Xunknown _Xunknown:
1372: 40 0000A800 dd 00 pushl $0
1373: 41 0000A802 fe 08 efffff57f7 callf $8,_XTrap
1374: 42 0000A809 00 halt
1375: 43 0000A80A
1376: 44 0000A80A
1377: 45 0000A80A
1378: 46 0000A80A
1379: 47 0000A80A
1380: 48 0000A80A
1381: 49 0000A80A
1382: 50 0000A80A
1383: 51 0000A80A
1384: 52 0000A80A
1385: 53 0000A80A
1386: 54 0000A80A
1387: 55 0000A80A 0000 .align 2 .globl _Xpowerfail _Xpowerfail:
1388: 56 0000A80C dd 01 pushl $1
1389: 57 0000A80E fe 08 efffff57eb callf $8,_XTrap
1390: 58 0000A815 00 halt
1391: 59 0000A816
1392: 60 0000A816
1393: 61 0000A816
1394: 62 0000A816
1395: 63 0000A816
1396: 64 0000A816
1397: 65 0000A816 0000 .align 2 .globl _Xhardclock _Xhardclock:
1398: 66 0000A818 6d efffff57e2 incl _clock_event
1399: 67 0000A81E 20 rei
1400: 68 0000A81F
1401: 69 0000A81F
1402: 70 0000A81F
1403: 71 0000A81F
1404: 72 0000A81F
1405: 73 0000A81F 00 .align 2 .globl _Xcnrint _Xcnrint:
1406: 74 0000A820 dd 0a pushl $0xa
1407: 75 0000A822 fe 08 efffff57d7 callf $8,_XTrap
1408: 76 0000A829 00 halt
1409: 77 0000A82A
1410: 78 0000A82A
1411: 79 0000A82A
1412: 80 0000A82A
1413: 81 0000A82A 0000 .align 2 .globl _Xcnxint _Xcnxint:
1414: 82 0000A82C 20 rei
1415: 83 0000A82D
1416: 84 0000A82D
1417: 85 0000A82D
1418: 86 0000A82D
1419: 87 0000A82D 000000 .align 2 .globl _Xs15 _Xs15:
1420: 88 0000A830 dd 10 pushl $0x10
1421: 89 0000A832 fe 08 efffff57c7 callf $8,_XTrap
1422: 90 0000A839 00 halt
1423: 91 0000A83A
1424: 92 0000A83A
1425: 93 0000A83A
1426: 94 0000A83A
1427: 95 0000A83A 0000 .align 2 .globl _Xs14 _Xs14:
1428: 96 0000A83C dd 11 pushl $0x11
1429: 97 0000A83E fe 08 efffff57bb callf $8,_XTrap
1430: 98 0000A845 00 halt
1431: 99 0000A846
1432: 100 0000A846
1433: 101 0000A846
1434: 102 0000A846
1435: 103 0000A846 0000 .align 2 .globl _Xs13 _Xs13:
1436: 104 0000A848 dd 12 pushl $0x12
1437: 105 0000A84A fe 08 efffff57af callf $8,_XTrap
1438: 106 0000A851 00 halt
1439: 107 0000A852
1440: 108 0000A852
1441: 109 0000A852
1442: 110 0000A852
1443: 111 0000A852 0000 .align 2 .globl _Xs12 _Xs12:
1444: 112 0000A854 dd 13 pushl $0x13
1445: 113 0000A856 fe 08 efffff57a3 callf $8,_XTrap
1446: 114 0000A85D 00 halt
1447: 115 0000A85E
1448: 116 0000A85E
1449: 117 0000A85E
1450: 118 0000A85E
1451: 119 0000A85E 0000 .align 2 .globl _Xs11 _Xs11:
1452: 120 0000A860 dd 14 pushl $0x14
1453: 121 0000A862 fe 08 efffff5797 callf $8,_XTrap
1454: 122 0000A869 00 halt
1455: 123 0000A86A
1456: 124 0000A86A
1457: 125 0000A86A
1458: 126 0000A86A
1459: 127 0000A86A 0000 .align 2 .globl _Xs10 _Xs10:
1460: 128 0000A86C dd 15 pushl $0x15
1461: 129 0000A86E fe 08 efffff578b callf $8,_XTrap
1462: 130 0000A875 00 halt
1463: 131 0000A876
1464: 132 0000A876
1465: 133 0000A876
1466: 134 0000A876
1467: 135 0000A876 0000 .align 2 .globl _Xs9 _Xs9:
1468: 136 0000A878 dd 16 pushl $0x16
1469: 137 0000A87A fe 08 efffff577f callf $8,_XTrap
1470: 138 0000A881 00 halt
1471: 139 0000A882
1472: 140 0000A882
1473: 141 0000A882
1474: 142 0000A882
1475: 143 0000A882 0000 .align 2 .globl _Xs8 _Xs8:
1476: 144 0000A884 dd 17 pushl $0x17
1477: 145 0000A886 fe 08 efffff5773 callf $8,_XTrap
1478: 146 0000A88D 00 halt
1479: 147 0000A88E
1480: 148 0000A88E
1481: 149 0000A88E
1482: 150 0000A88E
1483: 151 0000A88E 0000 .align 2 .globl _Xs7 _Xs7:
1484: 152 0000A890 dd 18 pushl $0x18
1485: 153 0000A892 fe 08 efffff5767 callf $8,_XTrap
1486: 154 0000A899 00 halt
1487: 155 0000A89A
1488: 156 0000A89A
1489: 157 0000A89A
1490: 158 0000A89A
1491: 159 0000A89A 0000 .align 2 .globl _Xs6 _Xs6:
1492: 160 0000A89C dd 19 pushl $0x19
1493: 161 0000A89E fe 08 efffff575b callf $8,_XTrap
1494: 162 0000A8A5 00 halt
1495: 163 0000A8A6
1496: 164 0000A8A6
1497: 165 0000A8A6
1498: 166 0000A8A6
1499: 167 0000A8A6 0000 .align 2 .globl _Xs5 _Xs5:
1500: 168 0000A8A8 dd 1a pushl $0x1a
1501: 169 0000A8AA fe 08 efffff574f callf $8,_XTrap
1502: 170 0000A8B1 00 halt
1503: 171 0000A8B2
1504: 172 0000A8B2
1505: 173 0000A8B2
1506: 174 0000A8B2
1507: 175 0000A8B2 0000 .align 2 .globl _Xs4 _Xs4:
1508: 176 0000A8B4 dd 1b pushl $0x1b
1509: 177 0000A8B6 fe 08 efffff5743 callf $8,_XTrap
1510: 178 0000A8BD 00 halt
1511: 179 0000A8BE
1512: 180 0000A8BE
1513: 181 0000A8BE
1514: 182 0000A8BE
1515: 183 0000A8BE 0000 .align 2 .globl _Xs3 _Xs3:
1516: 184 0000A8C0 dd 1c pushl $0x1c
1517: 185 0000A8C2 fe 08 efffff5737 callf $8,_XTrap
1518: 186 0000A8C9 00 halt
1519: 187 0000A8CA
1520: 188 0000A8CA
1521: 189 0000A8CA
1522: 190 0000A8CA
1523: 191 0000A8CA 0000 .align 2 .globl _Xs2 _Xs2:
1524: 192 0000A8CC dd 1d pushl $0x1d
1525: 193 0000A8CE fe 08 efffff572b callf $8,_XTrap
1526: 194 0000A8D5 00 halt
1527: 195 0000A8D6
1528: 196 0000A8D6
1529: 197 0000A8D6
1530: 198 0000A8D6
1531: 199 0000A8D6 0000 .align 2 .globl _Xs1 _Xs1:
1532: 200 0000A8D8 dd 1e pushl $0x1e
1533: 201 0000A8DA fe 08 efffff571f callf $8,_XTrap
1534: 202 0000A8E1 00 halt
1535: 203 0000A8E2
1536: 204 0000A8E2
1537: 205 0000A8E2
1538: 206 0000A8E2
1539: 207 0000A8E2
1540: 208 0000A8E2 0000 .align 2 .globl _Xiovec14 _Xiovec14:
1541: 209 0000A8E4 00 halt
1542: 210 0000A8E5 000000 .align 2 .globl _Xiovec15 _Xiovec15:
1543: 211 0000A8E8 00 halt
1544: 212 0000A8E9 000000 .align 2 .globl _Xiovec16 _Xiovec16:
1545: 213 0000A8EC 00 halt
1546: 214 0000A8ED 000000 .align 2 .globl _Xiovec17 _Xiovec17:
1547: 215 0000A8F0 00 halt
1548: 216 0000A8F1
1549: 217 0000A8F1
1550: 218 0000A8F1
1551: 219 0000A8F1
1552: 220 0000A8F1
1553: 221 0000A8F1
1554: 222 0000A8F1
1555: 223 0000A8F1
1556: 224 0000A8F1
1557: 225 0000A8F1
1558: 226 0000A8F1
1559: 227 0000A8F1
1560: 228 0000A8F1
1561: 229 0000A8F1
1562: 230 0000A8F1
1563: 231 0000A8F1
1564: 232 0000A8F1
1565: 233 0000A8F1
1566: 234 0000A8F1 000000 .align 2 .globl _Xbuserror _Xbuserror:
1567: 235 0000A8F4 dd 20 pushl $0x20
1568: 236 0000A8F6 fe 08 efffff5703 callf $8,_XTrap
1569: 237 0000A8FD 00 halt
1570: 238 0000A8FE
1571: 239 0000A8FE
1572: 240 0000A8FE
1573: 241 0000A8FE
1574: 242 0000A8FE
1575: 243 0000A8FE
1576: 244 0000A8FE
1577: 245 0000A8FE
1578: 246 0000A8FE
1579: 247 0000A8FE
1580: 248 0000A8FE
1581: 249 0000A8FE 0000 .align 2 .globl _Xkspnotval _Xkspnotval:
1582: 250 0000A900 dd 31 pushl $0x31
1583: 251 0000A902 fe 08 efffff56f7 callf $8,_XTrap
1584: 252 0000A909 00 halt
1585: 253 0000A90A
1586: 254 0000A90A
1587: 255 0000A90A
1588: 256 0000A90A
1589: 257 0000A90A
1590: 258 0000A90A 0000 .align 2 .globl _Xprvinflt _Xprvinflt:
1591: 259 0000A90C cd efffff56ee movpsl _psl_val
1592: 260 0000A912 ad 1f 08 mtpr $0x1f,$IPL
1593: 261 0000A915 3d 890080 efffff56e2 bitl $PSL_DBL,_psl_val
1594: 262 0000A91E 31 08 beql 1f
1595: 263 0000A920 27 efffff56da std _post_evt_acc
1596: 264 0000A926 11 06 brb 2f
1597: 265 0000A928 26 efffff56d2 1: stf _post_evt_acc
1598: 266 0000A92E bb 891fff efffff56c9 2: storer $0x1fff,_store_regs
1599: 267 0000A937 ed 6d efffff56c2 moval (r13),_post_event_fp
1600: 268 0000A93E ed 6e efffff56bb moval (r14),_post_event_sp
1601: 269 0000A945 dd 2c pushl $0x2c
1602: 270 0000A947 fe 08 efffff56b2 callf $8,_XTrap
1603: 271 0000A94E 00 halt
1604: 272 0000A94F
1605: 273 0000A94F
1606: 274 0000A94F
1607: 275 0000A94F
1608: 276 0000A94F
1609: 277 0000A94F
1610: 278 0000A94F 00 .align 2 .globl _Xresopflt _Xresopflt:
1611: 279 0000A950 ad 1f 08 mtpr $0x1f,$IPL
1612: 280 0000A953 cd efffff56a7 movpsl _psl_val
1613: 281 0000A959 3d 890080 efffff569e bitl $PSL_DBL,_psl_val
1614: 282 0000A962 31 09 beql 1f
1615: 283 0000A964 27 efffff5696 std _post_evt_acc
1616: 284 0000A96A 13 000c brw 2f
1617: 285 0000A96D 26 efffff568d 1: stf _post_evt_acc
1618: 286 0000A973 4d efffff568b clrl _post_evt_acc+4
1619: 287 0000A979 2:
1620: 288 0000A979 bb 891fff efffff567e storer $0x1fff,_store_regs
1621: 289 0000A982 ed 6d efffff5677 moval (r13),_post_event_fp
1622: 290 0000A989 ed 6e efffff5670 moval (r14),_post_event_sp
1623: 291 0000A990 dd 2d pushl $0x2d
1624: 292 0000A992 fe 08 efffff5667 callf $8,_XTrap
1625: 293 0000A999 00 halt
1626: 294 0000A99A
1627: 295 0000A99A
1628: 296 0000A99A 0000 .align 2 .globl _Xresadflt _Xresadflt:
1629: 297 0000A99C cd efffff565e movpsl _psl_val
1630: 298 0000A9A2 ad 1f 08 mtpr $0x1f,$IPL
1631: 299 0000A9A5 3d 890080 efffff5652 bitl $PSL_DBL,_psl_val
1632: 300 0000A9AE 31 08 beql 1f
1633: 301 0000A9B0 27 efffff564a std _post_evt_acc
1634: 302 0000A9B6 11 06 brb 2f
1635: 303 0000A9B8 26 efffff5642 1: stf _post_evt_acc
1636: 304 0000A9BE bb 891fff efffff5639 2: storer $0x1fff,_store_regs
1637: 305 0000A9C7 ed 6d efffff5632 moval (r13),_post_event_fp
1638: 306 0000A9CE ed 6e efffff562b moval (r14),_post_event_sp
1639: 307 0000A9D5 dd 2e pushl $0x2e
1640: 308 0000A9D7 fe 08 efffff5622 callf $8,_XTrap
1641: 309 0000A9DE 00 halt
1642: 310 0000A9DF
1643: 311 0000A9DF 00 .align 2 .globl _Xbptflt _Xbptflt:
1644: 312 0000A9E0 dd 33 pushl $0x33
1645: 313 0000A9E2 fe 08 efffff5617 callf $8,_XTrap
1646: 314 0000A9E9 00 halt
1647: 315 0000A9EA
1648: 316 0000A9EA 0000 .align 2 .globl _Xtracep _Xtracep:
1649: 317 0000A9EC cd efffff560e movpsl _psl_val
1650: 318 0000A9F2 ad 1f 08 mtpr $0x1f,$IPL
1651: 319 0000A9F5 3d 890080 efffff5602 bitl $PSL_DBL,_psl_val
1652: 320 0000A9FE 31 08 beql 1f
1653: 321 0000AA00 27 efffff55fa std _post_evt_acc
1654: 322 0000AA06 11 06 brb 2f
1655: 323 0000AA08 26 efffff55f2 1: stf _post_evt_acc
1656: 324 0000AA0E bb 891fff efffff55e9 2: storer $0x1fff,_store_regs
1657: 325 0000AA17 dd 32 pushl $0x32
1658: 326 0000AA19 fe 08 efffff55e0 callf $8,_XTrap
1659: 327 0000AA20 00 halt
1660: 328 0000AA21
1661: 329 0000AA21
1662: 330 0000AA21
1663: 331 0000AA21
1664: 332 0000AA21
1665: 333 0000AA21
1666: 334 0000AA21 000000 .align 2 .globl _Xarithtrap _Xarithtrap:
1667: 335 0000AA24 ad 1f 08 mtpr $0x1f,$IPL
1668: 336 0000AA27 cd efffff55d3 movpsl _psl_val
1669: 337 0000AA2D 3d 890080 efffff55ca bitl $PSL_DBL,_psl_val
1670: 338 0000AA36 31 09 beql 1f
1671: 339 0000AA38 27 efffff55c2 std _post_evt_acc
1672: 340 0000AA3E 13 000c brw 2f
1673: 341 0000AA41 1:
1674: 342 0000AA41 26 efffff55b9 stf _post_evt_acc
1675: 343 0000AA47 4d efffff55b7 clrl _post_evt_acc+4
1676: 344 0000AA4D 2:
1677: 345 0000AA4D bb 891fff efffff55aa storer $0x1fff,_store_regs
1678: 346 0000AA56 ed 6d efffff55a3 moval (r13),_post_event_fp
1679: 347 0000AA5D ed 6e efffff559c moval (r14),_post_event_sp
1680: 348 0000AA64 dd 34 pushl $0x34
1681: 349 0000AA66 fe 08 efffff5593 callf $8,_XTrap
1682: 350 0000AA6D 00 halt
1683: 351 0000AA6E
1684: 352 0000AA6E
1685: 353 0000AA6E 0000 .align 2 .globl _Xprotflt _Xprotflt:
1686: 354 0000AA70 cd efffff558a movpsl _psl_val
1687: 355 0000AA76 ed 6e efffff5583 moval (r14),_post_event_sp
1688: 356 0000AA7D dd 2f pushl $0x2f
1689: 357 0000AA7F fe 08 efffff557a callf $8,_XTrap
1690: 358 0000AA86 00 halt
1691: 359 0000AA87 00 .align 2 .globl _Xtransflt _Xtransflt:
1692: 360 0000AA88 dd 30 pushl $0x30
1693: 361 0000AA8A fe 08 efffff556f callf $8,_XTrap
1694: 362 0000AA91 00 halt
1695: 363 0000AA92 0000 .align 2 .globl _Xalignflt _Xalignflt:
1696: 364 0000AA94 cd efffff5566 movpsl _psl_val
1697: 365 0000AA9A ad 1f 08 mtpr $0x1f,$IPL
1698: 366 0000AA9D 3d 890080 efffff555a bitl $PSL_DBL,_psl_val
1699: 367 0000AAA6 31 08 beql 1f
1700: 368 0000AAA8 27 efffff5552 std _post_evt_acc
1701: 369 0000AAAE 11 06 brb 2f
1702: 370 0000AAB0 26 efffff554a 1: stf _post_evt_acc
1703: 371 0000AAB6 bb 891fff efffff5541 2: storer $0x1fff,_store_regs
1704: 372 0000AABF dd 35 pushl $0x35
1705: 373 0000AAC1 fe 08 efffff5538 callf $8,_XTrap
1706: 374 0000AAC8 00 halt
1707: 375 0000AAC9 000000 .align 2 .globl _Xfpp_emulate _Xfpp_emulate:
1708: 376 0000AACC cd efffff552e movpsl _psl_val
1709: 377 0000AAD2 0d efffff5528 efffff5523 movl _psl_val,_post_event_psl
1710: 378 0000AADD bb 891fff efffff551a storer $0x1fff,_store_regs
1711: 379 0000AAE6 ed 6d efffff5513 moval (r13),_post_event_fp
1712: 380 0000AAED ed 6e efffff550c moval (r14),_post_event_sp
1713: 381 0000AAF4 0d 6e efffff5505 movl (sp),_fpm_ms_op
1714: 382 0000AAFB 0d ae04 efffff54fd movl 4(sp),_fpm_ls_op
1715: 383 0000AB03 0d ae08 efffff54f5 movl 8(sp),_fpm_op_code
1716: 384 0000AB0B 0d ae0c efffff54ed movl 12(sp),_fpm_pc
1717: 385 0000AB13 0d ae10 efffff54e5 movl 16(sp),_fpm_psl
1718: 386 0000AB1B 3d 890080 efffff54dc bitl $PSL_DBL,_psl_val
1719: 387 0000AB24 31 08 beql 1f
1720: 388 0000AB26 27 efffff54d4 std _post_evt_acc
1721: 389 0000AB2C 11 0c brb 2f
1722: 390 0000AB2E 26 efffff54cc 1: stf _post_evt_acc
1723: 391 0000AB34 4d efffff54ca clrl _post_evt_acc+4
1724: 392 0000AB3A 2:
1725: 393 0000AB3A dd 37 pushl $0x37
1726: 394 0000AB3C fe 08 efffff54bd callf $8,_XTrap
1727: 395 0000AB43 00 halt
1728: 396 0000AB44
1729: 397 0000AB44 alltraps:
1730: 398 0000AB44 00 halt
1731: 399 0000AB45
1732: 400 0000AB45 000000 .align 2 .globl _Xkcall _Xkcall:
1733: 401 0000AB48 dd 2b pushl $0x2b
1734: 402 0000AB4A fe 08 efffff54af callf $8,_XTrap
1735: 403 0000AB51 00 halt
1736: 404 0000AB52
1737: 405 0000AB52
1738: 406 0000AB52 # 751 ""
1739: 751 0000AB52
1740: 752 0000AB52
1741: 753 0000AB52
1742: 754 0000AB52
1743: 755 0000AB52
1744: 756 0000AB52
1745: 757 0000AB52
1746: 758 0000AB52
1747: 759 0000AB52
1748: 760 0000AB52
1749: 761 0000AB52
1750: 762 0000AB52
1751: 763 0000AB52
1752: 764 0000AB52 .globl start
1753: 765 0000AB52 start:
1754: 766 0000AB52 ad 00 09 mtpr $0,$MME
1755: 767 0000AB55 0d 50 efffff54a4 movl r0,_run_list
1756: 768 0000AB5C 0d 51 efffff549d movl r1,_OPTIONS
1757: 769 0000AB63 0d 53 efffff5496 movl r3,_evt_inst
1758: 770 0000AB6A 4d efffff5490 clrl _nonstop
1759: 771 0000AB70 0d 52 efffff5489 movl r2,_count
1760: 772 0000AB77 21 07 bneq 1f
1761: 773 0000AB79 0d 01 efffff5480 movl $1,_count
1762: 774 0000AB80 81 07 1: bgeq 1f
1763: 775 0000AB82 0d 01 efffff5477 movl $1,_nonstop
1764: 776 0000AB89 1:
1765: 777 0000AB89 4d efffff5471 clrl _no_fpp_wcs
1766: 778 0000AB8F ad 890400 1b mtpr $0x400,$DCR
1767: 779 0000AB94 5d 51 tstl r1
1768: 780 0000AB96 21 07 bneq 1f
1769: 781 0000AB98 0d 01 efffff5461 movl $1,_no_fpp_wcs
1770: 782 0000AB9F 1:
1771: 783 0000AB9F e9 effffff85b 50 movab _scb,r0
1772: 784 0000ABA6 ac 8f3ffffc00 50 andl2 $0x3ffffc00,r0
1773: 785 0000ABAD ad 50 12 mtpr r0,$SCBB
1774: 786 0000ABB0 ad 1f 08 mtpr $0x1f,$IPL
1775: 787 0000ABB3
1776: 788 0000ABB3 bc 04 5b efffff5445 andl3 $4,r11,_ss1
1777: 789 0000ABBB
1778: 790 0000ABBB
1779: 791 0000ABBB # clear the option flags
1780: 792 0000ABBB
1781: 793 0000ABBB 4d efffff543f clrl _halt_flg
1782: 794 0000ABC1 4d efffff5439 clrl _loop_on_err
1783: 795 0000ABC7 0d 01 efffff5432 movl $1,_prt_error
1784: 796 0000ABCE 0d 01 efffff542b movl $1,_prt_hdrs
1785: 797 0000ABD5 0d 01 efffff5424 movl $1,_en_data_cache
1786: 798 0000ABDC
1787: 799 0000ABDC
1788: 800 0000ABDC # set the option flags as needed
1789: 801 0000ABDC
1790: 802 0000ABDC 3d 01 efffff541d bitl $1,_OPTIONS
1791: 803 0000ABE3 31 07 beql 1f
1792: 804 0000ABE5 0d 01 efffff5414 movl $1,_halt_flg
1793: 805 0000ABEC 1:
1794: 806 0000ABEC 3d 02 efffff540d bitl $2,_OPTIONS
1795: 807 0000ABF3 31 07 beql 1f
1796: 808 0000ABF5 0d 01 efffff5404 movl $1,_loop_on_err
1797: 809 0000ABFC 1:
1798: 810 0000ABFC 3d 04 efffff53fd bitl $4,_OPTIONS
1799: 811 0000AC03 31 06 beql 1f
1800: 812 0000AC05 4d efffff53f5 clrl _prt_error
1801: 813 0000AC0B 1:
1802: 814 0000AC0B 3d 08 efffff53ee bitl $8,_OPTIONS
1803: 815 0000AC12 31 06 beql 1f
1804: 816 0000AC14 4d efffff53e6 clrl _prt_hdrs
1805: 817 0000AC1A 1:
1806: 818 0000AC1A 3d 10 efffff53df bitl $16,_OPTIONS
1807: 819 0000AC21 31 06 beql 1f
1808: 820 0000AC23 4d efffff53d7 clrl _en_data_cache
1809: 821 0000AC29 1:
1810: 822 0000AC29
1811: 823 0000AC29 4d efffff53d1 clrl _exp_event
1812: 824 0000AC2F cd 51 movpsl r1
1813: 825 0000AC31 ac 89ff00 51 andl2 $0xffffff00,r1
1814: 826 0000AC36 1d 51 8f041f0000 cmpl r1,$0x041f0000
1815: 827 0000AC3D 31 0b beql 1f
1816: 828 0000AC3F 0d 01 50 2: movl $1,r0
1817: 829 0000AC42 0d 8f041f0000 52 movl $0x041f0000,r2
1818: 830 0000AC49 00 halt
1819: 831 0000AC4A 1:
1820: 832 0000AC4A 0d 8f00001800 50 movl $_intstack+NISP* 1024,r0
1821: 833 0000AC51 ac 8f3fffffff 50 andl2 $0x3fffffff,r0
1822: 834 0000AC58 ad 50 0f mtpr r0,$ISP
1823: 835 0000AC5B 0d 50 5e movl r0,sp
1824: 836 0000AC5E e9 6e 5d movab (sp),fp
1825: 837 0000AC61
1826: 838 0000AC61 # Clear system data area all the way upto system code
1827: 839 0000AC61 # this includes dump buffer,interrupt stack,spt,iomap,pcbs,user
1828: 840 0000AC61 # page tables, & io buffer area.
1829: 841 0000AC61
1830: 842 0000AC61 3:
1831: 843 0000AC61 e9 effffff799 57 movab esysdata,r7
1832: 844 0000AC68 e9 efffff5f96 56 movab _restart,r6
1833: 845 0000AC6F 4d 66 1: clrl (r6)
1834: 846 0000AC71 0c 04 56 1d 56 57 51 f6 addl2 $4,r6; cmpl r6,r7; bleq 1b;
1835: 847 0000AC79
1836: 848 0000AC79 # Initialize System Page Table
1837: 849 0000AC79
1838: 850 0000AC79 5:
1839: 851 0000AC79 4d 52 clrl r2
1840: 852 0000AC7B e9 effffff77f 51 movab esysdata,r1
1841: 853 0000AC82 ac 8f3fffffff 51 andl2 $0x3fffffff,r1
1842: 854 0000AC89 5e 0a 51 51 shar $ 10 ,r1,r1
1843: 855 0000AC8D
1844: 856 0000AC8D 1:
1845: 857 0000AC8D 9c 8fe0000000 52 orl3 $ 0x80000000| 0x60000000,r2,_Sysmap[r2]
1846: 42efffff6b66
1847: 858 0000AC9A 2f 51 52 ffee aoblss r1,r2,1b
1848: 859 0000AC9F
1849: 860 0000AC9F
1850: 861 0000AC9F # Map system text area 1 to 1, Kernel read/write.
1851: 862 0000AC9F # For this to work, the label _etext must exist at the end
1852: 863 0000AC9F # of system code; Add in 4 more pages for data area used in C
1853: 864 0000AC9F
1854: 865 0000AC9F e9 ef000000db 51 movab _Esys,r1
1855: 866 0000ACA6 ac 8f3fffffff 51 andl2 $0x3fffffff,r1
1856: 867 0000ACAD 5e 0a 51 51 shar $ 10 ,r1,r1
1857: 868 0000ACB1 1:
1858: 869 0000ACB1 9c 8fe0000000 52 orl3 $ 0x80000000| 0x60000000,r2,_Sysmap[r2]
1859: 42efffff6b42
1860: 870 0000ACBE 3f 51 52 ffee aobleq r1,r2,1b
1861: 871 0000ACC3
1862: 872 0000ACC3 # Map from here to last page used by user :
1863: 873 0000ACC3 # invalid, User access, & virtual = physical
1864: 874 0000ACC3
1865: 875 0000ACC3 0d 52 efffff5f4a movl r2,_unused
1866: 876 0000ACCA 0d 52 efffff5fb3 movl r2,_Ufpte
1867: 877 0000ACD1 0d 8f00080000 51 movl $0x80000,r1
1868: 878 0000ACD8 5e 0a 51 51 shar $ 10 ,r1,r1
1869: 879 0000ACDC 0d 51 efffff5fa5 movl r1,_Ulpte
1870: 880 0000ACE3
1871: 881 0000ACE3 1:
1872: 882 0000ACE3 9c 8ff8000000 52 orl3 $ 0x80000000| 0x78000000,r2,_Sysmap[r2]
1873: 42efffff6b10
1874: 883 0000ACF0 2f 51 52 ffee aoblss r1,r2,1b
1875: 884 0000ACF5
1876: 885 0000ACF5
1877: 886 0000ACF5 # Initialize SBR, SLR
1878: 887 0000ACF5
1879: 888 0000ACF5 sysrdy:
1880: 889 0000ACF5 ad 8f00001800 00 mtpr $_Sysmap,$SBR
1881: 890 0000ACFC ad 890200 01 mtpr $_Syssize,$SLR
1882: 891 0000AD01 ad 8840 1b mtpr $64,$DCR
1883: 892 0000AD05
1884: 893 0000AD05 # GO TO VIRTUAL MODE
1885: 894 0000AD05 # Double map the kernel into user addresses :
1886: 895 0000AD05 # This will enable system to go to virtual mode the 1st time !!
1887: 896 0000AD05
1888: 897 0000AD05
1889: 898 0000AD05 9c 8fc0000000 8f00001800 orl3 $0xc0000000,$_Sysmap,r0
1890: 50
1891: 899 0000AD11 ad 50 02 mtpr r0,$P0BR
1892: 900 0000AD14 ad 890200 03 mtpr $_Syssize,$P0LR
1893: 901 0000AD19 ad 01 19 mtpr $1,$PADC
1894: 902 0000AD1C ad 01 17 mtpr $1,$PACC
1895: 903 0000AD1F ad 01 0a mtpr $1,$TBIA
1896: 904 0000AD22
1897: 905 0000AD22 ad 8f00002400 0e mtpr $_pcb0,$0xe
1898: 906 0000AD29
1899: 907 0000AD29 e9 efffff76d1 50 movab _pcb0,r0
1900: 908 0000AD30 e9 efffffdaca 60 movab ekstack,PCB_KSP(r0)
1901: 909 0000AD37 e9 ef00000c3f a004 movab eustack,PCB_USP(r0)
1902: 910 0000AD3F bd 02 a048 mfpr $P0BR,PCB_P0BR(r0)
1903: 911 0000AD43 bd 03 a04c mfpr $P0LR,PCB_P0LR(r0)
1904: 912 0000AD47 0d 00 a044 movl $0x0000000,PCB_PSL(r0)
1905: 913 0000AD4B
1906: 914 0000AD4B bd 12 50 mfpr $SCBB,r0
1907: 915 0000AD4E e9 ef00000024 a01c movab _Clock_handler,CLOCKVEC(r0)
1908: 916 0000AD56
1909: 917 0000AD56 e9 efffffdaa4 5e movab ekstack,sp
1910: 918 0000AD5D e9 6e 5d movab (sp),fp
1911: 919 0000AD60
1912: 920 0000AD60 0d 01 efffff5e99 movl $1,_Codek
1913: 921 0000AD67 ad efffff5e93 0d mtpr _Codek,$CCK
1914: 922 0000AD6E
1915: 923 0000AD6E fe 04 efffff528b callf $4,_monitor
1916: 924 0000AD75
1917: 925 0000AD75
1918: 926 0000AD75
1919: 927 0000AD75
1920: 928 0000AD75 #
1921: 929 0000AD75
1922: 930 0000AD75
1923: 931 0000AD75 000000 .align 2
1924: 932 0000AD78 .globl _Clock_handler
1925: 933 0000AD78 _Clock_handler:
1926: 934 0000AD78 0d 01 efffff5281 movl $1,_rtc_occurred
1927: 935 0000AD7F 20 rei
1928: 936 0000AD80
1929: 937 0000AD80
1930: 938 0000AD80
1931: 939 0000AD80 #
1932: 940 0000AD80
1933: 941 0000AD80
1934: 942 0000AD80
1935: 943 0000AD80 .globl _Esys
1936: 944 0000AD80 _Esys:
1937: 945 0000AD80 **** .space 1024
1938: 946 0000B180
1939: 947 0000B180 .globl _Ustack
1940: 948 0000B180 _Ustack:
1941: 949 0000B180 **** .space (2* 1024)-4
1942: 950 0000B97C .globl eustack
1943: 951 0000B97C eustack:
1944: 952 0000B97C 00000000 .long 0
1945: 953 0000b980 *
1946: 954 0000b980 * .globl U_area
1947: 955 0000b980 * U_area:
1948: 956 0000b980 *
1949: 956 0000b980 *
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