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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / fpevent|
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Power 6/32 Unix version 1.21
1 00000000 # 1 ""
1 00000000
2 00000000
3 00000000
4 00000000
5 00000000
6 00000000 .set SBR,0
7 00000000 .set SLR,1
8 00000000 .set P0BR,2
9 00000000 .set P0LR,3
10 00000000 .set P1BR,4
11 00000000 .set P1LR,5
12 00000000 .set P2BR,6
13 00000000 .set P2LR,7
14 00000000 .set IPL,8
15 00000000 .set MME,9
16 00000000 .set TBIA,10
17 00000000
18 00000000 .set TBIS,11
19 00000000
20 00000000 .set DCK,12
21 00000000 .set CCK,13
22 00000000 .set PCBB,14
23 00000000 .set ISP,15
24 00000000 .set SIRR,16
25 00000000 .set SISR,17
26 00000000 .set SCBB,18
27 00000000 .set KSP,19
28 00000000 .set USP,20
29 00000000 .set DCB,21
30 00000000 .set PACC,23
31 00000000
32 00000000 .set P1DC,24
33 00000000 .set PADC,25
34 00000000
35 00000000 .set HISR,26
36 00000000 .set DCR,27
37 00000000 .set PDCS,28
38 00000000
39 00000000
40 00000000 #TAHOE program status longword
41 00000000
42 00000000
43 00000000 .set PSL_C,0x00000001
44 00000000 .set PSL_V,0x00000002
45 00000000 .set PSL_Z,0x00000004
46 00000000 .set Z,0x00000004
47 00000000 .set PSL_N,0x00000008
48 00000000 .set PSL_T,0x00000010
49 00000000 .set PSL_I,0x00000020
50 00000000 .set PSL_EN_OVFL,0x20
51 00000000 .set PSL_EN_UNDFL,0x40
52 00000000 .set PSL_DBL,0x80
53 00000000 .set PSL_IPL,0x001f0000
54 00000000 .set PSL_MOD,0x01000000
55 00000000 .set PSL_IS,0x04000000
56 00000000 .set PSL_TP,0x40000000
57 00000000
58 00000000
59 00000000 # TAHOE page table entry
60 00000000 #/
61 00000000 .set PG_V,0x8000000
62 00000000 .set PG_PROT,0x78000000
63 00000000 .set PG_M,0x04000000
64 00000000 .set PG_USED,0x02000000
65 00000000 .set PG_NC,0x01000000
66 00000000 .set PG_PFNUM,0x003fffff
67 00000000
68 00000000 .set PG_NOACC,0
69 00000000 .set PG_KR,0x40000000
70 00000000 .set PG_KW,0x60000000
71 00000000 .set PG_URKR,0x50000000
72 00000000 .set PG_URKW,0x70000000
73 00000000 .set PG_UW,0x78000000
74 00000000
75 00000000 #* PCB offsets & diagnostic extension to pcb */
76 00000000 #* PCB is at pcb0 */
77 00000000
78 00000000
79 00000000 .set PCB_SIZE, 24
80 00000000 .set PCB_KSP, 0
81 00000000 .set PCB_USP, 4
82 00000000 .set PCB_R0, 8
83 00000000 .set PCB_R1, 12
84 00000000 .set PCB_R2, 16
85 00000000 .set PCB_R3, 20
86 00000000 .set PCB_R4, 24
87 00000000 .set PCB_R5, 28
88 00000000 .set PCB_R6, 32
89 00000000 .set PCB_R7, 36
90 00000000 .set PCB_R8, 40
91 00000000 .set PCB_R9, 44
92 00000000 .set PCB_R10, 48
93 00000000 .set PCB_R11, 52
94 00000000 .set PCB_R12, 56
95 00000000 .set PCB_R13, 60
96 00000000 .set PCB_PC, 64
97 00000000 .set PCB_PSL, 68
98 00000000 .set PCB_P0BR, 72
99 00000000 .set PCB_P0LR, 76
100 00000000 .set PCB_P1BR, 80
101 00000000 .set PCB_P1LR, 84
102 00000000 .set PCB_P2BR, 88
103 00000000 .set PCB_P2LR, 92
104 00000000 .set PCB_ACCM, 96
105 00000000 .set PCB_ACCL, 100
106 00000000 #*
107 00000000 # Diagnostic pcb extension
108 00000000 #/
109 00000000 .set PCB_STAT, 104
110 00000000
111 00000000
112 00000000
113 00000000 #* fundamental constants */
114 00000000
115 00000000 #*
116 00000000 # fundamental constants of the implementation--
117 00000000 # cannot be changed easily.
118 00000000 #/
119 00000000
120 00000000 .set NBPG,1024
121 00000000 .set PGOFSET,(NBPG-1)
122 00000000 .set PGSHIFT,10
123 00000000 .set HIGH,0x1f
124 00000000
125 00000000
126 00000000 #* SCB offsets */
127 00000000 #* SCB is at scb */
128 00000000
129 00000000 .set PFVEC,1*4
130 00000000 .set PRVEC,2*4
131 00000000 .set CLOCKVEC,7*4
132 00000000 .set CRVEC,0xa*4
133 00000000 .set CXVEC,44
134 00000000 .set SIVEC1,0x1e*4
135 00000000
136 00000000
137 00000000 .set BEVEC,0x20*4
138 00000000 .set SYSVEC,0x2b*4
139 00000000 .set PINSTVEC,0x2c*4
140 00000000 .set PRIVSVEC,0x2c*4
141 00000000 .set ROVEC,0x2d*4
142 00000000 .set RAVEC,0x2e*4
143 00000000 .set PROTVEC,0x2f*4
144 00000000 .set TRANS,0x30
145 00000000 .set TRANSVEC,0x30*4
146 00000000 .set KSPVEC,0x31*4
147 00000000 .set TRACEVEC,0x32*4
148 00000000 .set BPTVEC,0x33*4
149 00000000 .set ARITHVEC,0x34*4
150 00000000 .set ALIGNVEC,0x35*4
151 00000000 .set FPMVEC,0x37*4
152 00000000 .set IO14VEC,256
153 00000000 .set IO15VEC,320
154 00000000 .set IO16VEC,384
155 00000000 .set IO17VEC,448
156 00000000
157 00000000 #* SPT (system page table) offsets */
158 00000000 #* SPT is at Sysmap */
159 00000000
160 00000000 .set SCBPTE,8
161 00000000 .set BUFPTE,12
162 00000000 .set ISPTE,16
163 00000000 .set IS1PTE,20
164 00000000 .set SPTPTE,20
165 00000000 .set SPT1PTE,20
166 00000000 .set IOMAPPTE,24
167 00000000 .set PCBPTE,28
168 00000000 .set U0P0PTE,32
169 00000000 .set U0P1PTE,36
170 00000000 .set U0P2PTE,40
171 00000000 .set U1P0PTE,44
172 00000000 .set U1P1PTE,48
173 00000000 .set U1P2PTE,52
174 00000000 .set U2P0PTE,56
175 00000000 .set U2P1PTE,60
176 00000000 .set U2P2PTE,64
177 00000000 .set U3P0PTE,68
178 00000000 .set U3P1PTE,72
179 00000000 .set U3P2PTE,76
180 00000000 .set U4P0PTE,80
181 00000000 .set U4P1PTE,84
182 00000000 .set U4P2PTE,88
183 00000000 .set U5P0PTE,92
184 00000000 .set U5P1PTE,96
185 00000000 .set U5P2PTE,100
186 00000000 .set U6P0PTE,104
187 00000000 .set U6P1PTE,108
188 00000000 .set U6P2PTE,112
189 00000000 .set U7P0PTE,116
190 00000000 .set U7P1PTE,120
191 00000000 .set U7P2PTE,124
192 00000000 .set IOB0PTE,128
193 00000000 .set IOB1PTE,132
194 00000000 .set IOB2PTE,136
195 00000000 .set IOB3PTE,140
196 00000000 .set IOB4PTE,144
197 00000000 .set IOB5PTE,148
198 00000000 .set IOB6PTE,152
199 00000000 .set IOB7PTE,156
200 00000000
201 00000000
202 00000000 #* trap.h 4.6 81/03/03 */
203 00000000
204 00000000 #*
205 00000000 #* Trap type values
206 00000000 #/
207 00000000
208 00000000 .set RESADFLT,0
209 00000000 .set PRIVINFLT,1
210 00000000 .set RESOPFLT,2
211 00000000 .set BPTFLT,3
212 00000000 .set ALIGNFLT,4
213 00000000 .set SYSCALL,5
214 00000000 .set ARITHTRAP,6
215 00000000 .set PROTFLT,7
216 00000000 .set TRCTRAP,8
217 00000000 .set TRANSFLT,9
218 00000000 .set DONE,255
219 00000000
220 00000000
221 00000000 # Event codes
222 00000000
223 00000000 .set RTCLOCK_CODE,7
224 00000000 .set RESOP_CODE,0x2d
225 00000000 .set RESAD_CODE,0x2e
226 00000000 .set ARITH_CODE,0x34
227 00000000 .set FPM_CODE,0x37
228 00000000 .set INTEGER_OVERFLOW,1
229 00000000
230 00000000
231 00000000 # Arithmetic Event types
232 00000000
233 00000000 .set INT_OVFL_CODE,1
234 00000000 .set INT_0_DIV_CODE,2
235 00000000 .set FLT_0_DIV_CODE,3
236 00000000 .set FLT_OVFL_CODE,4
237 00000000 .set FLT_UNDFL_CODE,5
238 00000000
239 00000000
240 00000000 # Floating Point Instruction Op-Codes
241 00000000
242 00000000 .set LDF_OP_CODE,0x06
243 00000000 .set LDD_OP_CODE,0x07
244 00000000 .set LNF_OP_CODE,0x16
245 00000000 .set LND_OP_CODE,0x17
246 00000000 .set STF_OP_CODE,0x26
247 00000000 .set STD_OP_CODE,0x27
248 00000000 .set CMPF_OP_CODE,0x36
249 00000000 .set CMPD_OP_CODE,0x37
250 00000000 .set CMPF2_OP_CODE,0x46
251 00000000 .set CMPD2_OP_CODE,0x47
252 00000000 .set TSTF_OP_CODE,0x56
253 00000000 .set TSTD_OP_CODE,0x57
254 00000000 .set PUSHD_OP_CODE,0x67
255 00000000 .set CVLF_OP_CODE,0x76
256 00000000 .set CVLD_OP_CODE,0x77
257 00000000 .set CVFL_OP_CODE,0x86
258 00000000 .set CVDL_OP_CODE,0x87
259 00000000 .set LDFD_OP_CODE,0x97
260 00000000 .set CVDF_OP_CODE,0xa6
261 00000000 .set NEGF_OP_CODE,0xb6
262 00000000 .set NEGD_OP_CODE,0xb7
263 00000000 .set ADDF_OP_CODE,0xc6
264 00000000 .set ADDD_OP_CODE,0xc7
265 00000000 .set SUBF_OP_CODE,0xd6
266 00000000 .set SUBD_OP_CODE,0xd7
267 00000000 .set MULF_OP_CODE,0xe6
268 00000000 .set MULD_OP_CODE,0xe7
269 00000000 .set DIVF_OP_CODE,0xf6
270 00000000 .set DIVD_OP_CODE,0xf7
271 00000000 .set SINF_OP_CODE,0x05
272 00000000 .set COSF_OP_CODE,0x15
273 00000000 .set ATANF_OP_CODE,0x25
274 00000000 .set LOGF_OP_CODE,0x35
275 00000000 .set SQRTF_OP_CODE,0x45
276 00000000 .set EXPF_OP_CODE,0x55
277 00000000 .set MULL2_OP_CODE,0x4c
278 00000000 .set MULL3_OP_CODE,0x5c
279 00000000
280 00000000
281 00000000
282 00000000 # Addressing test constants - These must agree with "fpp_defs.h"
283 00000000
284 00000000 .set ADR_ABSOLUTE,1
285 00000000 .set ADR_LITERAL,2
286 00000000 .set ADR_IM_B,3
287 00000000 .set ADR_IM_W,4
288 00000000 .set ADR_IM_L,5
289 00000000 .set ADR_B_DSP,6
290 00000000 .set ADR_W_DSP,7
291 00000000 .set ADR_L_DSP,8
292 00000000 .set ADR_B_DSP_DEF,9
293 00000000 .set ADR_W_DSP_DEF,10
294 00000000 .set ADR_L_DSP_DEF,11
295 00000000 .set ADR_REG,12
296 00000000 .set ADR_REG_DEF,13
297 00000000 .set ADR_FP_DEF,14
298 00000000 .set ADR_SP_DEF,15
299 00000000 .set ADR_PUSH,16
300 00000000 .set ADR_POP,17
301 00000000 .set ADR_POP_DEF,18
302 00000000 .set ADR_REG_B,19
303 00000000 .set ADR_REG_W,20
304 00000000 .set ADR_REG_L,21
305 00000000 .set ADR_REG_B_DEF,22
306 00000000 .set ADR_REG_W_DEF,23
307 00000000 .set ADR_REG_L_DEF,24
308 00000000 .set ADR_I_FP_DEF,25
309 00000000 .set ADR_I_L,26
310 00000000
311 00000000
312 00000000 #*************************************************************************
313 00000000
314 00000000 # Stuff for the Demand Paging , Events, & Addressing Tests
315 00000000
316 00000000 #************************************************************************/
317 00000000 .set SGL,1
318 00000000 .set DBL,2
319 00000000 .set ENABLE_EVENTS,0x60
320 00000000 .set NONE,0
321 00000000 .set LOAD,1
322 00000000 .set STORE,2
323 00000000
324 00000000 .set NO_EVT_HLT,1
325 00000000 .set EVT_MSK_HLT,2
326 00000000 .set BAD_PSL_HLT,3
327 00000000 .set PUSH_CNT_HLT,4
328 00000000 .set PUSH_PSL_HLT,5
329 00000000 .set PUSH_PC_HLT,6
330 00000000 .set BAD_REG_HLT,7
331 00000000 .set BAD_ACC_HLT,8
332 00000000
333 00000000
334 00000000 # set DMP_PG_0 to the 1st empty page
335 00000000
336 00000000 .set DMP_PG_0,0x36000
337 00000000 .set DMP_PG_1,DMP_PG_0+0x400
338 00000000 .set DMP_PG_2,DMP_PG_1+0x400
339 00000000 .set DMP_PG_3,DMP_PG_2+0x400
340 00000000 .set DMP_PG_4,DMP_PG_3+0x400
341 00000000 .set DMP_PG_5,DMP_PG_4+0x400
342 00000000 .set DMP_PG_6,DMP_PG_5+0x400
343 00000000 .set DMP_PG_7,DMP_PG_6+0x400
344 00000000 .set DMP_PG_8,DMP_PG_7+0x400
345 00000000 .set DMP_PG_9,DMP_PG_8+0x400
346 00000000 .set DMP_PG_10,DMP_PG_9+0x400
347 00000000 .set DMP_PG_11,DMP_PG_10+0x400
348 00000000 .set DMP_PG_12,DMP_PG_11+0x400
349 00000000 .set DMP_PG_13,DMP_PG_12+0x400
350 00000000
351 00000000
352 00000000 # test code space for the address / demand page tests
353 00000000
354 00000000 .set START_OF_CODE,DMP_PG_1-20
355 00000000 .set CODE_BUF_SIZE,40
356 00000000 .set END_OF_CODE,START_OF_CODE+CODE_BUF_SIZE
357 00000000
358 00000000
359 00000000 # data locations used by the event and demand page tests
360 00000000
361 00000000 .set _dmp_byte_op_1,DMP_PG_1+0x30
362 00000000 .set _dmp_byte_op_2,DMP_PG_1+0x50
363 00000000 .set _dmp_byte_op_3,DMP_PG_1+0x70
364 00000000 .set _dmp_op_1,DMP_PG_3-4
365 00000000 .set _dmp_op_1_ptr,DMP_PG_4+0x30
366 00000000 .set _dmp_op_2_ptr,DMP_PG_5+0x30
367 00000000 .set _dmp_op_2,DMP_PG_7-4
368 00000000 .set _dmp_op_3,DMP_PG_8
369 00000000 .set _dmp_op_3_ptr,DMP_PG_9+0x30
370 00000000 .set _dmp_op_4,DMP_PG_10
371 00000000 .set _dmp_op_5,DMP_PG_11
372 00000000 .set _sp_minus,DMP_PG_13-4
373 00000000 .set _sp_page,DMP_PG_13
374 00000000 .set _sp_plus,DMP_PG_13+4
375 00000000
376 00000000
377 00000000
378 00000000
379 00000000
380 00000000
381 00000000
382 00000000
383 00000000
384 00000000
385 00000000
386 00000000 # INIT.X for the FPP Events Tests
387 00000000
388 00000000 # This file is a diagnostic version of locore.s.
389 00000000 # It contains the following:
390 00000000 # *system data area = scb, dump buffer, interrupt stack,
391 00000000 # *system page table,user page tables,pcbs,iomap, & io buffers.
392 00000000 #
393 00000000 # *system code = interrupt vectors, initialization of system data,
394 00000000 # *memory size calculation,initialization of SPT, zeroing of
395 00000000 # *unused memory, & loading of SBR & SLR.
396 00000000 # *
397 00000000 # *at the end of this code, you are ready to go to virtual mode.
398 00000000 # * --- GOOD LUCK!
399 00000000
400 00000000 ##########################################################################
401 00000000
402 00000000 # 22-Mar-85 : Stole the code from the Demand Paging Test directory
403 00000000 # 16-Jul-85 : Added the test for the FPP WCS / NO-FPP WCS
404 00000000
405 00000000 ##########################################################################
406 00000000
407 00000000
408 00000000
409 00000000
410 00000000 # 1 "./prvreg.h"
1 00000000
2 00000000
3 00000000
4 00000000
5 00000000
6 00000000
7 00000000
8 00000000 .set SBR,0
9 00000000 .set SLR,1
10 00000000 .set P0BR,2
11 00000000 .set P0LR,3
12 00000000 .set P1BR,4
13 00000000 .set P1LR,5
14 00000000 .set P2BR,6
15 00000000 .set P2LR,7
16 00000000 .set IPL,8
17 00000000 .set MME,9
18 00000000 .set TBIA,10
19 00000000
20 00000000 .set TBIS,11
21 00000000
22 00000000 .set DCK,12
23 00000000 .set CCK,13
24 00000000
25 00000000
26 00000000 .set PCBB,14
27 00000000 .set ISP,15
28 00000000 .set SIRR,16
29 00000000 .set SISR,17
30 00000000 .set SCBB,18
31 00000000 .set KSP,19
32 00000000 .set USP,20
33 00000000 .set DCB,21
34 00000000 .set PACC,23
35 00000000
36 00000000 .set P1DC,24
37 00000000 .set PADC,25
38 00000000
39 00000000 .set HISR,26
40 00000000 .set DCR,27
41 00000000 .set PDCS,28
42 00000000 # 410 ""
410 00000000
411 00000000
412 00000000
413 00000000 # 1 "./psl.h"
1 00000000
2 00000000
3 00000000
4 00000000
5 00000000
6 00000000
7 00000000
8 00000000
9 00000000
10 00000000
11 00000000
12 00000000
13 00000000
14 00000000
15 00000000
16 00000000
17 00000000
18 00000000
19 00000000
20 00000000
21 00000000
22 00000000
23 00000000
24 00000000
25 00000000
26 00000000 # 413 ""
413 00000000
414 00000000
415 00000000
416 00000000 # 1 "./pte.h"
1 00000000
2 00000000
3 00000000
4 00000000
5 00000000
6 00000000
7 00000000
8 00000000
9 00000000
10 00000000
11 00000000
12 00000000
13 00000000
14 00000000
15 00000000
16 00000000
17 00000000
18 00000000
19 00000000
20 00000000
21 00000000
22 00000000
23 00000000
24 00000000
25 00000000
26 00000000
27 00000000
28 00000000
29 00000000
30 00000000 # 416 ""
416 00000000
417 00000000
418 00000000
419 00000000 # 1 "./pcboffset.h"
1 00000000
2 00000000
3 00000000
4 00000000
5 00000000
6 00000000 .set PCB_KSP, 0
7 00000000 .set PCB_USP, 4
8 00000000 .set PCB_R0, 8
9 00000000 .set PCB_R1, 12
10 00000000 .set PCB_R2, 16
11 00000000 .set PCB_R3, 20
12 00000000 .set PCB_R4, 24
13 00000000 .set PCB_R5, 28
14 00000000 .set PCB_R6, 32
15 00000000 .set PCB_R7, 36
16 00000000 .set PCB_R8, 40
17 00000000 .set PCB_R9, 44
18 00000000 .set PCB_R10, 48
19 00000000 .set PCB_R11, 52
20 00000000 .set PCB_R12, 56
21 00000000 .set PCB_R13, 60
22 00000000 .set PCB_PC, 64
23 00000000 .set PCB_PSL, 68
24 00000000 .set PCB_P0BR, 72
25 00000000 .set PCB_P0LR, 76
26 00000000 .set PCB_P1BR, 80
27 00000000 .set PCB_P1LR, 84
28 00000000 .set PCB_P2BR, 88
29 00000000 .set PCB_P2LR, 92
30 00000000
31 00000000
32 00000000
33 00000000 .set PCB_STAT, 96
34 00000000
35 00000000
36 00000000 # 419 ""
419 00000000
420 00000000
421 00000000
422 00000000 # 1 "./const.h"
1 00000000
2 00000000
3 00000000
4 00000000
5 00000000
6 00000000
7 00000000
8 00000000
9 00000000
10 00000000
11 00000000
12 00000000
13 00000000
14 00000000
15 00000000
16 00000000
17 00000000
18 00000000
19 00000000
20 00000000
21 00000000
22 00000000
23 00000000
24 00000000
25 00000000
26 00000000
27 00000000
28 00000000
29 00000000
30 00000000
31 00000000
32 00000000
33 00000000
34 00000000
35 00000000
36 00000000
37 00000000
38 00000000
39 00000000
40 00000000
41 00000000
42 00000000
43 00000000
44 00000000
45 00000000
46 00000000
47 00000000
48 00000000
49 00000000
50 00000000
51 00000000 # 422 ""
422 00000000
423 00000000
424 00000000
425 00000000 # 1 "./scboffset.h"
1 00000000
2 00000000
3 00000000
4 00000000
5 00000000 .set PFVEC,4
6 00000000 .set CLOCKVEC,28
7 00000000 .set CRVEC,40
8 00000000 .set CXVEC,44
9 00000000 .set SIVEC1,120
10 00000000
11 00000000
12 00000000 .set BEVEC,128
13 00000000 .set SYSVEC,172
14 00000000 .set PINSTVEC,176
15 00000000 .set ROVEC,180
16 00000000 .set RAVEC,184
17 00000000 .set PROTVEC,188
18 00000000
19 00000000 .set TRANS,0x30
20 00000000 .set TRANSVEC,192
21 00000000
22 00000000 .set KSPVEC,196
23 00000000 .set TRACEVEC,200
24 00000000 .set BPTVEC,204
25 00000000 .set ARITHVEC,208
26 00000000 .set ALIGNVEC,212
27 00000000 .set FPMVEC,220
28 00000000 .set IO14VEC,256
29 00000000 .set IO15VEC,320
30 00000000 .set IO16VEC,384
31 00000000 .set IO17VEC,448
32 00000000
33 00000000 # 425 ""
425 00000000
426 00000000
427 00000000 # 1 "./sptoffset.h"
1 00000000
2 00000000
3 00000000
4 00000000
5 00000000
6 00000000
7 00000000
8 00000000
9 00000000 .set SCBPTE,8
10 00000000 .set BUFPTE,12
11 00000000 .set ISPTE,16
12 00000000 .set IS1PTE,20
13 00000000 .set SPTPTE,20
14 00000000 .set SPT1PTE,20
15 00000000 .set IOMAPPTE,24
16 00000000 .set PCBPTE,28
17 00000000 .set U0P0PTE,32
18 00000000 .set U0P1PTE,36
19 00000000 .set U0P2PTE,40
20 00000000 .set U1P0PTE,44
21 00000000 .set U1P1PTE,48
22 00000000 .set U1P2PTE,52
23 00000000 .set U2P0PTE,56
24 00000000 .set U2P1PTE,60
25 00000000 .set U2P2PTE,64
26 00000000 .set U3P0PTE,68
27 00000000 .set U3P1PTE,72
28 00000000 .set U3P2PTE,76
29 00000000 .set U4P0PTE,80
30 00000000 .set U4P1PTE,84
31 00000000 .set U4P2PTE,88
32 00000000 .set U5P0PTE,92
33 00000000 .set U5P1PTE,96
34 00000000 .set U5P2PTE,100
35 00000000 .set U6P0PTE,104
36 00000000 .set U6P1PTE,108
37 00000000 .set U6P2PTE,112
38 00000000 .set U7P0PTE,116
39 00000000 .set U7P1PTE,120
40 00000000 .set U7P2PTE,124
41 00000000 .set IOB0PTE,128
42 00000000 .set IOB1PTE,132
43 00000000 .set IOB2PTE,136
44 00000000 .set IOB3PTE,140
45 00000000 .set IOB4PTE,144
46 00000000 .set IOB5PTE,148
47 00000000 .set IOB6PTE,152
48 00000000 .set IOB7PTE,156
49 00000000
50 00000000
51 00000000 # 427 ""
427 00000000
428 00000000
429 00000000
430 00000000 # 1 "./trap.h"
1 00000000
2 00000000
3 00000000
4 00000000
5 00000000
6 00000000
7 00000000
8 00000000
9 00000000
10 00000000
11 00000000
12 00000000
13 00000000
14 00000000
15 00000000
16 00000000
17 00000000 # 430 ""
430 00000000
431 00000000
432 00000000
433 00000000
434 00000000
435 00000000 .set HIGH,0x1f
436 00000000 .set MCKVEC,4
437 00000000 .set NISP,2
438 00000000 .set DONE,255
439 00000000 .set TTRAP,0x32
440 00000000 .set TRANS,0x30
441 00000000 .set PRIVS,0x2c
442 00000000
443 00000000 .text
444 00000000
445 00000000
446 00000000
447 00000000 # 1 "./pstorage.s"
1 00000000 #
2 00000000
3 00000000
4 00000000
5 00000000
6 00000000
7 00000000
8 00000000
9 00000000
10 00000000
11 00000000
12 00000000
13 00000000
14 00000000
15 00000000
16 00000000
17 00000000
18 00000000
19 00000000
20 00000000 _pstore:
21 00000000 .globl _pstore
22 00000000 **** .space 1024
23 00000400
24 00000400 _pstore1:
25 00000400 .globl _pstore1
26 00000400
27 00000400 **** _pcbb: .space 4
28 00000404 .globl _isp
29 00000404 **** _isp: .space 4
30 00000408 **** _sirr: .space 4
31 0000040C .globl _sisr
32 0000040C **** _sisr: .space 4
33 00000410
34 00000410 **** .space 4
35 00000414 **** .space 4
36 00000418 **** .space 4
37 0000041C
38 0000041C **** _cpmdcb: .space 4
39 00000420 **** _cpfdcb: .space 4
40 00000424 **** _cpcdcb: .space 4
41 00000428 **** _cpidcb: .space 4
42 0000042C **** _cpstat: .space 4
43 00000430 **** _cpctl: .space 4
44 00000434
45 00000434 .globl _hisr
46 00000434 **** _hisr: .space 4
47 00000438 **** _dcr: .space 4
48 0000043C
49 0000043C **** .space 4*48
50 000004FC
51 000004FC _pstemp:
52 000004FC .globl _pstemp
53 000004FC
54 000004FC **** _tr0: .space 16
55 0000050C
56 0000050C **** _tpc: .space 4
57 00000510 **** _tpsl: .space 4
58 00000514 **** _tsp: .space 4
59 00000518 **** _tksp: .space 4
60 0000051C **** _tusp: .space 4
61 00000520 **** _tcck: .space 4
62 00000524 **** _tdck: .space 4
63 00000528 **** _ttbk: .space 4
64 0000052C **** _tsbr: .space 4
65 00000530 **** _tslr: .space 4
66 00000534 **** _tp0br: .space 4
67 00000538 **** _tp0lr: .space 4
68 0000053C **** _tp1br: .space 4
69 00000540 **** _tp1lr: .space 4
70 00000544 **** _tp2br: .space 4
71 00000548 **** _tp2lr: .space 4
72 0000054C **** _tipl: .space 4
73 00000550 **** _tmme: .space 4
74 00000554 **** _ttbia: .space 4
75 00000558 **** _ttbis: .space 4
76 0000055C
77 0000055C
78 0000055C **** _tpcbb: .space 4
79 00000560 **** _tisp: .space 4
80 00000564 **** _tsirr: .space 4
81 00000568 **** _tsisr: .space 4
82 0000056C **** _tscbb: .space 4
83 00000570 **** _tp1cc: .space 4
84 00000574
85 00000574 **** _tpacc: .space 4
86 00000578
87 00000578 **** _tp1dc: .space 4
88 0000057C **** _tpadc: .space 4
89 00000580 _tcpmdcb:
90 00000580 **** .space 4
91 00000584 _tcpfdcb:
92 00000584 **** .space 4
93 00000588 _tcpcdcb:
94 00000588 **** .space 4
95 0000058C _tcpidcb:
96 0000058C **** .space 4
97 00000590 _tcpstat:
98 00000590 **** .space 4
99 00000594 _tcpctl:
100 00000594 **** .space 4
101 00000598
102 00000598 _probflag:
103 00000598 **** .space 4
104 0000059C _inexcflg:
105 0000059C **** .space 4
106 000005A0
107 000005A0 **** .space 4*10
108 000005C8 _psend: .globl _psend
109 000005C8 .set MM,(_psend - _pstore1)
110 000005C8 **** .space 1024 - MM
111 00000800
112 00000800
113 00000800 #
114 00000800
115 00000800
116 00000800
117 00000800
118 00000800
119 00000800 .set PCBB,0x400 #process control block base
120 00000800
121 00000800 .globl INTSP
122 00000800 .set INTSP,0x404 #Interrupt stack pointer
123 00000800 .set SIRR,0x408 #Software interrupt request
124 00000800
125 00000800 .globl SSR
126 00000800 .set SSR,0x40C #Software interrupt summary
127 00000800
128 00000800 .globl HSR
129 00000800 .set HSR,0x410 #Hardware interrupt summary
130 00000800
131 00000800 .set SBB,0x414 #Pointer to system control block base
132 00000800 .set TBCR,0x418 #Current value of hardware TBCR
133 00000800 .set CPMDCB,0x420 #pointer to CP master DCB
134 00000800 .set CPCTL,0x424 #CPU control word
135 00000800 .set CPREQ,0x428 #CPU request
136 00000800 .set CPRUN,0x42C #CPU run status (8 = step mode)
137 00000800 .set CPRSW,0x430 #CP interrupt request word
138 00000800 .set PSL,0x434 #Software Process Status Longword
139 00000800 .set TVAPR,0x5E8 #saved vapr register
140 00000800 .set TRA,0x5EC #
141 00000800 .set TLSP,0x5F0 #
142 00000800 .set TIAR,0x5F4 #
143 00000800 .set TLIA,0x5F8 #
144 00000800 .set TQ,0x5FC #
145 00000800 .set TR0,0x600 #decellerated processor registers
146 00000800 .set TR1,0x604 #decellerated processor registers
147 00000800 .set TR2,0x608 #decellerated processor registers
148 00000800 .set TR3,0x60C #decellerated processor registers
149 00000800 .set TR4,0x610 #decellerated processor registers
150 00000800 .set TR5,0x614 #decellerated processor registers
151 00000800 .set TR6,0x618 #decellerated processor registers
152 00000800 .set TR7,0x61C #decellerated processor registers
153 00000800 .set TR8,0x620 #decellerated processor registers
154 00000800 .set TR9,0x624 #decellerated processor registers
155 00000800 .set TR10,0x628 #decellerated processor registers
156 00000800 .set TR11,0x62C #decellerated processor registers
157 00000800 .set TR12,0x630 #decellerated processor registers
158 00000800 .set TR13,0x634 #decellerated processor registers
159 00000800 .set TR14,0x638 #decellerated processor registers
160 00000800 .set TR15,0x63C #decellerated processor registers
161 00000800 .set TPC,0x640 #decellerated program counter
162 00000800 .set TPSL,0x644 #decellerated process status longword
163 00000800 .set TSP,0x648 #decellerated stack pointer
164 00000800 .set TKSP,0x64C #decellerated kernel stack pointer
165 00000800 .set TUSP,0x650 #decellerated user stack pointer
166 00000800 .globl TCCK
167 00000800 .set TCCK,0x654 #decellerated Code cache key
168 00000800 .globl TDCK
169 00000800 .set TDCK,0x658 #decellerated data cache key
170 00000800 .set TTBK,0x65C #decellerated translation buffer key
171 00000800 .set TSBR,0x660 #decellerated System Base Register
172 00000800 .set TSLR,0x664 #decellerated System length register
173 00000800 .set TP0BR,0x668 #decellerated P0 base register
174 00000800 .set TP0LR,0x66C #decellerated P0 length register
175 00000800 .set TP1BR,0x670 #decellerated P1 base register
176 00000800 .set TP1LR,0x674 #decellerated P1 length register
177 00000800 .set TP2BR,0x678 #decellerated P2 base register
178 00000800 .set TP2LR,0x67C #decellerated P1 length register
179 00000800 .set TIPL,0x680 #decellerated Interrupt priority level
180 00000800 .set TMME,0x684 #decellerated Memory management enable
181 00000800 .set TTBIA,0x68C #decellerated translation buffer invalid
182 00000800 .set TTBIS,0x68C #decellerated transl buffer invalid single
183 00000800 .set TPCBB,0x690 #decellerated Process control block base
184 00000800 .set TISP,0x694 #decellerated Interrupt stack pointer
185 00000800 .set TSIRR,0x698 #decellerated Software interrupt request
186 00000800 .set TSISR,0x69C #decellerated Software interrupt summary
187 00000800 .set TSCBB,0x6A0 #decellerated System control block base
188 00000800 .set TP1CC,0x6A4 #decellerated
189 00000800 .set TPACC,0x6A8 #decellerated
190 00000800 .set TP1DC,0x6AC #decellerated
191 00000800 .set TPADC,0x6B0 #decellerated
192 00000800 .set TCPMDCB,0x6B4 #decellerated address of master DCB
193 00000800 .set PROBFLG,0x6B8 #decellerated
194 00000800 .set INEXCFLG,0x6BC #decellerated
195 00000800 .set PCTYPFLG,0x6C0 #
196 00000800 .set NOOFPARS,0x6C4 #
197 00000800 .set STKPAR1,0x6C8 #
198 00000800 .set STKPAR2,0x6CC #
199 00000800 .set JMPVEC,0x6D0 #
200 00000800 .set PSEND,0x7FC #
201 00000800 # 447 ""
447 00000800
448 00000800 .globl _Entry
449 00000800 _Entry:
450 00000800 71 ef0000a34c jmp start
451 00000806 **** .space (1024-6)
452 00000C00
453 00000C00
454 00000C00
455 00000C00
456 00000C00
457 00000C00
458 00000C00
459 00000C00 .set NLWU,35
460 00000C00
461 00000C00
462 00000C00
463 00000C00 .globl _Codek
464 00000C00 00000000 _Codek: .long 0
465 00000C04
466 00000C04 .globl _restart
467 00000C04 _restart:
468 00000C04 **** .space 4
469 00000C08
470 00000C08
471 00000C08
472 00000C08 .globl _maxmem
473 00000C08 _maxmem:
474 00000C08 **** .space 4
475 00000C0C
476 00000C0C .globl _maxpages
477 00000C0C _maxpages:
478 00000C0C **** .space 4
479 00000C10
480 00000C10 .globl _lastadd
481 00000C10 _lastadd:
482 00000C10 **** .space 4
483 00000C14
484 00000C14 .globl _unused
485 00000C14 _unused:
486 00000C14 **** .space 4
487 00000C18
488 00000C18 .globl _ctlblk
489 00000C18 _ctlblk:
490 00000C18 00000000 .long 0
491 00000C1C
492 00000C1C .globl _savvec0
493 00000C1C _savvec0:
494 00000C1C **** .space 4
495 00000C20
496 00000C20 .globl _savvec1
497 00000C20 _savvec1:
498 00000C20 **** .space 4
499 00000C24
500 00000C24 .globl _savvec2
501 00000C24 _savvec2:
502 00000C24 **** .space 4
503 00000C28
504 00000C28 .globl _savvec3
505 00000C28 _savvec3:
506 00000C28 **** .space 4
507 00000C2C
508 00000C2C .globl _savvec4
509 00000C2C _savvec4:
510 00000C2C **** .space 4
511 00000C30
512 00000C30 .globl _savvec5
513 00000C30 _savvec5:
514 00000C30 **** .space 4
515 00000C34 .globl _savvec6
516 00000C34 _savvec6:
517 00000C34 **** .space 4
518 00000C38 .globl _savvec7
519 00000C38 _savvec7:
520 00000C38 **** .space 4
521 00000C3C
522 00000C3C .globl _savvec8
523 00000C3C _savvec8:
524 00000C3C **** .space 4
525 00000C40
526 00000C40 .globl _r_no
527 00000C40 _r_no:
528 00000C40 00000000 .long 0
529 00000C44 .globl _pt_base
530 00000C44 _pt_base:
531 00000C44 00000000 .long 0
532 00000C48 .globl _saved_psl
533 00000C48 _saved_psl:
534 00000C48 00000000 .long 0
535 00000C4C .globl _saved_sp
536 00000C4C _saved_sp:
537 00000C4C 00000000 .long 0
538 00000C50 .globl _saved_fp
539 00000C50 _saved_fp:
540 00000C50 00000000 .long 0
541 00000C54 .globl _ret_adr
542 00000C54 _ret_adr:
543 00000C54 00000000 .long 0
544 00000C58 .globl _exp_par0
545 00000C58 _exp_par0:
546 00000C58 00000000 .long 0
547 00000C5C .globl _exp_par1
548 00000C5C _exp_par1:
549 00000C5C 00000000 .long 0
550 00000C60 .globl _f_vaddr
551 00000C60 _f_vaddr:
552 00000C60 00000000 .long 0
553 00000C64
554 00000C64 .globl _f_ptr
555 00000C64 _f_ptr:
556 00000C64 00000000 .long 0
557 00000C68 .globl _df_cnt
558 00000C68 _df_cnt:
559 00000C68 00000000 .long 0
560 00000C6C
561 00000C6C .globl _if_cnt
562 00000C6C _if_cnt:
563 00000C6C 00000000 .long 0
564 00000C70
565 00000C70 .globl _newepc
566 00000C70 _newepc:
567 00000C70 00000000 .long 0
568 00000C74
569 00000C74 .globl _errcnt
570 00000C74 _errcnt:
571 00000C74 00000000 .long 0
572 00000C78
573 00000C78 .globl _clk_cnt
574 00000C78 _clk_cnt:
575 00000C78 00000000 .long 0
576 00000C7C
577 00000C7C .globl _ttcnt
578 00000C7C _ttcnt:
579 00000C7C 00000000 .long 0
580 00000C80 .globl _trcnt
581 00000C80 _trcnt:
582 00000C80 00000000 .long 0
583 00000C84
584 00000C84 .globl _Ufpte
585 00000C84 00000000 _Ufpte: .long 0
586 00000C88 .globl _Ulpte
587 00000C88 00000000 _Ulpte: .long 0
588 00000C8C
589 00000C8C .globl _dbuf
590 00000C8C _dbuf:
591 00000C8C **** .space 1024 - (NLWU *4)
592 00001000 edbuf:
593 00001000
594 00001000
595 00001000 .globl _intstack
596 00001000 _intstack:
597 00001000 **** .space NISP* 1024
598 00001800 eintstack:
599 00001800
600 00001800
601 00001800 .set SYSPTSIZE,512
602 00001800
603 00001800
604 00001800
605 00001800
606 00001800 .align 2
607 00001800 .globl _Sysmap
608 00001800 _Sysmap:
609 00001800 **** .space SYSPTSIZE*4
610 00002000 eSysmap:
611 00002000 .globl _Syssize
612 00002000 .set _Syssize,(eSysmap-_Sysmap)/4
613 00002000
614 00002000 .globl _iomap
615 00002000 **** _iomap: .space 1024
616 00002400 .globl _eiomap
617 00002400 _eiomap:
618 00002400
619 00002400 .globl _pcb0
620 00002400 **** _pcb0: .space 128
621 00002480 .globl _pcb1
622 00002480 **** _pcb1: .space 128
623 00002500 .globl _pcb2
624 00002500 **** _pcb2: .space 128
625 00002580 .globl _pcb3
626 00002580 **** _pcb3: .space 128
627 00002600 .globl _pcb4
628 00002600 **** _pcb4: .space 128
629 00002680 .globl _pcb5
630 00002680 **** _pcb5: .space 128
631 00002700 .globl _pcb6
632 00002700 **** _pcb6: .space 128
633 00002780 .globl _pcb7
634 00002780 **** _pcb7: .space 128
635 00002800
636 00002800
637 00002800
638 00002800
639 00002800
640 00002800 .align 2
641 00002800 .globl _u0p0pt
642 00002800 _u0p0pt:
643 00002800 **** .space 1024
644 00002C00 .globl _u0p1pt
645 00002C00 _u0p1pt:
646 00002C00 **** .space 1024
647 00003000 .globl _u0p2pt
648 00003000 _u0p2pt:
649 00003000 **** .space 1020
650 000033FC eu0p2pt:
651 000033FC **** .space 4
652 00003400
653 00003400
654 00003400
655 00003400
656 00003400
657 00003400 .align 2
658 00003400 .globl _u1p0pt
659 00003400 _u1p0pt:
660 00003400 **** .space 1024
661 00003800 .globl _u1p1pt
662 00003800 _u1p1pt:
663 00003800 **** .space 1024
664 00003C00 .globl _u1p2pt
665 00003C00 _u1p2pt:
666 00003C00 **** .space 1020
667 00003FFC eu1p2pt:
668 00003FFC **** .space 4
669 00004000
670 00004000
671 00004000
672 00004000
673 00004000
674 00004000
675 00004000 .align 2
676 00004000 .globl _u2p0pt
677 00004000 _u2p0pt:
678 00004000 **** .space 1024
679 00004400 .globl _u2p1pt
680 00004400 _u2p1pt:
681 00004400 **** .space 1024
682 00004800 .globl _u2p2pt
683 00004800 _u2p2pt:
684 00004800 **** .space 1020
685 00004BFC eu2p2pt:
686 00004BFC **** .space 4
687 00004C00
688 00004C00
689 00004C00
690 00004C00
691 00004C00
692 00004C00
693 00004C00 .align 2
694 00004C00 .globl _u3p0pt
695 00004C00 _u3p0pt:
696 00004C00 **** .space 1024
697 00005000 .globl _u3p1pt
698 00005000 _u3p1pt:
699 00005000 **** .space 1024
700 00005400 .globl _u3p2pt
701 00005400 _u3p2pt:
702 00005400 **** .space 1020
703 000057FC eu3p2pt:
704 000057FC **** .space 4
705 00005800
706 00005800
707 00005800
708 00005800
709 00005800
710 00005800 .globl _u4p0pt
711 00005800 _u4p0pt:
712 00005800 **** .space (9* 1024) - 4
713 00007BFC eu6p2pt:
714 00007BFC **** .space 4
715 00007C00
716 00007C00
717 00007C00
718 00007C00
719 00007C00
720 00007C00
721 00007C00 .align 2
722 00007C00 .globl _Kstack
723 00007C00 _Kstack:
724 00007C00 **** .space 3* 1024
725 00008800 .globl ekstack
726 00008800 ekstack:
727 00008800
728 00008800
729 00008800 .globl _iob0
730 00008800 **** _iob0: .space 1024
731 00008C00 .globl _iob1
732 00008C00 **** _iob1: .space 1024
733 00009000 .globl _iob2
734 00009000 **** _iob2: .space 1024
735 00009400 .globl _iob3
736 00009400 **** _iob3: .space 1024
737 00009800 .globl _iob4
738 00009800 **** _iob4: .space 1024
739 00009C00 .globl _iob5
740 00009C00 **** _iob5: .space 1024
741 0000A000 .globl _iob6
742 0000A000 **** _iob6: .space 1024
743 0000A400 esysdata:
744 0000A400
745 0000A400
746 0000A400
747 0000A400 # 1 "./scblock.s"
1 0000A400
2 0000A400 #
3 0000A400
4 0000A400
5 0000A400 .align 2
6 0000A400 .globl _scb
7 0000A400 _scb:
8 0000A400
9 0000A400
10 0000A400
11 0000A400
12 0000A400
13 0000A400
14 0000A400
15 0000A400 0000a800 0000a80c .long _Xunknown; .long _Xpowerfail;
16 0000A408 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
17 0000A410 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
18 0000A418 0000a800 0000a818 .long _Xunknown; .long _Xhardclock;
19 0000A420 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
20 0000A428 0000a820 0000a82c .long _Xcnrint; .long _Xcnxint;
21 0000A430 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
22 0000A438 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
23 0000A440 0000a830 0000a83c .long _Xs15; .long _Xs14;
24 0000A448 0000a848 0000a854 .long _Xs13; .long _Xs12;
25 0000A450 0000a860 0000a86c .long _Xs11; .long _Xs10;
26 0000A458 0000a878 0000a884 .long _Xs9; .long _Xs8;
27 0000A460 0000a890 0000a89c .long _Xs7; .long _Xs6;
28 0000A468 0000a8a8 0000a8b4 .long _Xs5; .long _Xs4;
29 0000A470 0000a8c0 0000a8cc .long _Xs3; .long _Xs2;
30 0000A478 0000a8d8 0000a800 .long _Xs1; .long _Xunknown;
31 0000A480 0000a8f4 0000a800 .long _Xbuserror; .long _Xunknown;
32 0000A488 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
33 0000A490 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
34 0000A498 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
35 0000A4A0 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
36 0000A4A8 0000a800 0000ab48 .long _Xunknown; .long _Xkcall;
37 0000A4B0 0000a90c 0000a950 .long _Xprvinflt; .long _Xresopflt;
38 0000A4B8 0000a99c 0000aa70 .long _Xresadflt; .long _Xprotflt;
39 0000A4C0 0000aa88 0000a900 .long _Xtransflt; .long _Xkspnotval;
40 0000A4C8 0000a9ec 0000a9e0 .long _Xtracep; .long _Xbptflt;
41 0000A4D0 0000aa24 0000aa94 .long _Xarithtrap; .long _Xalignflt;
42 0000A4D8 0000a800 0000aacc .long _Xunknown; .long _Xfpp_emulate;
43 0000A4E0 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
44 0000A4E8 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
45 0000A4F0 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
46 0000A4F8 0000a800 0000a800 .long _Xunknown; .long _Xunknown;
47 0000A500 0000a8e4 0000a800 .long _Xiovec14; .long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xun000177C0 ng _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;
0000a800 0000a800
0000a800 0000a800
0000a800 0000a800
0000a800 0000a800
0000a800 0000a800
0000a800 0000a800
0000a800 0000a800
48 0000A540 0000a8e8 0000a800 .long _Xiovec15; .long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xu000177C0 ong _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;
0000a800 0000a800
0000a800 0000a800
0000a800 0000a800
0000a800 0000a800
0000a800 0000a800
0000a800 0000a800
0000a800 0000a800
49 0000A580 0000a8ec 0000a800 .long _Xiovec16; .long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xu000177C0 ong _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;
0000a800 0000a800
0000a800 0000a800
0000a800 0000a800
0000a800 0000a800
0000a800 0000a800
0000a800 0000a800
0000a800 0000a800
50 0000A5C0 0000a8f0 0000a800 .long _Xiovec17; .long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xu000177C0 ong _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;.long _Xunknown;
0000a800 0000a800
0000a800 0000a800
0000a800 0000a800
0000a800 0000a800
0000a800 0000a800
0000a800 0000a800
0000a800 0000a800
51 0000A600
52 0000A600 **** .space 512
53 0000A800
54 0000A800
55 0000A800 # 747 ""
747 0000A800
748 0000A800
749 0000A800
750 0000A800
751 0000A800 # 1 "./evthandlers.s"
1 0000A800
2 0000A800
3 0000A800
4 0000A800
5 0000A800
6 0000A800
7 0000A800
8 0000A800
9 0000A800
10 0000A800
11 0000A800
12 0000A800
13 0000A800
14 0000A800
15 0000A800
16 0000A800
17 0000A800
18 0000A800
19 0000A800
20 0000A800
21 0000A800
22 0000A800
23 0000A800
24 0000A800
25 0000A800
26 0000A800
27 0000A800
28 0000A800
29 0000A800
30 0000A800
31 0000A800
32 0000A800
33 0000A800
34 0000A800
35 0000A800
36 0000A800
37 0000A800
38 0000A800
39 0000A800 .align 2 .globl _Xunknown _Xunknown:
40 0000A800 dd 00 pushl $0
41 0000A802 fe 08 efffff57f7 callf $8,_XTrap
42 0000A809 00 halt
43 0000A80A
44 0000A80A
45 0000A80A
46 0000A80A
47 0000A80A
48 0000A80A
49 0000A80A
50 0000A80A
51 0000A80A
52 0000A80A
53 0000A80A
54 0000A80A
55 0000A80A 0000 .align 2 .globl _Xpowerfail _Xpowerfail:
56 0000A80C dd 01 pushl $1
57 0000A80E fe 08 efffff57eb callf $8,_XTrap
58 0000A815 00 halt
59 0000A816
60 0000A816
61 0000A816
62 0000A816
63 0000A816
64 0000A816
65 0000A816 0000 .align 2 .globl _Xhardclock _Xhardclock:
66 0000A818 6d efffff57e2 incl _clock_event
67 0000A81E 20 rei
68 0000A81F
69 0000A81F
70 0000A81F
71 0000A81F
72 0000A81F
73 0000A81F 00 .align 2 .globl _Xcnrint _Xcnrint:
74 0000A820 dd 0a pushl $0xa
75 0000A822 fe 08 efffff57d7 callf $8,_XTrap
76 0000A829 00 halt
77 0000A82A
78 0000A82A
79 0000A82A
80 0000A82A
81 0000A82A 0000 .align 2 .globl _Xcnxint _Xcnxint:
82 0000A82C 20 rei
83 0000A82D
84 0000A82D
85 0000A82D
86 0000A82D
87 0000A82D 000000 .align 2 .globl _Xs15 _Xs15:
88 0000A830 dd 10 pushl $0x10
89 0000A832 fe 08 efffff57c7 callf $8,_XTrap
90 0000A839 00 halt
91 0000A83A
92 0000A83A
93 0000A83A
94 0000A83A
95 0000A83A 0000 .align 2 .globl _Xs14 _Xs14:
96 0000A83C dd 11 pushl $0x11
97 0000A83E fe 08 efffff57bb callf $8,_XTrap
98 0000A845 00 halt
99 0000A846
100 0000A846
101 0000A846
102 0000A846
103 0000A846 0000 .align 2 .globl _Xs13 _Xs13:
104 0000A848 dd 12 pushl $0x12
105 0000A84A fe 08 efffff57af callf $8,_XTrap
106 0000A851 00 halt
107 0000A852
108 0000A852
109 0000A852
110 0000A852
111 0000A852 0000 .align 2 .globl _Xs12 _Xs12:
112 0000A854 dd 13 pushl $0x13
113 0000A856 fe 08 efffff57a3 callf $8,_XTrap
114 0000A85D 00 halt
115 0000A85E
116 0000A85E
117 0000A85E
118 0000A85E
119 0000A85E 0000 .align 2 .globl _Xs11 _Xs11:
120 0000A860 dd 14 pushl $0x14
121 0000A862 fe 08 efffff5797 callf $8,_XTrap
122 0000A869 00 halt
123 0000A86A
124 0000A86A
125 0000A86A
126 0000A86A
127 0000A86A 0000 .align 2 .globl _Xs10 _Xs10:
128 0000A86C dd 15 pushl $0x15
129 0000A86E fe 08 efffff578b callf $8,_XTrap
130 0000A875 00 halt
131 0000A876
132 0000A876
133 0000A876
134 0000A876
135 0000A876 0000 .align 2 .globl _Xs9 _Xs9:
136 0000A878 dd 16 pushl $0x16
137 0000A87A fe 08 efffff577f callf $8,_XTrap
138 0000A881 00 halt
139 0000A882
140 0000A882
141 0000A882
142 0000A882
143 0000A882 0000 .align 2 .globl _Xs8 _Xs8:
144 0000A884 dd 17 pushl $0x17
145 0000A886 fe 08 efffff5773 callf $8,_XTrap
146 0000A88D 00 halt
147 0000A88E
148 0000A88E
149 0000A88E
150 0000A88E
151 0000A88E 0000 .align 2 .globl _Xs7 _Xs7:
152 0000A890 dd 18 pushl $0x18
153 0000A892 fe 08 efffff5767 callf $8,_XTrap
154 0000A899 00 halt
155 0000A89A
156 0000A89A
157 0000A89A
158 0000A89A
159 0000A89A 0000 .align 2 .globl _Xs6 _Xs6:
160 0000A89C dd 19 pushl $0x19
161 0000A89E fe 08 efffff575b callf $8,_XTrap
162 0000A8A5 00 halt
163 0000A8A6
164 0000A8A6
165 0000A8A6
166 0000A8A6
167 0000A8A6 0000 .align 2 .globl _Xs5 _Xs5:
168 0000A8A8 dd 1a pushl $0x1a
169 0000A8AA fe 08 efffff574f callf $8,_XTrap
170 0000A8B1 00 halt
171 0000A8B2
172 0000A8B2
173 0000A8B2
174 0000A8B2
175 0000A8B2 0000 .align 2 .globl _Xs4 _Xs4:
176 0000A8B4 dd 1b pushl $0x1b
177 0000A8B6 fe 08 efffff5743 callf $8,_XTrap
178 0000A8BD 00 halt
179 0000A8BE
180 0000A8BE
181 0000A8BE
182 0000A8BE
183 0000A8BE 0000 .align 2 .globl _Xs3 _Xs3:
184 0000A8C0 dd 1c pushl $0x1c
185 0000A8C2 fe 08 efffff5737 callf $8,_XTrap
186 0000A8C9 00 halt
187 0000A8CA
188 0000A8CA
189 0000A8CA
190 0000A8CA
191 0000A8CA 0000 .align 2 .globl _Xs2 _Xs2:
192 0000A8CC dd 1d pushl $0x1d
193 0000A8CE fe 08 efffff572b callf $8,_XTrap
194 0000A8D5 00 halt
195 0000A8D6
196 0000A8D6
197 0000A8D6
198 0000A8D6
199 0000A8D6 0000 .align 2 .globl _Xs1 _Xs1:
200 0000A8D8 dd 1e pushl $0x1e
201 0000A8DA fe 08 efffff571f callf $8,_XTrap
202 0000A8E1 00 halt
203 0000A8E2
204 0000A8E2
205 0000A8E2
206 0000A8E2
207 0000A8E2
208 0000A8E2 0000 .align 2 .globl _Xiovec14 _Xiovec14:
209 0000A8E4 00 halt
210 0000A8E5 000000 .align 2 .globl _Xiovec15 _Xiovec15:
211 0000A8E8 00 halt
212 0000A8E9 000000 .align 2 .globl _Xiovec16 _Xiovec16:
213 0000A8EC 00 halt
214 0000A8ED 000000 .align 2 .globl _Xiovec17 _Xiovec17:
215 0000A8F0 00 halt
216 0000A8F1
217 0000A8F1
218 0000A8F1
219 0000A8F1
220 0000A8F1
221 0000A8F1
222 0000A8F1
223 0000A8F1
224 0000A8F1
225 0000A8F1
226 0000A8F1
227 0000A8F1
228 0000A8F1
229 0000A8F1
230 0000A8F1
231 0000A8F1
232 0000A8F1
233 0000A8F1
234 0000A8F1 000000 .align 2 .globl _Xbuserror _Xbuserror:
235 0000A8F4 dd 20 pushl $0x20
236 0000A8F6 fe 08 efffff5703 callf $8,_XTrap
237 0000A8FD 00 halt
238 0000A8FE
239 0000A8FE
240 0000A8FE
241 0000A8FE
242 0000A8FE
243 0000A8FE
244 0000A8FE
245 0000A8FE
246 0000A8FE
247 0000A8FE
248 0000A8FE
249 0000A8FE 0000 .align 2 .globl _Xkspnotval _Xkspnotval:
250 0000A900 dd 31 pushl $0x31
251 0000A902 fe 08 efffff56f7 callf $8,_XTrap
252 0000A909 00 halt
253 0000A90A
254 0000A90A
255 0000A90A
256 0000A90A
257 0000A90A
258 0000A90A 0000 .align 2 .globl _Xprvinflt _Xprvinflt:
259 0000A90C cd efffff56ee movpsl _psl_val
260 0000A912 ad 1f 08 mtpr $0x1f,$IPL
261 0000A915 3d 890080 efffff56e2 bitl $PSL_DBL,_psl_val
262 0000A91E 31 08 beql 1f
263 0000A920 27 efffff56da std _post_evt_acc
264 0000A926 11 06 brb 2f
265 0000A928 26 efffff56d2 1: stf _post_evt_acc
266 0000A92E bb 891fff efffff56c9 2: storer $0x1fff,_store_regs
267 0000A937 ed 6d efffff56c2 moval (r13),_post_event_fp
268 0000A93E ed 6e efffff56bb moval (r14),_post_event_sp
269 0000A945 dd 2c pushl $0x2c
270 0000A947 fe 08 efffff56b2 callf $8,_XTrap
271 0000A94E 00 halt
272 0000A94F
273 0000A94F
274 0000A94F
275 0000A94F
276 0000A94F
277 0000A94F
278 0000A94F 00 .align 2 .globl _Xresopflt _Xresopflt:
279 0000A950 ad 1f 08 mtpr $0x1f,$IPL
280 0000A953 cd efffff56a7 movpsl _psl_val
281 0000A959 3d 890080 efffff569e bitl $PSL_DBL,_psl_val
282 0000A962 31 09 beql 1f
283 0000A964 27 efffff5696 std _post_evt_acc
284 0000A96A 13 000c brw 2f
285 0000A96D 26 efffff568d 1: stf _post_evt_acc
286 0000A973 4d efffff568b clrl _post_evt_acc+4
287 0000A979 2:
288 0000A979 bb 891fff efffff567e storer $0x1fff,_store_regs
289 0000A982 ed 6d efffff5677 moval (r13),_post_event_fp
290 0000A989 ed 6e efffff5670 moval (r14),_post_event_sp
291 0000A990 dd 2d pushl $0x2d
292 0000A992 fe 08 efffff5667 callf $8,_XTrap
293 0000A999 00 halt
294 0000A99A
295 0000A99A
296 0000A99A 0000 .align 2 .globl _Xresadflt _Xresadflt:
297 0000A99C cd efffff565e movpsl _psl_val
298 0000A9A2 ad 1f 08 mtpr $0x1f,$IPL
299 0000A9A5 3d 890080 efffff5652 bitl $PSL_DBL,_psl_val
300 0000A9AE 31 08 beql 1f
301 0000A9B0 27 efffff564a std _post_evt_acc
302 0000A9B6 11 06 brb 2f
303 0000A9B8 26 efffff5642 1: stf _post_evt_acc
304 0000A9BE bb 891fff efffff5639 2: storer $0x1fff,_store_regs
305 0000A9C7 ed 6d efffff5632 moval (r13),_post_event_fp
306 0000A9CE ed 6e efffff562b moval (r14),_post_event_sp
307 0000A9D5 dd 2e pushl $0x2e
308 0000A9D7 fe 08 efffff5622 callf $8,_XTrap
309 0000A9DE 00 halt
310 0000A9DF
311 0000A9DF 00 .align 2 .globl _Xbptflt _Xbptflt:
312 0000A9E0 dd 33 pushl $0x33
313 0000A9E2 fe 08 efffff5617 callf $8,_XTrap
314 0000A9E9 00 halt
315 0000A9EA
316 0000A9EA 0000 .align 2 .globl _Xtracep _Xtracep:
317 0000A9EC cd efffff560e movpsl _psl_val
318 0000A9F2 ad 1f 08 mtpr $0x1f,$IPL
319 0000A9F5 3d 890080 efffff5602 bitl $PSL_DBL,_psl_val
320 0000A9FE 31 08 beql 1f
321 0000AA00 27 efffff55fa std _post_evt_acc
322 0000AA06 11 06 brb 2f
323 0000AA08 26 efffff55f2 1: stf _post_evt_acc
324 0000AA0E bb 891fff efffff55e9 2: storer $0x1fff,_store_regs
325 0000AA17 dd 32 pushl $0x32
326 0000AA19 fe 08 efffff55e0 callf $8,_XTrap
327 0000AA20 00 halt
328 0000AA21
329 0000AA21
330 0000AA21
331 0000AA21
332 0000AA21
333 0000AA21
334 0000AA21 000000 .align 2 .globl _Xarithtrap _Xarithtrap:
335 0000AA24 ad 1f 08 mtpr $0x1f,$IPL
336 0000AA27 cd efffff55d3 movpsl _psl_val
337 0000AA2D 3d 890080 efffff55ca bitl $PSL_DBL,_psl_val
338 0000AA36 31 09 beql 1f
339 0000AA38 27 efffff55c2 std _post_evt_acc
340 0000AA3E 13 000c brw 2f
341 0000AA41 1:
342 0000AA41 26 efffff55b9 stf _post_evt_acc
343 0000AA47 4d efffff55b7 clrl _post_evt_acc+4
344 0000AA4D 2:
345 0000AA4D bb 891fff efffff55aa storer $0x1fff,_store_regs
346 0000AA56 ed 6d efffff55a3 moval (r13),_post_event_fp
347 0000AA5D ed 6e efffff559c moval (r14),_post_event_sp
348 0000AA64 dd 34 pushl $0x34
349 0000AA66 fe 08 efffff5593 callf $8,_XTrap
350 0000AA6D 00 halt
351 0000AA6E
352 0000AA6E
353 0000AA6E 0000 .align 2 .globl _Xprotflt _Xprotflt:
354 0000AA70 cd efffff558a movpsl _psl_val
355 0000AA76 ed 6e efffff5583 moval (r14),_post_event_sp
356 0000AA7D dd 2f pushl $0x2f
357 0000AA7F fe 08 efffff557a callf $8,_XTrap
358 0000AA86 00 halt
359 0000AA87 00 .align 2 .globl _Xtransflt _Xtransflt:
360 0000AA88 dd 30 pushl $0x30
361 0000AA8A fe 08 efffff556f callf $8,_XTrap
362 0000AA91 00 halt
363 0000AA92 0000 .align 2 .globl _Xalignflt _Xalignflt:
364 0000AA94 cd efffff5566 movpsl _psl_val
365 0000AA9A ad 1f 08 mtpr $0x1f,$IPL
366 0000AA9D 3d 890080 efffff555a bitl $PSL_DBL,_psl_val
367 0000AAA6 31 08 beql 1f
368 0000AAA8 27 efffff5552 std _post_evt_acc
369 0000AAAE 11 06 brb 2f
370 0000AAB0 26 efffff554a 1: stf _post_evt_acc
371 0000AAB6 bb 891fff efffff5541 2: storer $0x1fff,_store_regs
372 0000AABF dd 35 pushl $0x35
373 0000AAC1 fe 08 efffff5538 callf $8,_XTrap
374 0000AAC8 00 halt
375 0000AAC9 000000 .align 2 .globl _Xfpp_emulate _Xfpp_emulate:
376 0000AACC cd efffff552e movpsl _psl_val
377 0000AAD2 0d efffff5528 efffff5523 movl _psl_val,_post_event_psl
378 0000AADD bb 891fff efffff551a storer $0x1fff,_store_regs
379 0000AAE6 ed 6d efffff5513 moval (r13),_post_event_fp
380 0000AAED ed 6e efffff550c moval (r14),_post_event_sp
381 0000AAF4 0d 6e efffff5505 movl (sp),_fpm_ms_op
382 0000AAFB 0d ae04 efffff54fd movl 4(sp),_fpm_ls_op
383 0000AB03 0d ae08 efffff54f5 movl 8(sp),_fpm_op_code
384 0000AB0B 0d ae0c efffff54ed movl 12(sp),_fpm_pc
385 0000AB13 0d ae10 efffff54e5 movl 16(sp),_fpm_psl
386 0000AB1B 3d 890080 efffff54dc bitl $PSL_DBL,_psl_val
387 0000AB24 31 08 beql 1f
388 0000AB26 27 efffff54d4 std _post_evt_acc
389 0000AB2C 11 0c brb 2f
390 0000AB2E 26 efffff54cc 1: stf _post_evt_acc
391 0000AB34 4d efffff54ca clrl _post_evt_acc+4
392 0000AB3A 2:
393 0000AB3A dd 37 pushl $0x37
394 0000AB3C fe 08 efffff54bd callf $8,_XTrap
395 0000AB43 00 halt
396 0000AB44
397 0000AB44 alltraps:
398 0000AB44 00 halt
399 0000AB45
400 0000AB45 000000 .align 2 .globl _Xkcall _Xkcall:
401 0000AB48 dd 2b pushl $0x2b
402 0000AB4A fe 08 efffff54af callf $8,_XTrap
403 0000AB51 00 halt
404 0000AB52
405 0000AB52
406 0000AB52 # 751 ""
751 0000AB52
752 0000AB52
753 0000AB52
754 0000AB52
755 0000AB52
756 0000AB52
757 0000AB52
758 0000AB52
759 0000AB52
760 0000AB52
761 0000AB52
762 0000AB52
763 0000AB52
764 0000AB52 .globl start
765 0000AB52 start:
766 0000AB52 ad 00 09 mtpr $0,$MME
767 0000AB55 0d 50 efffff54a4 movl r0,_run_list
768 0000AB5C 0d 51 efffff549d movl r1,_OPTIONS
769 0000AB63 0d 53 efffff5496 movl r3,_evt_inst
770 0000AB6A 4d efffff5490 clrl _nonstop
771 0000AB70 0d 52 efffff5489 movl r2,_count
772 0000AB77 21 07 bneq 1f
773 0000AB79 0d 01 efffff5480 movl $1,_count
774 0000AB80 81 07 1: bgeq 1f
775 0000AB82 0d 01 efffff5477 movl $1,_nonstop
776 0000AB89 1:
777 0000AB89 4d efffff5471 clrl _no_fpp_wcs
778 0000AB8F ad 890400 1b mtpr $0x400,$DCR
779 0000AB94 5d 51 tstl r1
780 0000AB96 21 07 bneq 1f
781 0000AB98 0d 01 efffff5461 movl $1,_no_fpp_wcs
782 0000AB9F 1:
783 0000AB9F e9 effffff85b 50 movab _scb,r0
784 0000ABA6 ac 8f3ffffc00 50 andl2 $0x3ffffc00,r0
785 0000ABAD ad 50 12 mtpr r0,$SCBB
786 0000ABB0 ad 1f 08 mtpr $0x1f,$IPL
787 0000ABB3
788 0000ABB3 bc 04 5b efffff5445 andl3 $4,r11,_ss1
789 0000ABBB
790 0000ABBB
791 0000ABBB # clear the option flags
792 0000ABBB
793 0000ABBB 4d efffff543f clrl _halt_flg
794 0000ABC1 4d efffff5439 clrl _loop_on_err
795 0000ABC7 0d 01 efffff5432 movl $1,_prt_error
796 0000ABCE 0d 01 efffff542b movl $1,_prt_hdrs
797 0000ABD5 0d 01 efffff5424 movl $1,_en_data_cache
798 0000ABDC
799 0000ABDC
800 0000ABDC # set the option flags as needed
801 0000ABDC
802 0000ABDC 3d 01 efffff541d bitl $1,_OPTIONS
803 0000ABE3 31 07 beql 1f
804 0000ABE5 0d 01 efffff5414 movl $1,_halt_flg
805 0000ABEC 1:
806 0000ABEC 3d 02 efffff540d bitl $2,_OPTIONS
807 0000ABF3 31 07 beql 1f
808 0000ABF5 0d 01 efffff5404 movl $1,_loop_on_err
809 0000ABFC 1:
810 0000ABFC 3d 04 efffff53fd bitl $4,_OPTIONS
811 0000AC03 31 06 beql 1f
812 0000AC05 4d efffff53f5 clrl _prt_error
813 0000AC0B 1:
814 0000AC0B 3d 08 efffff53ee bitl $8,_OPTIONS
815 0000AC12 31 06 beql 1f
816 0000AC14 4d efffff53e6 clrl _prt_hdrs
817 0000AC1A 1:
818 0000AC1A 3d 10 efffff53df bitl $16,_OPTIONS
819 0000AC21 31 06 beql 1f
820 0000AC23 4d efffff53d7 clrl _en_data_cache
821 0000AC29 1:
822 0000AC29
823 0000AC29 4d efffff53d1 clrl _exp_event
824 0000AC2F cd 51 movpsl r1
825 0000AC31 ac 89ff00 51 andl2 $0xffffff00,r1
826 0000AC36 1d 51 8f041f0000 cmpl r1,$0x041f0000
827 0000AC3D 31 0b beql 1f
828 0000AC3F 0d 01 50 2: movl $1,r0
829 0000AC42 0d 8f041f0000 52 movl $0x041f0000,r2
830 0000AC49 00 halt
831 0000AC4A 1:
832 0000AC4A 0d 8f00001800 50 movl $_intstack+NISP* 1024,r0
833 0000AC51 ac 8f3fffffff 50 andl2 $0x3fffffff,r0
834 0000AC58 ad 50 0f mtpr r0,$ISP
835 0000AC5B 0d 50 5e movl r0,sp
836 0000AC5E e9 6e 5d movab (sp),fp
837 0000AC61
838 0000AC61 # Clear system data area all the way upto system code
839 0000AC61 # this includes dump buffer,interrupt stack,spt,iomap,pcbs,user
840 0000AC61 # page tables, & io buffer area.
841 0000AC61
842 0000AC61 3:
843 0000AC61 e9 effffff799 57 movab esysdata,r7
844 0000AC68 e9 efffff5f96 56 movab _restart,r6
845 0000AC6F 4d 66 1: clrl (r6)
846 0000AC71 0c 04 56 1d 56 57 51 f6 addl2 $4,r6; cmpl r6,r7; bleq 1b;
847 0000AC79
848 0000AC79 # Initialize System Page Table
849 0000AC79
850 0000AC79 5:
851 0000AC79 4d 52 clrl r2
852 0000AC7B e9 effffff77f 51 movab esysdata,r1
853 0000AC82 ac 8f3fffffff 51 andl2 $0x3fffffff,r1
854 0000AC89 5e 0a 51 51 shar $ 10 ,r1,r1
855 0000AC8D
856 0000AC8D 1:
857 0000AC8D 9c 8fe0000000 52 orl3 $ 0x80000000| 0x60000000,r2,_Sysmap[r2]
42efffff6b66
858 0000AC9A 2f 51 52 ffee aoblss r1,r2,1b
859 0000AC9F
860 0000AC9F
861 0000AC9F # Map system text area 1 to 1, Kernel read/write.
862 0000AC9F # For this to work, the label _etext must exist at the end
863 0000AC9F # of system code; Add in 4 more pages for data area used in C
864 0000AC9F
865 0000AC9F e9 ef000000db 51 movab _Esys,r1
866 0000ACA6 ac 8f3fffffff 51 andl2 $0x3fffffff,r1
867 0000ACAD 5e 0a 51 51 shar $ 10 ,r1,r1
868 0000ACB1 1:
869 0000ACB1 9c 8fe0000000 52 orl3 $ 0x80000000| 0x60000000,r2,_Sysmap[r2]
42efffff6b42
870 0000ACBE 3f 51 52 ffee aobleq r1,r2,1b
871 0000ACC3
872 0000ACC3 # Map from here to last page used by user :
873 0000ACC3 # invalid, User access, & virtual = physical
874 0000ACC3
875 0000ACC3 0d 52 efffff5f4a movl r2,_unused
876 0000ACCA 0d 52 efffff5fb3 movl r2,_Ufpte
877 0000ACD1 0d 8f00080000 51 movl $0x80000,r1
878 0000ACD8 5e 0a 51 51 shar $ 10 ,r1,r1
879 0000ACDC 0d 51 efffff5fa5 movl r1,_Ulpte
880 0000ACE3
881 0000ACE3 1:
882 0000ACE3 9c 8ff8000000 52 orl3 $ 0x80000000| 0x78000000,r2,_Sysmap[r2]
42efffff6b10
883 0000ACF0 2f 51 52 ffee aoblss r1,r2,1b
884 0000ACF5
885 0000ACF5
886 0000ACF5 # Initialize SBR, SLR
887 0000ACF5
888 0000ACF5 sysrdy:
889 0000ACF5 ad 8f00001800 00 mtpr $_Sysmap,$SBR
890 0000ACFC ad 890200 01 mtpr $_Syssize,$SLR
891 0000AD01 ad 8840 1b mtpr $64,$DCR
892 0000AD05
893 0000AD05 # GO TO VIRTUAL MODE
894 0000AD05 # Double map the kernel into user addresses :
895 0000AD05 # This will enable system to go to virtual mode the 1st time !!
896 0000AD05
897 0000AD05
898 0000AD05 9c 8fc0000000 8f00001800 orl3 $0xc0000000,$_Sysmap,r0
50
899 0000AD11 ad 50 02 mtpr r0,$P0BR
900 0000AD14 ad 890200 03 mtpr $_Syssize,$P0LR
901 0000AD19 ad 01 19 mtpr $1,$PADC
902 0000AD1C ad 01 17 mtpr $1,$PACC
903 0000AD1F ad 01 0a mtpr $1,$TBIA
904 0000AD22
905 0000AD22 ad 8f00002400 0e mtpr $_pcb0,$0xe
906 0000AD29
907 0000AD29 e9 efffff76d1 50 movab _pcb0,r0
908 0000AD30 e9 efffffdaca 60 movab ekstack,PCB_KSP(r0)
909 0000AD37 e9 ef00000c3f a004 movab eustack,PCB_USP(r0)
910 0000AD3F bd 02 a048 mfpr $P0BR,PCB_P0BR(r0)
911 0000AD43 bd 03 a04c mfpr $P0LR,PCB_P0LR(r0)
912 0000AD47 0d 00 a044 movl $0x0000000,PCB_PSL(r0)
913 0000AD4B
914 0000AD4B bd 12 50 mfpr $SCBB,r0
915 0000AD4E e9 ef00000024 a01c movab _Clock_handler,CLOCKVEC(r0)
916 0000AD56
917 0000AD56 e9 efffffdaa4 5e movab ekstack,sp
918 0000AD5D e9 6e 5d movab (sp),fp
919 0000AD60
920 0000AD60 0d 01 efffff5e99 movl $1,_Codek
921 0000AD67 ad efffff5e93 0d mtpr _Codek,$CCK
922 0000AD6E
923 0000AD6E fe 04 efffff528b callf $4,_monitor
924 0000AD75
925 0000AD75
926 0000AD75
927 0000AD75
928 0000AD75 #
929 0000AD75
930 0000AD75
931 0000AD75 000000 .align 2
932 0000AD78 .globl _Clock_handler
933 0000AD78 _Clock_handler:
934 0000AD78 0d 01 efffff5281 movl $1,_rtc_occurred
935 0000AD7F 20 rei
936 0000AD80
937 0000AD80
938 0000AD80
939 0000AD80 #
940 0000AD80
941 0000AD80
942 0000AD80
943 0000AD80 .globl _Esys
944 0000AD80 _Esys:
945 0000AD80 **** .space 1024
946 0000B180
947 0000B180 .globl _Ustack
948 0000B180 _Ustack:
949 0000B180 **** .space (2* 1024)-4
950 0000B97C .globl eustack
951 0000B97C eustack:
952 0000B97C 00000000 .long 0
953 0000b980 *
954 0000b980 * .globl U_area
955 0000b980 * U_area:
956 0000b980 *
956 0000b980 *
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.