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1.1 root 1:
2: #include "evt_defs.h"
3:
4: /*
5: ********************************************************************
6: *
7: * MONITOR FOR THE FPP INTEGER-OVERFLOW EVENT TEST
8: *
9: * This test will generate integer-overflow faults with the FPP.
10: * There are 2 ways for the floating point to generate integer overflows:
11: * -either with the convert floating to integer instructions (CVFL, CVDL),
12: * or with the longword integer multiply instructions (MULL2, MULL3).
13: * CVFL and CVDL can cause integer overflows because any floating point
14: * accumulator larger than +(2**23)-1 or -2**23 will be too big to store
15: * as a longword integer.
16: * The test will cause the overflows with and without the integer
17: * overflow event being enabled. If the event is enabled we'll get an
18: * arithmetic trap (but the overflow bit (V) will NOT be set in the PSL.
19: * If the event is disabled then no event will occur but the 'V' bit
20: * will be set in the PSL.
21: * The integer multiplys will only be tested if there is an active FPP
22: * in the system. The converts will always be tested.
23: *
24: * 26-Mar-85 : written
25: * 20-Jul-85 : added MULL2, MULL3
26: *
27: ********************************************************************
28: */
29: int_ovfl_test()
30: {
31: event_msg = "Integer Overflow";
32: test_event = ARITH_CODE; /* expect an arithmetic fault */
33: exp_code = INT_OVFL_CODE; /* -specificly integer overflow */
34: if( evt_inst ) { /* was the op-code specified? */
35: if( evt_inst == CVFL_OP_CODE )
36: run_cvfl(); /* test the CVFL instruction */
37: else if( evt_inst == CVDL_OP_CODE )
38: run_cvdl(); /* test the CVDL instruction */
39: else if( evt_inst == MULL2_OP_CODE ) {
40: if( !no_fpp_wcs )
41: run_mull2(); /* test the MULL2 instruction */
42: else {
43: if( (prt_hdrs) && (cycle == 1) )
44: writes("MULL2 is only tested with FPP hardware\n");
45: }
46: }
47: else if( evt_inst == MULL3_OP_CODE ) {
48: if( !no_fpp_wcs )
49: run_mull3(); /* test the MULL3 instruction */
50: else {
51: if( (prt_hdrs) && (cycle == 1) )
52: writes("MULL3 is only tested with FPP hardware\n");
53: }
54: }
55: else if( (prt_hdrs) && (cycle == 1) ) {
56: writes(
57: "There are no INTEGER OVERFLOW faults with op-code ");
58: writeh( evt_inst ); /* print the ersatz op-code */
59: writec('\n');
60: error = TRUE; /* needed for line feed spacing */
61: }
62: }
63: else { /* test all instructions */
64: run_cvfl(); /* test the CVFL instruction */
65: run_cvdl(); /* test the CVDL instruction */
66: if( !no_fpp_wcs ) {
67: run_mull2(); /* test the MULL2 instruction */
68: run_mull3(); /* test the MULL3 instruction */
69: }
70: }
71: }
72:
73:
74: /*
75: **********************************************************************
76: *
77: * SET UP TO TEST INTEGER OVERFLOW WITH THE CVFL INSTRUCTION
78: *
79: **********************************************************************
80: */
81: run_cvfl()
82: {
83: valid_test = TRUE; /* a test is being run */
84: op_code = CVFL_OP_CODE; /* set the inst's op_code */
85: op_name = "CVFL "; /* set the inst's name */
86: precision = SGL;
87: acc_ld_size = SGL; /* load a single precision Acc. */
88: sgl_op = TRUE;
89: no_ops = 1; /* one operand */
90: data_ptr = cvfl_ov_dat; /* set the data ptr */
91: max_index = cvfl_ov_cnt; /* set the max index */
92: if( (prt_hdrs) && (cycle == 1) )
93: writes( op_name );
94: disable_mask = 0; /* don't disable any events */
95: evt_disabled = FALSE; /* expected event is enabled */
96: test_inst();
97: disable_mask = PSL_EN_OVFL; /* disable the int ovfl event */
98: evt_disabled = TRUE;
99: test_inst();
100: }
101:
102: /*
103: **********************************************************************
104: *
105: * SET UP TO TEST INTEGER OVERFLOW WITH THE CVDL INSTRUCTION
106: *
107: **********************************************************************
108: */
109: run_cvdl()
110: {
111: valid_test = TRUE; /* a test is being run */
112: op_code = CVDL_OP_CODE; /* set the inst's op_code */
113: op_name = "CVDL "; /* set the inst's name */
114: precision = DBL;
115: acc_ld_size = DBL; /* load a double precision Acc. */
116: sgl_op = TRUE;
117: no_ops = 1; /* one operand */
118: data_ptr = cvdl_ov_dat; /* set the data ptr */
119: max_index = cvdl_ov_cnt; /* set the max index */
120: if( (prt_hdrs) && (cycle == 1) )
121: writes( op_name );
122: disable_mask = 0; /* don't disable any events */
123: evt_disabled = FALSE; /* expected event is enabled */
124: test_inst();
125: disable_mask = PSL_EN_OVFL; /* disable the int ovfl event */
126: evt_disabled = TRUE;
127: test_inst();
128: }
129:
130:
131: /*
132: **********************************************************************
133: *
134: * SET UP TO TEST INTEGER OVERFLOW WITH THE MULL2 INSTRUCTION
135: *
136: **********************************************************************
137: */
138: run_mull2()
139: {
140: valid_test = TRUE; /* a test is being run */
141: op_code = MULL2_OP_CODE; /* set the inst's op_code */
142: op_name = "MULL2 "; /* set the inst's name */
143: precision = SGL;
144: acc_ld_size = DBL; /* load a double precision Acc. */
145: sgl_op = TRUE;
146: no_ops = 2; /* two operands */
147: data_ptr = mull_ov_dat; /* set the data ptr */
148: max_index = mull_ov_cnt; /* set the max index */
149: if( (prt_hdrs) && (cycle == 1) )
150: writes( op_name );
151: disable_mask = 0; /* don't disable any events */
152: evt_disabled = FALSE; /* expected event is enabled */
153: test_inst();
154: disable_mask = PSL_EN_OVFL; /* disable the int ovfl event */
155: evt_disabled = TRUE;
156: test_inst();
157: }
158:
159:
160:
161: /*
162: **********************************************************************
163: *
164: * SET UP TO TEST INTEGER OVERFLOW WITH THE MULL3 INSTRUCTION
165: *
166: **********************************************************************
167: */
168: run_mull3()
169: {
170: valid_test = TRUE; /* a test is being run */
171: op_code = MULL3_OP_CODE; /* set the inst's op_code */
172: op_name = "MULL3 "; /* set the inst's name */
173: precision = SGL;
174: acc_ld_size = DBL; /* load a double precision Acc. */
175: sgl_op = TRUE;
176: no_ops = 3; /* three operands */
177: data_ptr = mull_ov_dat; /* set the data ptr */
178: max_index = mull_ov_cnt; /* set the max index */
179: if( (prt_hdrs) && (cycle == 1) )
180: writes( op_name );
181: disable_mask = 0; /* don't disable any events */
182: evt_disabled = FALSE; /* expected event is enabled */
183: test_inst();
184: disable_mask = PSL_EN_OVFL; /* disable the int ovfl event */
185: evt_disabled = TRUE;
186: test_inst();
187: }
188:
189:
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