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Power 6/32 Unix version 1.21

#include "evt_defs.h"

/*
 ********************************************************************
 *
 *	MONITOR FOR THE FPP INTEGER-OVERFLOW EVENT TEST
 *
 *  This test will generate integer-overflow faults with the FPP. 
 *  There are 2 ways for the floating point to generate integer overflows:
 *  -either with the convert floating to integer instructions (CVFL, CVDL),
 *  or with the longword integer multiply instructions (MULL2, MULL3).
 *  CVFL and CVDL can cause integer overflows because any floating point
 *  accumulator larger than +(2**23)-1 or -2**23 will be too big to store 
 *  as a longword integer.
 *  The test will cause the overflows with and without the integer
 *  overflow event being enabled. If the event is enabled we'll get an
 *  arithmetic trap (but the overflow bit (V) will NOT be set in the PSL.
 *  If the event is disabled then no event will occur but the 'V' bit
 *  will be set in the PSL.
 *  The integer multiplys will only be tested if there is an active FPP
 *  in the system. The converts will always be tested.
 *
 *  26-Mar-85  : written
 *  20-Jul-85  : added MULL2, MULL3
 *
 ********************************************************************
*/
int_ovfl_test()
{
	event_msg = "Integer Overflow";
	test_event = ARITH_CODE;	/* expect an arithmetic fault */
	exp_code = INT_OVFL_CODE;	/*  -specificly integer overflow */
	if( evt_inst )	{		/* was the op-code specified? */
	      if( evt_inst == CVFL_OP_CODE ) 
		   run_cvfl();		/* test the CVFL instruction */
	      else if( evt_inst == CVDL_OP_CODE ) 
		   run_cvdl();		/* test the CVDL instruction */
	      else if( evt_inst == MULL2_OP_CODE ) {
		   if( !no_fpp_wcs )
			run_mull2();	/* test the MULL2 instruction */
		   else {
			if( (prt_hdrs) && (cycle == 1) ) 
			    writes("MULL2 is only tested with FPP hardware\n");
		   }
	      }
	      else if( evt_inst == MULL3_OP_CODE ) {
		   if( !no_fpp_wcs )
			run_mull3();	/* test the MULL3 instruction */
		   else {
			if( (prt_hdrs) && (cycle == 1) ) 
			    writes("MULL3 is only tested with FPP hardware\n");
		   }
	      }
	      else if( (prt_hdrs) && (cycle == 1) ) {
		   writes(
		     "There are no INTEGER OVERFLOW faults with op-code ");
		   writeh( evt_inst );	/* print the ersatz op-code  */
		   writec('\n');
		   error = TRUE;	/* needed for line feed spacing */
	      }
	} 
	 else  {	/* test all instructions */
	     run_cvfl();		/* test the CVFL instruction */
	     run_cvdl();		/* test the CVDL instruction */
	     if( !no_fpp_wcs ) {
		  run_mull2();		/* test the MULL2 instruction */
		  run_mull3();		/* test the MULL3 instruction */
	     }
	}
}
 

/*
 **********************************************************************
 *
 *	SET UP TO TEST INTEGER OVERFLOW WITH THE CVFL INSTRUCTION
 *
 **********************************************************************
*/
run_cvfl()
{
	valid_test = TRUE;		/* a test is being run */
	op_code   =  CVFL_OP_CODE;	/* set the inst's op_code */
	op_name   =  "CVFL ";		/* set the inst's name */
	precision =  SGL;
	acc_ld_size = SGL;		/* load a single precision Acc. */
	sgl_op    =  TRUE;
	no_ops	  =  1;			/* one operand */
	data_ptr  =  cvfl_ov_dat;	/* set the data ptr */
	max_index =  cvfl_ov_cnt; 	/* set the max index */
	if( (prt_hdrs) && (cycle == 1) ) 
	     writes( op_name );
	disable_mask = 0;		/* don't disable any events   */
	evt_disabled = FALSE;		/* expected event is enabled  */
	test_inst();
	disable_mask = PSL_EN_OVFL;	/* disable the int ovfl event */
	evt_disabled = TRUE;
	test_inst();
}

/*
 **********************************************************************
 *
 *	SET UP TO TEST INTEGER OVERFLOW WITH THE CVDL INSTRUCTION
 *
 **********************************************************************
*/
run_cvdl()
{
	valid_test = TRUE;		/* a test is being run */
	op_code   =  CVDL_OP_CODE;	/* set the inst's op_code */
	op_name   =  "CVDL ";		/* set the inst's name */
	precision =  DBL;
	acc_ld_size = DBL;		/* load a double precision Acc. */
	sgl_op    =  TRUE;
	no_ops	  =  1;			/* one operand */
	data_ptr  =  cvdl_ov_dat;	/* set the data ptr */
	max_index =  cvdl_ov_cnt; 	/* set the max index */
	if( (prt_hdrs) && (cycle == 1) ) 
	     writes( op_name );
	disable_mask = 0;		/* don't disable any events   */
	evt_disabled = FALSE;		/* expected event is enabled  */
	test_inst();
	disable_mask = PSL_EN_OVFL;	/* disable the int ovfl event */
	evt_disabled = TRUE;
	test_inst();
}


/*
 **********************************************************************
 *
 *	SET UP TO TEST INTEGER OVERFLOW WITH THE MULL2 INSTRUCTION
 *
 **********************************************************************
*/
run_mull2()
{
	valid_test = TRUE;		/* a test is being run */
	op_code   =  MULL2_OP_CODE;	/* set the inst's op_code */
	op_name   =  "MULL2 ";		/* set the inst's name */
	precision =  SGL;
	acc_ld_size = DBL;		/* load a double precision Acc. */
	sgl_op    =  TRUE;
	no_ops	  =  2;			/* two operands */
	data_ptr  =  mull_ov_dat;	/* set the data ptr */
	max_index =  mull_ov_cnt; 	/* set the max index */
	if( (prt_hdrs) && (cycle == 1) ) 
	     writes( op_name );
	disable_mask = 0;		/* don't disable any events   */
	evt_disabled = FALSE;		/* expected event is enabled  */
	test_inst();
	disable_mask = PSL_EN_OVFL;	/* disable the int ovfl event */
	evt_disabled = TRUE;
	test_inst();
}



/*
 **********************************************************************
 *
 *	SET UP TO TEST INTEGER OVERFLOW WITH THE MULL3 INSTRUCTION
 *
 **********************************************************************
*/
run_mull3()
{
	valid_test = TRUE;		/* a test is being run */
	op_code   =  MULL3_OP_CODE;	/* set the inst's op_code */
	op_name   =  "MULL3 ";		/* set the inst's name */
	precision =  SGL;
	acc_ld_size = DBL;		/* load a double precision Acc. */
	sgl_op    =  TRUE;
	no_ops	  =  3;			/* three operands */
	data_ptr  =  mull_ov_dat;	/* set the data ptr */
	max_index =  mull_ov_cnt; 	/* set the max index */
	if( (prt_hdrs) && (cycle == 1) ) 
	     writes( op_name );
	disable_mask = 0;		/* don't disable any events   */
	evt_disabled = FALSE;		/* expected event is enabled  */
	test_inst();
	disable_mask = PSL_EN_OVFL;	/* disable the int ovfl event */
	evt_disabled = TRUE;
	test_inst();
}

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