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1.1 ! root 1: 1 00000000 LL0: ! 2: 2 00000000 .data ! 3: 3 000003a0 * .text ! 4: 4 00000000 .align 1 ! 5: 5 00000000 .globl _int_ovfl_test ! 6: 6 00000000 _int_ovfl_test: ! 7: 7 0000DAB0 0000 .word L381 ! 8: 8 0000DAB2 # ! 9: 9 0000DAB2 # #include "evt_defs.h" ! 10: 10 0000DAB2 # ! 11: 11 0000DAB2 # /* ! 12: 12 0000DAB2 # ******************************************************************** ! 13: 13 0000DAB2 # * ! 14: 14 0000DAB2 # * MONITOR FOR THE FPP INTEGER-OVERFLOW EVENT TEST ! 15: 15 0000DAB2 # * ! 16: 16 0000DAB2 # * This test will generate integer-overflow faults with the FPP. ! 17: 17 0000DAB2 # * There are 2 ways for the floating point to generate integer overflows: ! 18: 18 0000DAB2 # * -either with the convert floating to integer instructions (CVFL, CVDL), ! 19: 19 0000DAB2 # * or with the longword integer multiply instructions (MULL2, MULL3). ! 20: 20 0000DAB2 # * CVFL and CVDL can cause integer overflows because any floating point ! 21: 21 0000DAB2 # * accumulator larger than +(2**23)-1 or -2**23 will be too big to store ! 22: 22 0000DAB2 # * as a longword integer. ! 23: 23 0000DAB2 # * The test will cause the overflows with and without the integer ! 24: 24 0000DAB2 # * overflow event being enabled. If the event is enabled we'll get an ! 25: 25 0000DAB2 # * arithmetic trap (but the overflow bit (V) will NOT be set in the PSL. ! 26: 26 0000DAB2 # * If the event is disabled then no event will occur but the 'V' bit ! 27: 27 0000DAB2 # * will be set in the PSL. ! 28: 28 0000DAB2 # * The integer multiplys will only be tested if there is an active FPP ! 29: 29 0000DAB2 # * in the system. The converts will always be tested. ! 30: 30 0000DAB2 # * ! 31: 31 0000DAB2 # * 26-Mar-85 : written ! 32: 32 0000DAB2 # * 20-Jul-85 : added MULL2, MULL3 ! 33: 33 0000DAB2 # * ! 34: 34 0000DAB2 # ******************************************************************** ! 35: 35 0000DAB2 # */ ! 36: 36 0000DAB2 # int_ovfl_test() ! 37: 37 0000DAB2 # { ! 38: 38 0000DAB2 13 0126 jbr L383 ! 39: 39 0000DAB5 L384: ! 40: 40 0000DAB5 # event_msg = "Integer Overflow"; ! 41: 41 0000DAB5 .data 1 ! 42: 42 000003a0 * L385: ! 43: 43 000003a0 * 496E7465676572204F7665726 .ascii "Integer Overflow\0" ! 44: 66C6F7700 ! 45: 44 000003b1 * .text ! 46: 45 0000DAB5 0d 8f000003a0 effffffff0 movl $L385,_event_msg ! 47: 46 0000DAC0 # test_event = ARITH_CODE; /* expect an arithmetic fault */ ! 48: 47 0000DAC0 0d 34 efffffffe9 movl $52,_test_event ! 49: 48 0000DAC7 # exp_code = INT_OVFL_CODE; /* -specificly integer overflow */ ! 50: 49 0000DAC7 0d 01 efffffffe2 movl $1,_exp_code ! 51: 50 0000DACE # if( evt_inst ) { /* was the op-code specified? */ ! 52: 51 0000DACE 5d efffffffdc tstl _evt_inst ! 53: 52 0000DAD4 21 03 13 00dd jeql L386 ! 54: 53 0000DAD9 # if( evt_inst == CVFL_OP_CODE ) ! 55: 54 0000DAD9 1d efffffffd1 890086 cmpl _evt_inst,$134 ! 56: 55 0000DAE2 21 0a jneq L387 ! 57: 56 0000DAE4 # run_cvfl(); /* test the CVFL instruction */ ! 58: 57 0000DAE4 fe 04 ef000000f3 callf $4,_run_cvfl ! 59: 58 0000DAEB # else if( evt_inst == CVDL_OP_CODE ) ! 60: 59 0000DAEB 13 00c6 jbr L389 ! 61: 60 0000DAEE L387: ! 62: 61 0000DAEE 1d efffffffbc 890087 cmpl _evt_inst,$135 ! 63: 62 0000DAF7 21 0a jneq L390 ! 64: 63 0000DAF9 # run_cvdl(); /* test the CVDL instruction */ ! 65: 64 0000DAF9 fe 04 ef0000017a callf $4,_run_cvdl ! 66: 65 0000DB00 # else if( evt_inst == MULL2_OP_CODE ) { ! 67: 66 0000DB00 13 00b1 jbr L392 ! 68: 67 0000DB03 L390: ! 69: 68 0000DB03 1d efffffffa7 884c cmpl _evt_inst,$76 ! 70: 69 0000DB0B 21 31 jneq L393 ! 71: 70 0000DB0D # if( !no_fpp_wcs ) ! 72: 71 0000DB0D 5d efffffff9d tstl _no_fpp_wcs ! 73: 72 0000DB13 21 09 jneq L394 ! 74: 73 0000DB15 # run_mull2(); /* test the MULL2 instruction */ ! 75: 74 0000DB15 fe 04 ef000001fa callf $4,_run_mull2 ! 76: 75 0000DB1C # else { ! 77: 76 0000DB1C 11 1e jbr L396 ! 78: 77 0000DB1E L394: ! 79: 78 0000DB1E # if( (prt_hdrs) && (cycle == 1) ) ! 80: 79 0000DB1E 5d efffffff8c tstl _prt_hdrs ! 81: 80 0000DB24 31 16 jeql L397 ! 82: 81 0000DB26 1d efffffff84 01 cmpl _cycle,$1 ! 83: 82 0000DB2D 21 0d jneq L397 ! 84: 83 0000DB2F # writes("MULL2 is only tested with FPP hardware\n"); ! 85: 84 0000DB2F .data 1 ! 86: 85 000003b1 * L399: ! 87: 86 000003b1 * 4D554C4C32206973206F6E6C7 .ascii "MULL2 is only tested with FPP hardware\12\0" ! 88: 9207465737465642077697468 ! 89: 2046505020686172647761726 ! 90: 50A00 ! 91: 87 000003d9 * .text ! 92: 88 0000DB2F dd 8f000003b1 pushl $L399 ! 93: 89 0000DB35 fe 08 efffffff74 callf $8,_writes ! 94: 90 0000DB3C # } ! 95: 91 0000DB3C L397: ! 96: 92 0000DB3C L396: ! 97: 93 0000DB3C # } ! 98: 94 0000DB3C # else if( evt_inst == MULL3_OP_CODE ) { ! 99: 95 0000DB3C 11 76 jbr L400 ! 100: 96 0000DB3E L393: ! 101: 97 0000DB3E 1d efffffff6c 885c cmpl _evt_inst,$92 ! 102: 98 0000DB46 21 31 jneq L401 ! 103: 99 0000DB48 # if( !no_fpp_wcs ) ! 104: 100 0000DB48 5d efffffff62 tstl _no_fpp_wcs ! 105: 101 0000DB4E 21 09 jneq L402 ! 106: 102 0000DB50 # run_mull3(); /* test the MULL3 instruction */ ! 107: 103 0000DB50 fe 04 ef0000025b callf $4,_run_mull3 ! 108: 104 0000DB57 # else { ! 109: 105 0000DB57 11 1e jbr L404 ! 110: 106 0000DB59 L402: ! 111: 107 0000DB59 # if( (prt_hdrs) && (cycle == 1) ) ! 112: 108 0000DB59 5d efffffff51 tstl _prt_hdrs ! 113: 109 0000DB5F 31 16 jeql L405 ! 114: 110 0000DB61 1d efffffff49 01 cmpl _cycle,$1 ! 115: 111 0000DB68 21 0d jneq L405 ! 116: 112 0000DB6A # writes("MULL3 is only tested with FPP hardware\n"); ! 117: 113 0000DB6A .data 1 ! 118: 114 000003d9 * L406: ! 119: 115 000003d9 * 4D554C4C33206973206F6E6C7 .ascii "MULL3 is only tested with FPP hardware\12\0" ! 120: 9207465737465642077697468 ! 121: 2046505020686172647761726 ! 122: 50A00 ! 123: 116 00000401 * .text ! 124: 117 0000DB6A dd 8f000003d9 pushl $L406 ! 125: 118 0000DB70 fe 08 efffffff39 callf $8,_writes ! 126: 119 0000DB77 # } ! 127: 120 0000DB77 L405: ! 128: 121 0000DB77 L404: ! 129: 122 0000DB77 # } ! 130: 123 0000DB77 # else if( (prt_hdrs) && (cycle == 1) ) { ! 131: 124 0000DB77 11 3b jbr L407 ! 132: 125 0000DB79 L401: ! 133: 126 0000DB79 5d efffffff31 tstl _prt_hdrs ! 134: 127 0000DB7F 31 33 jeql L408 ! 135: 128 0000DB81 1d efffffff29 01 cmpl _cycle,$1 ! 136: 129 0000DB88 21 2a jneq L408 ! 137: 130 0000DB8A # writes( ! 138: 131 0000DB8A # "There are no INTEGER OVERFLOW faults with op-code "); ! 139: 132 0000DB8A .data 1 ! 140: 133 00000401 * L409: ! 141: 134 00000401 * 546865726520617265206E6F2 .ascii "There are no INTEGER OVERFLOW faults with op-code \0" ! 142: 0494E5445474552204F564552 ! 143: 464C4F57206661756C7473207 ! 144: 7697468206F702D636F646520 ! 145: 00 ! 146: 135 00000434 * .text ! 147: 136 0000DB8A dd 8f00000401 pushl $L409 ! 148: 137 0000DB90 fe 08 efffffff19 callf $8,_writes ! 149: 138 0000DB97 # writeh( evt_inst ); /* print the ersatz op-code */ ! 150: 139 0000DB97 dd efffffff13 pushl _evt_inst ! 151: 140 0000DB9D fe 08 efffffff0c callf $8,_writeh ! 152: 141 0000DBA4 # writec('\n'); ! 153: 142 0000DBA4 dd 0a pushl $10 ! 154: 143 0000DBA6 fe 08 efffffff03 callf $8,_writec ! 155: 144 0000DBAD # error = TRUE; /* needed for line feed spacing */ ! 156: 145 0000DBAD 0d 01 effffffefc movl $1,_error ! 157: 146 0000DBB4 # } ! 158: 147 0000DBB4 # } ! 159: 148 0000DBB4 L408: ! 160: 149 0000DBB4 L407: ! 161: 150 0000DBB4 L400: ! 162: 151 0000DBB4 L392: ! 163: 152 0000DBB4 L389: ! 164: 153 0000DBB4 # else { /* test all instructions */ ! 165: 154 0000DBB4 11 24 jbr L412 ! 166: 155 0000DBB6 L386: ! 167: 156 0000DBB6 # run_cvfl(); /* test the CVFL instruction */ ! 168: 157 0000DBB6 fe 04 ef00000021 callf $4,_run_cvfl ! 169: 158 0000DBBD # run_cvdl(); /* test the CVDL instruction */ ! 170: 159 0000DBBD fe 04 ef000000b6 callf $4,_run_cvdl ! 171: 160 0000DBC4 # if( !no_fpp_wcs ) { ! 172: 161 0000DBC4 5d effffffee6 tstl _no_fpp_wcs ! 173: 162 0000DBCA 21 0e jneq L413 ! 174: 163 0000DBCC # run_mull2(); /* test the MULL2 instruction */ ! 175: 164 0000DBCC fe 04 ef00000143 callf $4,_run_mull2 ! 176: 165 0000DBD3 # run_mull3(); /* test the MULL3 instruction */ ! 177: 166 0000DBD3 fe 04 ef000001d8 callf $4,_run_mull3 ! 178: 167 0000DBDA # } ! 179: 168 0000DBDA # } ! 180: 169 0000DBDA L413: ! 181: 170 0000DBDA L412: ! 182: 171 0000DBDA # } ! 183: 172 0000DBDA 40 ret#2 ! 184: 173 0000DBDB .set L381,0x0 ! 185: 174 0000DBDB L383: ! 186: 175 0000DBDB 13 fed7 jbr L384 ! 187: 176 0000DBDE .data ! 188: 177 000003a0 * .text ! 189: 178 0000DBDE .align 1 ! 190: 179 0000DBDE .globl _run_cvfl ! 191: 180 0000DBDE _run_cvfl: ! 192: 181 0000DBDE 0000 .word L414 ! 193: 182 0000DBE0 # ! 194: 183 0000DBE0 # ! 195: 184 0000DBE0 # /* ! 196: 185 0000DBE0 # ********************************************************************** ! 197: 186 0000DBE0 # * ! 198: 187 0000DBE0 # * SET UP TO TEST INTEGER OVERFLOW WITH THE CVFL INSTRUCTION ! 199: 188 0000DBE0 # * ! 200: 189 0000DBE0 # ********************************************************************** ! 201: 190 0000DBE0 # */ ! 202: 191 0000DBE0 # run_cvfl() ! 203: 192 0000DBE0 # { ! 204: 193 0000DBE0 13 0094 jbr L416 ! 205: 194 0000DBE3 L417: ! 206: 195 0000DBE3 # valid_test = TRUE; /* a test is being run */ ! 207: 196 0000DBE3 0d 01 effffffec6 movl $1,_valid_test ! 208: 197 0000DBEA # op_code = CVFL_OP_CODE; /* set the inst's op_code */ ! 209: 198 0000DBEA 0d 890086 effffffebd movl $134,_op_code ! 210: 199 0000DBF3 # op_name = "CVFL "; /* set the inst's name */ ! 211: 200 0000DBF3 .data 1 ! 212: 201 00000434 * L418: ! 213: 202 00000434 * 4356464C2000 .ascii "CVFL \0" ! 214: 203 0000043a * .text ! 215: 204 0000DBF3 0d 8f00000434 effffffeb2 movl $L418,_op_name ! 216: 205 0000DBFE # precision = SGL; ! 217: 206 0000DBFE 0d 01 effffffeab movl $1,_precision ! 218: 207 0000DC05 # acc_ld_size = SGL; /* load a single precision Acc. */ ! 219: 208 0000DC05 0d 01 effffffea4 movl $1,_acc_ld_size ! 220: 209 0000DC0C # sgl_op = TRUE; ! 221: 210 0000DC0C 0d 01 effffffe9d movl $1,_sgl_op ! 222: 211 0000DC13 # no_ops = 1; /* one operand */ ! 223: 212 0000DC13 0d 01 effffffe96 movl $1,_no_ops ! 224: 213 0000DC1A # data_ptr = cvfl_ov_dat; /* set the data ptr */ ! 225: 214 0000DC1A 0d 8f00000000 effffffe8b movl $_cvfl_ov_dat,_data_ptr ! 226: 215 0000DC25 # max_index = cvfl_ov_cnt; /* set the max index */ ! 227: 216 0000DC25 0d effffffe85 effffffe80 movl _cvfl_ov_cnt,_max_index ! 228: 217 0000DC30 # if( (prt_hdrs) && (cycle == 1) ) ! 229: 218 0000DC30 5d effffffe7a tstl _prt_hdrs ! 230: 219 0000DC36 31 16 jeql L419 ! 231: 220 0000DC38 1d effffffe72 01 cmpl _cycle,$1 ! 232: 221 0000DC3F 21 0d jneq L419 ! 233: 222 0000DC41 # writes( op_name ); ! 234: 223 0000DC41 dd effffffe69 pushl _op_name ! 235: 224 0000DC47 fe 08 effffffe62 callf $8,_writes ! 236: 225 0000DC4E # disable_mask = 0; /* don't disable any events */ ! 237: 226 0000DC4E L419: ! 238: 227 0000DC4E 4b effffffe5c clrw _disable_mask ! 239: 228 0000DC54 # evt_disabled = FALSE; /* expected event is enabled */ ! 240: 229 0000DC54 4d effffffe56 clrl _evt_disabled ! 241: 230 0000DC5A # test_inst(); ! 242: 231 0000DC5A fe 04 effffffe4f callf $4,_test_inst ! 243: 232 0000DC61 # disable_mask = PSL_EN_OVFL; /* disable the int ovfl event */ ! 244: 233 0000DC61 7f 20 effffffe48 cvtlw $32,_disable_mask ! 245: 234 0000DC68 # evt_disabled = TRUE; ! 246: 235 0000DC68 0d 01 effffffe41 movl $1,_evt_disabled ! 247: 236 0000DC6F # test_inst(); ! 248: 237 0000DC6F fe 04 effffffe3a callf $4,_test_inst ! 249: 238 0000DC76 # } ! 250: 239 0000DC76 40 ret#2 ! 251: 240 0000DC77 .set L414,0x0 ! 252: 241 0000DC77 L416: ! 253: 242 0000DC77 13 ff69 jbr L417 ! 254: 243 0000DC7A .data ! 255: 244 000003a0 * .text ! 256: 245 0000DC7A .align 1 ! 257: 246 0000DC7A .globl _run_cvdl ! 258: 247 0000DC7A _run_cvdl: ! 259: 248 0000DC7A 0000 .word L421 ! 260: 249 0000DC7C # ! 261: 250 0000DC7C # /* ! 262: 251 0000DC7C # ********************************************************************** ! 263: 252 0000DC7C # * ! 264: 253 0000DC7C # * SET UP TO TEST INTEGER OVERFLOW WITH THE CVDL INSTRUCTION ! 265: 254 0000DC7C # * ! 266: 255 0000DC7C # ********************************************************************** ! 267: 256 0000DC7C # */ ! 268: 257 0000DC7C # run_cvdl() ! 269: 258 0000DC7C # { ! 270: 259 0000DC7C 13 0094 jbr L423 ! 271: 260 0000DC7F L424: ! 272: 261 0000DC7F # valid_test = TRUE; /* a test is being run */ ! 273: 262 0000DC7F 0d 01 effffffe2a movl $1,_valid_test ! 274: 263 0000DC86 # op_code = CVDL_OP_CODE; /* set the inst's op_code */ ! 275: 264 0000DC86 0d 890087 effffffe21 movl $135,_op_code ! 276: 265 0000DC8F # op_name = "CVDL "; /* set the inst's name */ ! 277: 266 0000DC8F .data 1 ! 278: 267 0000043a * L425: ! 279: 268 0000043a * 4356444C2000 .ascii "CVDL \0" ! 280: 269 00000440 * .text ! 281: 270 0000DC8F 0d 8f0000043a effffffe16 movl $L425,_op_name ! 282: 271 0000DC9A # precision = DBL; ! 283: 272 0000DC9A 0d 02 effffffe0f movl $2,_precision ! 284: 273 0000DCA1 # acc_ld_size = DBL; /* load a double precision Acc. */ ! 285: 274 0000DCA1 0d 02 effffffe08 movl $2,_acc_ld_size ! 286: 275 0000DCA8 # sgl_op = TRUE; ! 287: 276 0000DCA8 0d 01 effffffe01 movl $1,_sgl_op ! 288: 277 0000DCAF # no_ops = 1; /* one operand */ ! 289: 278 0000DCAF 0d 01 effffffdfa movl $1,_no_ops ! 290: 279 0000DCB6 # data_ptr = cvdl_ov_dat; /* set the data ptr */ ! 291: 280 0000DCB6 0d 8f00000000 effffffdef movl $_cvdl_ov_dat,_data_ptr ! 292: 281 0000DCC1 # max_index = cvdl_ov_cnt; /* set the max index */ ! 293: 282 0000DCC1 0d effffffde9 effffffde4 movl _cvdl_ov_cnt,_max_index ! 294: 283 0000DCCC # if( (prt_hdrs) && (cycle == 1) ) ! 295: 284 0000DCCC 5d effffffdde tstl _prt_hdrs ! 296: 285 0000DCD2 31 16 jeql L426 ! 297: 286 0000DCD4 1d effffffdd6 01 cmpl _cycle,$1 ! 298: 287 0000DCDB 21 0d jneq L426 ! 299: 288 0000DCDD # writes( op_name ); ! 300: 289 0000DCDD dd effffffdcd pushl _op_name ! 301: 290 0000DCE3 fe 08 effffffdc6 callf $8,_writes ! 302: 291 0000DCEA # disable_mask = 0; /* don't disable any events */ ! 303: 292 0000DCEA L426: ! 304: 293 0000DCEA 4b effffffdc0 clrw _disable_mask ! 305: 294 0000DCF0 # evt_disabled = FALSE; /* expected event is enabled */ ! 306: 295 0000DCF0 4d effffffdba clrl _evt_disabled ! 307: 296 0000DCF6 # test_inst(); ! 308: 297 0000DCF6 fe 04 effffffdb3 callf $4,_test_inst ! 309: 298 0000DCFD # disable_mask = PSL_EN_OVFL; /* disable the int ovfl event */ ! 310: 299 0000DCFD 7f 20 effffffdac cvtlw $32,_disable_mask ! 311: 300 0000DD04 # evt_disabled = TRUE; ! 312: 301 0000DD04 0d 01 effffffda5 movl $1,_evt_disabled ! 313: 302 0000DD0B # test_inst(); ! 314: 303 0000DD0B fe 04 effffffd9e callf $4,_test_inst ! 315: 304 0000DD12 # } ! 316: 305 0000DD12 40 ret#2 ! 317: 306 0000DD13 .set L421,0x0 ! 318: 307 0000DD13 L423: ! 319: 308 0000DD13 13 ff69 jbr L424 ! 320: 309 0000DD16 .data ! 321: 310 000003a0 * .text ! 322: 311 0000DD16 .align 1 ! 323: 312 0000DD16 .globl _run_mull2 ! 324: 313 0000DD16 _run_mull2: ! 325: 314 0000DD16 0000 .word L427 ! 326: 315 0000DD18 # ! 327: 316 0000DD18 # ! 328: 317 0000DD18 # /* ! 329: 318 0000DD18 # ********************************************************************** ! 330: 319 0000DD18 # * ! 331: 320 0000DD18 # * SET UP TO TEST INTEGER OVERFLOW WITH THE MULL2 INSTRUCTION ! 332: 321 0000DD18 # * ! 333: 322 0000DD18 # ********************************************************************** ! 334: 323 0000DD18 # */ ! 335: 324 0000DD18 # run_mull2() ! 336: 325 0000DD18 # { ! 337: 326 0000DD18 13 0093 jbr L429 ! 338: 327 0000DD1B L430: ! 339: 328 0000DD1B # valid_test = TRUE; /* a test is being run */ ! 340: 329 0000DD1B 0d 01 effffffd8e movl $1,_valid_test ! 341: 330 0000DD22 # op_code = MULL2_OP_CODE; /* set the inst's op_code */ ! 342: 331 0000DD22 0d 884c effffffd86 movl $76,_op_code ! 343: 332 0000DD2A # op_name = "MULL2 "; /* set the inst's name */ ! 344: 333 0000DD2A .data 1 ! 345: 334 00000440 * L431: ! 346: 335 00000440 * 4D554C4C322000 .ascii "MULL2 \0" ! 347: 336 00000447 * .text ! 348: 337 0000DD2A 0d 8f00000440 effffffd7b movl $L431,_op_name ! 349: 338 0000DD35 # precision = SGL; ! 350: 339 0000DD35 0d 01 effffffd74 movl $1,_precision ! 351: 340 0000DD3C # acc_ld_size = DBL; /* load a double precision Acc. */ ! 352: 341 0000DD3C 0d 02 effffffd6d movl $2,_acc_ld_size ! 353: 342 0000DD43 # sgl_op = TRUE; ! 354: 343 0000DD43 0d 01 effffffd66 movl $1,_sgl_op ! 355: 344 0000DD4A # no_ops = 2; /* two operands */ ! 356: 345 0000DD4A 0d 02 effffffd5f movl $2,_no_ops ! 357: 346 0000DD51 # data_ptr = mull_ov_dat; /* set the data ptr */ ! 358: 347 0000DD51 0d 8f00000000 effffffd54 movl $_mull_ov_dat,_data_ptr ! 359: 348 0000DD5C # max_index = mull_ov_cnt; /* set the max index */ ! 360: 349 0000DD5C 0d effffffd4e effffffd49 movl _mull_ov_cnt,_max_index ! 361: 350 0000DD67 # if( (prt_hdrs) && (cycle == 1) ) ! 362: 351 0000DD67 5d effffffd43 tstl _prt_hdrs ! 363: 352 0000DD6D 31 16 jeql L432 ! 364: 353 0000DD6F 1d effffffd3b 01 cmpl _cycle,$1 ! 365: 354 0000DD76 21 0d jneq L432 ! 366: 355 0000DD78 # writes( op_name ); ! 367: 356 0000DD78 dd effffffd32 pushl _op_name ! 368: 357 0000DD7E fe 08 effffffd2b callf $8,_writes ! 369: 358 0000DD85 # disable_mask = 0; /* don't disable any events */ ! 370: 359 0000DD85 L432: ! 371: 360 0000DD85 4b effffffd25 clrw _disable_mask ! 372: 361 0000DD8B # evt_disabled = FALSE; /* expected event is enabled */ ! 373: 362 0000DD8B 4d effffffd1f clrl _evt_disabled ! 374: 363 0000DD91 # test_inst(); ! 375: 364 0000DD91 fe 04 effffffd18 callf $4,_test_inst ! 376: 365 0000DD98 # disable_mask = PSL_EN_OVFL; /* disable the int ovfl event */ ! 377: 366 0000DD98 7f 20 effffffd11 cvtlw $32,_disable_mask ! 378: 367 0000DD9F # evt_disabled = TRUE; ! 379: 368 0000DD9F 0d 01 effffffd0a movl $1,_evt_disabled ! 380: 369 0000DDA6 # test_inst(); ! 381: 370 0000DDA6 fe 04 effffffd03 callf $4,_test_inst ! 382: 371 0000DDAD # } ! 383: 372 0000DDAD 40 ret#2 ! 384: 373 0000DDAE .set L427,0x0 ! 385: 374 0000DDAE L429: ! 386: 375 0000DDAE 13 ff6a jbr L430 ! 387: 376 0000DDB1 .data ! 388: 377 000003a0 * .text ! 389: 378 0000DDB1 00 .align 1 ! 390: 379 0000DDB2 .globl _run_mull3 ! 391: 380 0000DDB2 _run_mull3: ! 392: 381 0000DDB2 0000 .word L433 ! 393: 382 0000DDB4 # ! 394: 383 0000DDB4 # ! 395: 384 0000DDB4 # ! 396: 385 0000DDB4 # /* ! 397: 386 0000DDB4 # ********************************************************************** ! 398: 387 0000DDB4 # * ! 399: 388 0000DDB4 # * SET UP TO TEST INTEGER OVERFLOW WITH THE MULL3 INSTRUCTION ! 400: 389 0000DDB4 # * ! 401: 390 0000DDB4 # ********************************************************************** ! 402: 391 0000DDB4 # */ ! 403: 392 0000DDB4 # run_mull3() ! 404: 393 0000DDB4 # { ! 405: 394 0000DDB4 13 0093 jbr L435 ! 406: 395 0000DDB7 L436: ! 407: 396 0000DDB7 # valid_test = TRUE; /* a test is being run */ ! 408: 397 0000DDB7 0d 01 effffffcf2 movl $1,_valid_test ! 409: 398 0000DDBE # op_code = MULL3_OP_CODE; /* set the inst's op_code */ ! 410: 399 0000DDBE 0d 885c effffffcea movl $92,_op_code ! 411: 400 0000DDC6 # op_name = "MULL3 "; /* set the inst's name */ ! 412: 401 0000DDC6 .data 1 ! 413: 402 00000447 * L437: ! 414: 403 00000447 * 4D554C4C332000 .ascii "MULL3 \0" ! 415: 404 0000044e * .text ! 416: 405 0000DDC6 0d 8f00000447 effffffcdf movl $L437,_op_name ! 417: 406 0000DDD1 # precision = SGL; ! 418: 407 0000DDD1 0d 01 effffffcd8 movl $1,_precision ! 419: 408 0000DDD8 # acc_ld_size = DBL; /* load a double precision Acc. */ ! 420: 409 0000DDD8 0d 02 effffffcd1 movl $2,_acc_ld_size ! 421: 410 0000DDDF # sgl_op = TRUE; ! 422: 411 0000DDDF 0d 01 effffffcca movl $1,_sgl_op ! 423: 412 0000DDE6 # no_ops = 3; /* three operands */ ! 424: 413 0000DDE6 0d 03 effffffcc3 movl $3,_no_ops ! 425: 414 0000DDED # data_ptr = mull_ov_dat; /* set the data ptr */ ! 426: 415 0000DDED 0d 8f00000000 effffffcb8 movl $_mull_ov_dat,_data_ptr ! 427: 416 0000DDF8 # max_index = mull_ov_cnt; /* set the max index */ ! 428: 417 0000DDF8 0d effffffcb2 effffffcad movl _mull_ov_cnt,_max_index ! 429: 418 0000DE03 # if( (prt_hdrs) && (cycle == 1) ) ! 430: 419 0000DE03 5d effffffca7 tstl _prt_hdrs ! 431: 420 0000DE09 31 16 jeql L438 ! 432: 421 0000DE0B 1d effffffc9f 01 cmpl _cycle,$1 ! 433: 422 0000DE12 21 0d jneq L438 ! 434: 423 0000DE14 # writes( op_name ); ! 435: 424 0000DE14 dd effffffc96 pushl _op_name ! 436: 425 0000DE1A fe 08 effffffc8f callf $8,_writes ! 437: 426 0000DE21 # disable_mask = 0; /* don't disable any events */ ! 438: 427 0000DE21 L438: ! 439: 428 0000DE21 4b effffffc89 clrw _disable_mask ! 440: 429 0000DE27 # evt_disabled = FALSE; /* expected event is enabled */ ! 441: 430 0000DE27 4d effffffc83 clrl _evt_disabled ! 442: 431 0000DE2D # test_inst(); ! 443: 432 0000DE2D fe 04 effffffc7c callf $4,_test_inst ! 444: 433 0000DE34 # disable_mask = PSL_EN_OVFL; /* disable the int ovfl event */ ! 445: 434 0000DE34 7f 20 effffffc75 cvtlw $32,_disable_mask ! 446: 435 0000DE3B # evt_disabled = TRUE; ! 447: 436 0000DE3B 0d 01 effffffc6e movl $1,_evt_disabled ! 448: 437 0000DE42 # test_inst(); ! 449: 438 0000DE42 fe 04 effffffc67 callf $4,_test_inst ! 450: 439 0000DE49 # } ! 451: 440 0000DE49 40 ret#2 ! 452: 441 0000DE4A .set L433,0x0 ! 453: 442 0000DE4A L435: ! 454: 443 0000DE4A 13 ff6a jbr L436 ! 455: 444 0000DE4D .data ! 456: 445 000003a0 * # ! 457: 446 000003a0 * # ! 458: 446 000003a0 * #
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