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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / fpevent|
Return to int_ov_test.lst CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / fpevent |
Power 6/32 Unix version 1.21
1 00000000 LL0:
2 00000000 .data
3 000003a0 * .text
4 00000000 .align 1
5 00000000 .globl _int_ovfl_test
6 00000000 _int_ovfl_test:
7 0000DAB0 0000 .word L381
8 0000DAB2 #
9 0000DAB2 # #include "evt_defs.h"
10 0000DAB2 #
11 0000DAB2 # /*
12 0000DAB2 # ********************************************************************
13 0000DAB2 # *
14 0000DAB2 # * MONITOR FOR THE FPP INTEGER-OVERFLOW EVENT TEST
15 0000DAB2 # *
16 0000DAB2 # * This test will generate integer-overflow faults with the FPP.
17 0000DAB2 # * There are 2 ways for the floating point to generate integer overflows:
18 0000DAB2 # * -either with the convert floating to integer instructions (CVFL, CVDL),
19 0000DAB2 # * or with the longword integer multiply instructions (MULL2, MULL3).
20 0000DAB2 # * CVFL and CVDL can cause integer overflows because any floating point
21 0000DAB2 # * accumulator larger than +(2**23)-1 or -2**23 will be too big to store
22 0000DAB2 # * as a longword integer.
23 0000DAB2 # * The test will cause the overflows with and without the integer
24 0000DAB2 # * overflow event being enabled. If the event is enabled we'll get an
25 0000DAB2 # * arithmetic trap (but the overflow bit (V) will NOT be set in the PSL.
26 0000DAB2 # * If the event is disabled then no event will occur but the 'V' bit
27 0000DAB2 # * will be set in the PSL.
28 0000DAB2 # * The integer multiplys will only be tested if there is an active FPP
29 0000DAB2 # * in the system. The converts will always be tested.
30 0000DAB2 # *
31 0000DAB2 # * 26-Mar-85 : written
32 0000DAB2 # * 20-Jul-85 : added MULL2, MULL3
33 0000DAB2 # *
34 0000DAB2 # ********************************************************************
35 0000DAB2 # */
36 0000DAB2 # int_ovfl_test()
37 0000DAB2 # {
38 0000DAB2 13 0126 jbr L383
39 0000DAB5 L384:
40 0000DAB5 # event_msg = "Integer Overflow";
41 0000DAB5 .data 1
42 000003a0 * L385:
43 000003a0 * 496E7465676572204F7665726 .ascii "Integer Overflow\0"
66C6F7700
44 000003b1 * .text
45 0000DAB5 0d 8f000003a0 effffffff0 movl $L385,_event_msg
46 0000DAC0 # test_event = ARITH_CODE; /* expect an arithmetic fault */
47 0000DAC0 0d 34 efffffffe9 movl $52,_test_event
48 0000DAC7 # exp_code = INT_OVFL_CODE; /* -specificly integer overflow */
49 0000DAC7 0d 01 efffffffe2 movl $1,_exp_code
50 0000DACE # if( evt_inst ) { /* was the op-code specified? */
51 0000DACE 5d efffffffdc tstl _evt_inst
52 0000DAD4 21 03 13 00dd jeql L386
53 0000DAD9 # if( evt_inst == CVFL_OP_CODE )
54 0000DAD9 1d efffffffd1 890086 cmpl _evt_inst,$134
55 0000DAE2 21 0a jneq L387
56 0000DAE4 # run_cvfl(); /* test the CVFL instruction */
57 0000DAE4 fe 04 ef000000f3 callf $4,_run_cvfl
58 0000DAEB # else if( evt_inst == CVDL_OP_CODE )
59 0000DAEB 13 00c6 jbr L389
60 0000DAEE L387:
61 0000DAEE 1d efffffffbc 890087 cmpl _evt_inst,$135
62 0000DAF7 21 0a jneq L390
63 0000DAF9 # run_cvdl(); /* test the CVDL instruction */
64 0000DAF9 fe 04 ef0000017a callf $4,_run_cvdl
65 0000DB00 # else if( evt_inst == MULL2_OP_CODE ) {
66 0000DB00 13 00b1 jbr L392
67 0000DB03 L390:
68 0000DB03 1d efffffffa7 884c cmpl _evt_inst,$76
69 0000DB0B 21 31 jneq L393
70 0000DB0D # if( !no_fpp_wcs )
71 0000DB0D 5d efffffff9d tstl _no_fpp_wcs
72 0000DB13 21 09 jneq L394
73 0000DB15 # run_mull2(); /* test the MULL2 instruction */
74 0000DB15 fe 04 ef000001fa callf $4,_run_mull2
75 0000DB1C # else {
76 0000DB1C 11 1e jbr L396
77 0000DB1E L394:
78 0000DB1E # if( (prt_hdrs) && (cycle == 1) )
79 0000DB1E 5d efffffff8c tstl _prt_hdrs
80 0000DB24 31 16 jeql L397
81 0000DB26 1d efffffff84 01 cmpl _cycle,$1
82 0000DB2D 21 0d jneq L397
83 0000DB2F # writes("MULL2 is only tested with FPP hardware\n");
84 0000DB2F .data 1
85 000003b1 * L399:
86 000003b1 * 4D554C4C32206973206F6E6C7 .ascii "MULL2 is only tested with FPP hardware\12\0"
9207465737465642077697468
2046505020686172647761726
50A00
87 000003d9 * .text
88 0000DB2F dd 8f000003b1 pushl $L399
89 0000DB35 fe 08 efffffff74 callf $8,_writes
90 0000DB3C # }
91 0000DB3C L397:
92 0000DB3C L396:
93 0000DB3C # }
94 0000DB3C # else if( evt_inst == MULL3_OP_CODE ) {
95 0000DB3C 11 76 jbr L400
96 0000DB3E L393:
97 0000DB3E 1d efffffff6c 885c cmpl _evt_inst,$92
98 0000DB46 21 31 jneq L401
99 0000DB48 # if( !no_fpp_wcs )
100 0000DB48 5d efffffff62 tstl _no_fpp_wcs
101 0000DB4E 21 09 jneq L402
102 0000DB50 # run_mull3(); /* test the MULL3 instruction */
103 0000DB50 fe 04 ef0000025b callf $4,_run_mull3
104 0000DB57 # else {
105 0000DB57 11 1e jbr L404
106 0000DB59 L402:
107 0000DB59 # if( (prt_hdrs) && (cycle == 1) )
108 0000DB59 5d efffffff51 tstl _prt_hdrs
109 0000DB5F 31 16 jeql L405
110 0000DB61 1d efffffff49 01 cmpl _cycle,$1
111 0000DB68 21 0d jneq L405
112 0000DB6A # writes("MULL3 is only tested with FPP hardware\n");
113 0000DB6A .data 1
114 000003d9 * L406:
115 000003d9 * 4D554C4C33206973206F6E6C7 .ascii "MULL3 is only tested with FPP hardware\12\0"
9207465737465642077697468
2046505020686172647761726
50A00
116 00000401 * .text
117 0000DB6A dd 8f000003d9 pushl $L406
118 0000DB70 fe 08 efffffff39 callf $8,_writes
119 0000DB77 # }
120 0000DB77 L405:
121 0000DB77 L404:
122 0000DB77 # }
123 0000DB77 # else if( (prt_hdrs) && (cycle == 1) ) {
124 0000DB77 11 3b jbr L407
125 0000DB79 L401:
126 0000DB79 5d efffffff31 tstl _prt_hdrs
127 0000DB7F 31 33 jeql L408
128 0000DB81 1d efffffff29 01 cmpl _cycle,$1
129 0000DB88 21 2a jneq L408
130 0000DB8A # writes(
131 0000DB8A # "There are no INTEGER OVERFLOW faults with op-code ");
132 0000DB8A .data 1
133 00000401 * L409:
134 00000401 * 546865726520617265206E6F2 .ascii "There are no INTEGER OVERFLOW faults with op-code \0"
0494E5445474552204F564552
464C4F57206661756C7473207
7697468206F702D636F646520
00
135 00000434 * .text
136 0000DB8A dd 8f00000401 pushl $L409
137 0000DB90 fe 08 efffffff19 callf $8,_writes
138 0000DB97 # writeh( evt_inst ); /* print the ersatz op-code */
139 0000DB97 dd efffffff13 pushl _evt_inst
140 0000DB9D fe 08 efffffff0c callf $8,_writeh
141 0000DBA4 # writec('\n');
142 0000DBA4 dd 0a pushl $10
143 0000DBA6 fe 08 efffffff03 callf $8,_writec
144 0000DBAD # error = TRUE; /* needed for line feed spacing */
145 0000DBAD 0d 01 effffffefc movl $1,_error
146 0000DBB4 # }
147 0000DBB4 # }
148 0000DBB4 L408:
149 0000DBB4 L407:
150 0000DBB4 L400:
151 0000DBB4 L392:
152 0000DBB4 L389:
153 0000DBB4 # else { /* test all instructions */
154 0000DBB4 11 24 jbr L412
155 0000DBB6 L386:
156 0000DBB6 # run_cvfl(); /* test the CVFL instruction */
157 0000DBB6 fe 04 ef00000021 callf $4,_run_cvfl
158 0000DBBD # run_cvdl(); /* test the CVDL instruction */
159 0000DBBD fe 04 ef000000b6 callf $4,_run_cvdl
160 0000DBC4 # if( !no_fpp_wcs ) {
161 0000DBC4 5d effffffee6 tstl _no_fpp_wcs
162 0000DBCA 21 0e jneq L413
163 0000DBCC # run_mull2(); /* test the MULL2 instruction */
164 0000DBCC fe 04 ef00000143 callf $4,_run_mull2
165 0000DBD3 # run_mull3(); /* test the MULL3 instruction */
166 0000DBD3 fe 04 ef000001d8 callf $4,_run_mull3
167 0000DBDA # }
168 0000DBDA # }
169 0000DBDA L413:
170 0000DBDA L412:
171 0000DBDA # }
172 0000DBDA 40 ret#2
173 0000DBDB .set L381,0x0
174 0000DBDB L383:
175 0000DBDB 13 fed7 jbr L384
176 0000DBDE .data
177 000003a0 * .text
178 0000DBDE .align 1
179 0000DBDE .globl _run_cvfl
180 0000DBDE _run_cvfl:
181 0000DBDE 0000 .word L414
182 0000DBE0 #
183 0000DBE0 #
184 0000DBE0 # /*
185 0000DBE0 # **********************************************************************
186 0000DBE0 # *
187 0000DBE0 # * SET UP TO TEST INTEGER OVERFLOW WITH THE CVFL INSTRUCTION
188 0000DBE0 # *
189 0000DBE0 # **********************************************************************
190 0000DBE0 # */
191 0000DBE0 # run_cvfl()
192 0000DBE0 # {
193 0000DBE0 13 0094 jbr L416
194 0000DBE3 L417:
195 0000DBE3 # valid_test = TRUE; /* a test is being run */
196 0000DBE3 0d 01 effffffec6 movl $1,_valid_test
197 0000DBEA # op_code = CVFL_OP_CODE; /* set the inst's op_code */
198 0000DBEA 0d 890086 effffffebd movl $134,_op_code
199 0000DBF3 # op_name = "CVFL "; /* set the inst's name */
200 0000DBF3 .data 1
201 00000434 * L418:
202 00000434 * 4356464C2000 .ascii "CVFL \0"
203 0000043a * .text
204 0000DBF3 0d 8f00000434 effffffeb2 movl $L418,_op_name
205 0000DBFE # precision = SGL;
206 0000DBFE 0d 01 effffffeab movl $1,_precision
207 0000DC05 # acc_ld_size = SGL; /* load a single precision Acc. */
208 0000DC05 0d 01 effffffea4 movl $1,_acc_ld_size
209 0000DC0C # sgl_op = TRUE;
210 0000DC0C 0d 01 effffffe9d movl $1,_sgl_op
211 0000DC13 # no_ops = 1; /* one operand */
212 0000DC13 0d 01 effffffe96 movl $1,_no_ops
213 0000DC1A # data_ptr = cvfl_ov_dat; /* set the data ptr */
214 0000DC1A 0d 8f00000000 effffffe8b movl $_cvfl_ov_dat,_data_ptr
215 0000DC25 # max_index = cvfl_ov_cnt; /* set the max index */
216 0000DC25 0d effffffe85 effffffe80 movl _cvfl_ov_cnt,_max_index
217 0000DC30 # if( (prt_hdrs) && (cycle == 1) )
218 0000DC30 5d effffffe7a tstl _prt_hdrs
219 0000DC36 31 16 jeql L419
220 0000DC38 1d effffffe72 01 cmpl _cycle,$1
221 0000DC3F 21 0d jneq L419
222 0000DC41 # writes( op_name );
223 0000DC41 dd effffffe69 pushl _op_name
224 0000DC47 fe 08 effffffe62 callf $8,_writes
225 0000DC4E # disable_mask = 0; /* don't disable any events */
226 0000DC4E L419:
227 0000DC4E 4b effffffe5c clrw _disable_mask
228 0000DC54 # evt_disabled = FALSE; /* expected event is enabled */
229 0000DC54 4d effffffe56 clrl _evt_disabled
230 0000DC5A # test_inst();
231 0000DC5A fe 04 effffffe4f callf $4,_test_inst
232 0000DC61 # disable_mask = PSL_EN_OVFL; /* disable the int ovfl event */
233 0000DC61 7f 20 effffffe48 cvtlw $32,_disable_mask
234 0000DC68 # evt_disabled = TRUE;
235 0000DC68 0d 01 effffffe41 movl $1,_evt_disabled
236 0000DC6F # test_inst();
237 0000DC6F fe 04 effffffe3a callf $4,_test_inst
238 0000DC76 # }
239 0000DC76 40 ret#2
240 0000DC77 .set L414,0x0
241 0000DC77 L416:
242 0000DC77 13 ff69 jbr L417
243 0000DC7A .data
244 000003a0 * .text
245 0000DC7A .align 1
246 0000DC7A .globl _run_cvdl
247 0000DC7A _run_cvdl:
248 0000DC7A 0000 .word L421
249 0000DC7C #
250 0000DC7C # /*
251 0000DC7C # **********************************************************************
252 0000DC7C # *
253 0000DC7C # * SET UP TO TEST INTEGER OVERFLOW WITH THE CVDL INSTRUCTION
254 0000DC7C # *
255 0000DC7C # **********************************************************************
256 0000DC7C # */
257 0000DC7C # run_cvdl()
258 0000DC7C # {
259 0000DC7C 13 0094 jbr L423
260 0000DC7F L424:
261 0000DC7F # valid_test = TRUE; /* a test is being run */
262 0000DC7F 0d 01 effffffe2a movl $1,_valid_test
263 0000DC86 # op_code = CVDL_OP_CODE; /* set the inst's op_code */
264 0000DC86 0d 890087 effffffe21 movl $135,_op_code
265 0000DC8F # op_name = "CVDL "; /* set the inst's name */
266 0000DC8F .data 1
267 0000043a * L425:
268 0000043a * 4356444C2000 .ascii "CVDL \0"
269 00000440 * .text
270 0000DC8F 0d 8f0000043a effffffe16 movl $L425,_op_name
271 0000DC9A # precision = DBL;
272 0000DC9A 0d 02 effffffe0f movl $2,_precision
273 0000DCA1 # acc_ld_size = DBL; /* load a double precision Acc. */
274 0000DCA1 0d 02 effffffe08 movl $2,_acc_ld_size
275 0000DCA8 # sgl_op = TRUE;
276 0000DCA8 0d 01 effffffe01 movl $1,_sgl_op
277 0000DCAF # no_ops = 1; /* one operand */
278 0000DCAF 0d 01 effffffdfa movl $1,_no_ops
279 0000DCB6 # data_ptr = cvdl_ov_dat; /* set the data ptr */
280 0000DCB6 0d 8f00000000 effffffdef movl $_cvdl_ov_dat,_data_ptr
281 0000DCC1 # max_index = cvdl_ov_cnt; /* set the max index */
282 0000DCC1 0d effffffde9 effffffde4 movl _cvdl_ov_cnt,_max_index
283 0000DCCC # if( (prt_hdrs) && (cycle == 1) )
284 0000DCCC 5d effffffdde tstl _prt_hdrs
285 0000DCD2 31 16 jeql L426
286 0000DCD4 1d effffffdd6 01 cmpl _cycle,$1
287 0000DCDB 21 0d jneq L426
288 0000DCDD # writes( op_name );
289 0000DCDD dd effffffdcd pushl _op_name
290 0000DCE3 fe 08 effffffdc6 callf $8,_writes
291 0000DCEA # disable_mask = 0; /* don't disable any events */
292 0000DCEA L426:
293 0000DCEA 4b effffffdc0 clrw _disable_mask
294 0000DCF0 # evt_disabled = FALSE; /* expected event is enabled */
295 0000DCF0 4d effffffdba clrl _evt_disabled
296 0000DCF6 # test_inst();
297 0000DCF6 fe 04 effffffdb3 callf $4,_test_inst
298 0000DCFD # disable_mask = PSL_EN_OVFL; /* disable the int ovfl event */
299 0000DCFD 7f 20 effffffdac cvtlw $32,_disable_mask
300 0000DD04 # evt_disabled = TRUE;
301 0000DD04 0d 01 effffffda5 movl $1,_evt_disabled
302 0000DD0B # test_inst();
303 0000DD0B fe 04 effffffd9e callf $4,_test_inst
304 0000DD12 # }
305 0000DD12 40 ret#2
306 0000DD13 .set L421,0x0
307 0000DD13 L423:
308 0000DD13 13 ff69 jbr L424
309 0000DD16 .data
310 000003a0 * .text
311 0000DD16 .align 1
312 0000DD16 .globl _run_mull2
313 0000DD16 _run_mull2:
314 0000DD16 0000 .word L427
315 0000DD18 #
316 0000DD18 #
317 0000DD18 # /*
318 0000DD18 # **********************************************************************
319 0000DD18 # *
320 0000DD18 # * SET UP TO TEST INTEGER OVERFLOW WITH THE MULL2 INSTRUCTION
321 0000DD18 # *
322 0000DD18 # **********************************************************************
323 0000DD18 # */
324 0000DD18 # run_mull2()
325 0000DD18 # {
326 0000DD18 13 0093 jbr L429
327 0000DD1B L430:
328 0000DD1B # valid_test = TRUE; /* a test is being run */
329 0000DD1B 0d 01 effffffd8e movl $1,_valid_test
330 0000DD22 # op_code = MULL2_OP_CODE; /* set the inst's op_code */
331 0000DD22 0d 884c effffffd86 movl $76,_op_code
332 0000DD2A # op_name = "MULL2 "; /* set the inst's name */
333 0000DD2A .data 1
334 00000440 * L431:
335 00000440 * 4D554C4C322000 .ascii "MULL2 \0"
336 00000447 * .text
337 0000DD2A 0d 8f00000440 effffffd7b movl $L431,_op_name
338 0000DD35 # precision = SGL;
339 0000DD35 0d 01 effffffd74 movl $1,_precision
340 0000DD3C # acc_ld_size = DBL; /* load a double precision Acc. */
341 0000DD3C 0d 02 effffffd6d movl $2,_acc_ld_size
342 0000DD43 # sgl_op = TRUE;
343 0000DD43 0d 01 effffffd66 movl $1,_sgl_op
344 0000DD4A # no_ops = 2; /* two operands */
345 0000DD4A 0d 02 effffffd5f movl $2,_no_ops
346 0000DD51 # data_ptr = mull_ov_dat; /* set the data ptr */
347 0000DD51 0d 8f00000000 effffffd54 movl $_mull_ov_dat,_data_ptr
348 0000DD5C # max_index = mull_ov_cnt; /* set the max index */
349 0000DD5C 0d effffffd4e effffffd49 movl _mull_ov_cnt,_max_index
350 0000DD67 # if( (prt_hdrs) && (cycle == 1) )
351 0000DD67 5d effffffd43 tstl _prt_hdrs
352 0000DD6D 31 16 jeql L432
353 0000DD6F 1d effffffd3b 01 cmpl _cycle,$1
354 0000DD76 21 0d jneq L432
355 0000DD78 # writes( op_name );
356 0000DD78 dd effffffd32 pushl _op_name
357 0000DD7E fe 08 effffffd2b callf $8,_writes
358 0000DD85 # disable_mask = 0; /* don't disable any events */
359 0000DD85 L432:
360 0000DD85 4b effffffd25 clrw _disable_mask
361 0000DD8B # evt_disabled = FALSE; /* expected event is enabled */
362 0000DD8B 4d effffffd1f clrl _evt_disabled
363 0000DD91 # test_inst();
364 0000DD91 fe 04 effffffd18 callf $4,_test_inst
365 0000DD98 # disable_mask = PSL_EN_OVFL; /* disable the int ovfl event */
366 0000DD98 7f 20 effffffd11 cvtlw $32,_disable_mask
367 0000DD9F # evt_disabled = TRUE;
368 0000DD9F 0d 01 effffffd0a movl $1,_evt_disabled
369 0000DDA6 # test_inst();
370 0000DDA6 fe 04 effffffd03 callf $4,_test_inst
371 0000DDAD # }
372 0000DDAD 40 ret#2
373 0000DDAE .set L427,0x0
374 0000DDAE L429:
375 0000DDAE 13 ff6a jbr L430
376 0000DDB1 .data
377 000003a0 * .text
378 0000DDB1 00 .align 1
379 0000DDB2 .globl _run_mull3
380 0000DDB2 _run_mull3:
381 0000DDB2 0000 .word L433
382 0000DDB4 #
383 0000DDB4 #
384 0000DDB4 #
385 0000DDB4 # /*
386 0000DDB4 # **********************************************************************
387 0000DDB4 # *
388 0000DDB4 # * SET UP TO TEST INTEGER OVERFLOW WITH THE MULL3 INSTRUCTION
389 0000DDB4 # *
390 0000DDB4 # **********************************************************************
391 0000DDB4 # */
392 0000DDB4 # run_mull3()
393 0000DDB4 # {
394 0000DDB4 13 0093 jbr L435
395 0000DDB7 L436:
396 0000DDB7 # valid_test = TRUE; /* a test is being run */
397 0000DDB7 0d 01 effffffcf2 movl $1,_valid_test
398 0000DDBE # op_code = MULL3_OP_CODE; /* set the inst's op_code */
399 0000DDBE 0d 885c effffffcea movl $92,_op_code
400 0000DDC6 # op_name = "MULL3 "; /* set the inst's name */
401 0000DDC6 .data 1
402 00000447 * L437:
403 00000447 * 4D554C4C332000 .ascii "MULL3 \0"
404 0000044e * .text
405 0000DDC6 0d 8f00000447 effffffcdf movl $L437,_op_name
406 0000DDD1 # precision = SGL;
407 0000DDD1 0d 01 effffffcd8 movl $1,_precision
408 0000DDD8 # acc_ld_size = DBL; /* load a double precision Acc. */
409 0000DDD8 0d 02 effffffcd1 movl $2,_acc_ld_size
410 0000DDDF # sgl_op = TRUE;
411 0000DDDF 0d 01 effffffcca movl $1,_sgl_op
412 0000DDE6 # no_ops = 3; /* three operands */
413 0000DDE6 0d 03 effffffcc3 movl $3,_no_ops
414 0000DDED # data_ptr = mull_ov_dat; /* set the data ptr */
415 0000DDED 0d 8f00000000 effffffcb8 movl $_mull_ov_dat,_data_ptr
416 0000DDF8 # max_index = mull_ov_cnt; /* set the max index */
417 0000DDF8 0d effffffcb2 effffffcad movl _mull_ov_cnt,_max_index
418 0000DE03 # if( (prt_hdrs) && (cycle == 1) )
419 0000DE03 5d effffffca7 tstl _prt_hdrs
420 0000DE09 31 16 jeql L438
421 0000DE0B 1d effffffc9f 01 cmpl _cycle,$1
422 0000DE12 21 0d jneq L438
423 0000DE14 # writes( op_name );
424 0000DE14 dd effffffc96 pushl _op_name
425 0000DE1A fe 08 effffffc8f callf $8,_writes
426 0000DE21 # disable_mask = 0; /* don't disable any events */
427 0000DE21 L438:
428 0000DE21 4b effffffc89 clrw _disable_mask
429 0000DE27 # evt_disabled = FALSE; /* expected event is enabled */
430 0000DE27 4d effffffc83 clrl _evt_disabled
431 0000DE2D # test_inst();
432 0000DE2D fe 04 effffffc7c callf $4,_test_inst
433 0000DE34 # disable_mask = PSL_EN_OVFL; /* disable the int ovfl event */
434 0000DE34 7f 20 effffffc75 cvtlw $32,_disable_mask
435 0000DE3B # evt_disabled = TRUE;
436 0000DE3B 0d 01 effffffc6e movl $1,_evt_disabled
437 0000DE42 # test_inst();
438 0000DE42 fe 04 effffffc67 callf $4,_test_inst
439 0000DE49 # }
440 0000DE49 40 ret#2
441 0000DE4A .set L433,0x0
442 0000DE4A L435:
443 0000DE4A 13 ff6a jbr L436
444 0000DE4D .data
445 000003a0 * #
446 000003a0 * #
446 000003a0 * #
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