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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / fpevent|
Return to monitor.lst CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / fpevent |
1.1 root 1: 1 00000000 LL0:
2: 2 00000000 .data
3: 3 000002dc * .text
4: 4 00000000 .align 1
5: 5 00000000 .globl _monitor
6: 6 00000000 _monitor:
7: 7 0000C2D8 0000 .word L382
8: 8 0000C2DA #
9: 9 0000C2DA # #include "evt_defs.h"
10: 10 0000C2DA #
11: 11 0000C2DA # /*********************************************************************
12: 12 0000C2DA # *
13: 13 0000C2DA # * MONITOR FOR THE FPP EVENTS TESTS
14: 14 0000C2DA # *
15: 15 0000C2DA # * 22-Mar-85 : written
16: 16 0000C2DA # * 10-Jul-85 : don't run pipe test if running all tests on a specified op-code
17: 17 0000C2DA # * 16-Jul-85 : added NO-FPP test capability
18: 18 0000C2DA # *********************************************************************/
19: 19 0000C2DA # monitor()
20: 20 0000C2DA # {
21: 21 0000C2DA 13 02d0 jbr L384
22: 22 0000C2DD L385:
23: 23 0000C2DD # struct test_t *test_tbl; /* pointer to the test table to use */
24: 24 0000C2DD # int no_subtests; /* number of tests in the table */
25: 25 0000C2DD # force_loop = FALSE; /* clear the 'force loop' flag */
26: 26 0000C2DD 4d effffffff5 clrl _force_loop
27: 27 0000C2E3 # valid_test = FALSE; /* clear the 'a test was run' flag */
28: 28 0000C2E3 4d efffffffef clrl _valid_test
29: 29 0000C2E9 # cycle = 0; /* clear the cycle count */
30: 30 0000C2E9 4d efffffffe9 clrl _cycle
31: 31 0000C2EF # errcnt = 0; /* clear the error count */
32: 32 0000C2EF 4d efffffffe3 clrl _errcnt
33: 33 0000C2F5 # error = FALSE; /* clear the current error flag */
34: 34 0000C2F5 4d efffffffdd clrl _error
35: 35 0000C2FB # if( no_fpp_wcs ) {
36: 36 0000C2FB 5d efffffffd7 tstl _no_fpp_wcs
37: 37 0000C301 31 12 jeql L386
38: 38 0000C303 # test_tbl = no_fpp_test_tbl; /* use the NO-FPP tests */
39: 39 0000C303 0d 8f00000000 adc8 movl $_no_fpp_test_tbl,-56(fp)
40: 40 0000C30B # no_subtests = no_fpp_test_cnt;
41: 41 0000C30B 0d efffffffc7 adc4 movl _no_fpp_test_cnt,-60(fp)
42: 42 0000C313 # } else {
43: 43 0000C313 11 10 jbr L387
44: 44 0000C315 L386:
45: 45 0000C315 # test_tbl = fpp_test_tbl; /* use the FPP tests */
46: 46 0000C315 0d 8f00000000 adc8 movl $_fpp_test_tbl,-56(fp)
47: 47 0000C31D # no_subtests = fpp_test_cnt;
48: 48 0000C31D 0d efffffffb5 adc4 movl _fpp_test_cnt,-60(fp)
49: 49 0000C325 # }
50: 50 0000C325 L387:
51: 51 0000C325 # /*
52: 52 0000C325 # * Print the Header information and enable the Data Cache if desired
53: 53 0000C325 # */
54: 54 0000C325 # if( prt_hdrs ) {
55: 55 0000C325 5d efffffffad tstl _prt_hdrs
56: 56 0000C32B 31 31 jeql L388
57: 57 0000C32D # writes("\nFPP Events Test");
58: 58 0000C32D .data 1
59: 59 000002dc * L390:
60: 60 000002dc * 0A465050204576656E7473205 .ascii "\12FPP Events Test\0"
61: 465737400
62: 61 000002ed * .text
63: 62 0000C32D dd 8f000002dc pushl $L390
64: 63 0000C333 fe 08 efffffff9e callf $8,_writes
65: 64 0000C33A # if( no_fpp_wcs )
66: 65 0000C33A 5d efffffff98 tstl _no_fpp_wcs
67: 66 0000C340 31 0f jeql L391
68: 67 0000C342 # writes(" - FPP is NOT installed");
69: 68 0000C342 .data 1
70: 69 000002ed * L392:
71: 70 000002ed * 202D20465050206973204E4F5 .ascii " - FPP is NOT installed\0"
72: 420696E7374616C6C656400
73: 71 00000305 * .text
74: 72 0000C342 dd 8f000002ed pushl $L392
75: 73 0000C348 fe 08 efffffff89 callf $8,_writes
76: 74 0000C34F # else
77: 75 0000C34F 11 0d jbr L393
78: 76 0000C351 L391:
79: 77 0000C351 # writes(" - FPP is installed");
80: 78 0000C351 .data 1
81: 79 00000305 * L394:
82: 80 00000305 * 202D2046505020697320696E7 .ascii " - FPP is installed\0"
83: 374616C6C656400
84: 81 00000319 * .text
85: 82 0000C351 dd 8f00000305 pushl $L394
86: 83 0000C357 fe 08 efffffff7a callf $8,_writes
87: 84 0000C35E L393:
88: 85 0000C35E # }
89: 86 0000C35E # if( en_data_cache ) {
90: 87 0000C35E L388:
91: 88 0000C35E 5d efffffff74 tstl _en_data_cache
92: 89 0000C364 31 1d jeql L395
93: 90 0000C366 # if( prt_hdrs )
94: 91 0000C366 5d efffffff6c tstl _prt_hdrs
95: 92 0000C36C 31 0d jeql L396
96: 93 0000C36E # writes(", Data Cache Enabled: ");
97: 94 0000C36E .data 1
98: 95 00000319 * L397:
99: 96 00000319 * 2C20204461746120436163686 .ascii ", Data Cache Enabled: \0"
100: 520456E61626C65643A2000
101: 97 00000331 * .text
102: 98 0000C36E dd 8f00000319 pushl $L397
103: 99 0000C374 fe 08 efffffff5d callf $8,_writes
104: 100 0000C37B # asm("mtpr $1,$25"); /* purge all data cache pages */
105: 101 0000C37B L396:
106: 102 0000C37B ad 01 19 mtpr $1,$25
107: 103 0000C37E # asm("mtpr $1,$27");; /* enable the data cache */
108: 104 0000C37E ad 01 1b mtpr $1,$27
109: 105 0000C381 # } else {
110: 106 0000C381 11 18 jbr L398
111: 107 0000C383 L395:
112: 108 0000C383 # if( prt_hdrs )
113: 109 0000C383 5d efffffff4f tstl _prt_hdrs
114: 110 0000C389 31 0d jeql L399
115: 111 0000C38B # writes(", Data Cache Disabled: ");
116: 112 0000C38B .data 1
117: 113 00000331 * L400:
118: 114 00000331 * 2C20446174612043616368652 .ascii ", Data Cache Disabled: \0"
119: 044697361626C65643A2000
120: 115 00000349 * .text
121: 116 0000C38B dd 8f00000331 pushl $L400
122: 117 0000C391 fe 08 efffffff40 callf $8,_writes
123: 118 0000C398 # asm("mtpr $2,$27"); /* disable the data cache */
124: 119 0000C398 L399:
125: 120 0000C398 ad 02 1b mtpr $2,$27
126: 121 0000C39B # }
127: 122 0000C39B L398:
128: 123 0000C39B # /*
129: 124 0000C39B # * Check the run list to see if a specific test is called for
130: 125 0000C39B # */
131: 126 0000C39B # for( cycle = 1; ( (cycle <= count) || nonstop ); cycle++ ) {
132: 127 0000C39B 0d 01 efffffff36 movl $1,_cycle
133: 128 0000C3A2 L403:
134: 129 0000C3A2 1d efffffff30 efffffff2b cmpl _cycle,_count
135: 130 0000C3AD 51 0b jleq L9999
136: 131 0000C3AF 5d efffffff23 tstl _nonstop
137: 132 0000C3B5 21 03 13 0125 jeql L402
138: 133 0000C3BA L9999:
139: 134 0000C3BA # if( (prt_hdrs) && (cycle != 1) ) /* show we're still running */
140: 135 0000C3BA 5d efffffff18 tstl _prt_hdrs
141: 136 0000C3C0 31 12 jeql L404
142: 137 0000C3C2 1d efffffff10 01 cmpl _cycle,$1
143: 138 0000C3C9 31 09 jeql L404
144: 139 0000C3CB # writec('.');
145: 140 0000C3CB dd 2e pushl $46
146: 141 0000C3CD fe 08 efffffff04 callf $8,_writec
147: 142 0000C3D4 # if( (run_list > 0) && (run_list <= no_subtests) ) {
148: 143 0000C3D4 L404:
149: 144 0000C3D4 5d effffffefe tstl _run_list
150: 145 0000C3DA 51 6e jleq L406
151: 146 0000C3DC 1d effffffef6 adc4 cmpl _run_list,-60(fp)
152: 147 0000C3E4 41 64 jgtr L406
153: 148 0000C3E6 # test_no = run_list;
154: 149 0000C3E6 0d effffffeec effffffee7 movl _run_list,_test_no
155: 150 0000C3F1 # test_index = run_list - 1;
156: 151 0000C3F1 3c 01 effffffee0 50 subl3 $1,_run_list,r0
157: 152 0000C3F9 0d 50 effffffed8 movl r0,_test_index
158: 153 0000C400 # if( (prt_hdrs) && (cycle == 1) ) {
159: 154 0000C400 5d effffffed2 tstl _prt_hdrs
160: 155 0000C406 31 29 jeql L407
161: 156 0000C408 1d effffffeca 01 cmpl _cycle,$1
162: 157 0000C40F 21 20 jneq L407
163: 158 0000C411 # /* if( !error ) /* */
164: 159 0000C411 # writec('\n');
165: 160 0000C411 dd 0a pushl $10
166: 161 0000C413 fe 08 effffffebe callf $8,_writec
167: 162 0000C41A # writes( test_tbl[ test_index ].name );
168: 163 0000C41A 48 03 effffffeb7 50 shll $3,_test_index,r0
169: 164 0000C422 1c 50 adc8 50 addl3 r0,-56(fp),r0
170: 165 0000C427 dd a004 pushl 4(r0)
171: 166 0000C42A fe 08 effffffea7 callf $8,_writes
172: 167 0000C431 # };
173: 168 0000C431 L407:
174: 169 0000C431 # (test_tbl[ test_index ].test)();
175: 170 0000C431 0d effffffea1 50 movl _test_index,r0
176: 171 0000C438 48 03 50 50 shll $3,r0,r0
177: 172 0000C43C 1c 50 adc8 50 addl3 r0,-56(fp),r0
178: 173 0000C441 0d 60 50 movl (r0),r0
179: 174 0000C444 bf 04 60 calls $4,(r0)
180: 175 0000C447 # }
181: 176 0000C447 # else /* run all tests */
182: 177 0000C447 13 008c jbr L408
183: 178 0000C44A L406:
184: 179 0000C44A # {
185: 180 0000C44A # for(test_index=0; test_index<no_subtests; test_index++) {
186: 181 0000C44A 4d effffffe88 clrl _test_index
187: 182 0000C450 L411:
188: 183 0000C450 1d effffffe82 adc4 cmpl _test_index,-60(fp)
189: 184 0000C458 81 7c jgeq L410
190: 185 0000C45A # test_no = test_index + 1;
191: 186 0000C45A 1c 01 effffffe77 50 addl3 $1,_test_index,r0
192: 187 0000C462 0d 50 effffffe6f movl r0,_test_no
193: 188 0000C469 # if( (no_fpp_wcs) || /* don't run pipe test w/ FPP WCS */
194: 189 0000C469 # (!evt_inst) || /* and a specified instruction */
195: 190 0000C469 # (test_index != pipe_test_index) ) {
196: 191 0000C469 5d effffffe69 tstl _no_fpp_wcs
197: 192 0000C46F 21 15 jneq L9998
198: 193 0000C471 5d effffffe61 tstl _evt_inst
199: 194 0000C477 31 0d jeql L9998
200: 195 0000C479 1d effffffe59 effffffe54 cmpl _test_index,_pipe_test_index
201: 196 0000C484 31 47 jeql L412
202: 197 0000C486 L9998:
203: 198 0000C486 # if( (prt_hdrs) && (cycle == 1) ) {
204: 199 0000C486 5d effffffe4c tstl _prt_hdrs
205: 200 0000C48C 31 29 jeql L413
206: 201 0000C48E 1d effffffe44 01 cmpl _cycle,$1
207: 202 0000C495 21 20 jneq L413
208: 203 0000C497 # /* if( !error ) /* */
209: 204 0000C497 # writec('\n');
210: 205 0000C497 dd 0a pushl $10
211: 206 0000C499 fe 08 effffffe38 callf $8,_writec
212: 207 0000C4A0 # writes( test_tbl[ test_index ].name );
213: 208 0000C4A0 48 03 effffffe31 50 shll $3,_test_index,r0
214: 209 0000C4A8 1c 50 adc8 50 addl3 r0,-56(fp),r0
215: 210 0000C4AD dd a004 pushl 4(r0)
216: 211 0000C4B0 fe 08 effffffe21 callf $8,_writes
217: 212 0000C4B7 # };
218: 213 0000C4B7 L413:
219: 214 0000C4B7 # (test_tbl[ test_index ].test)();
220: 215 0000C4B7 0d effffffe1b 50 movl _test_index,r0
221: 216 0000C4BE 48 03 50 50 shll $3,r0,r0
222: 217 0000C4C2 1c 50 adc8 50 addl3 r0,-56(fp),r0
223: 218 0000C4C7 0d 60 50 movl (r0),r0
224: 219 0000C4CA bf 04 60 calls $4,(r0)
225: 220 0000C4CD # }
226: 221 0000C4CD # }
227: 222 0000C4CD L412:
228: 223 0000C4CD L409:
229: 224 0000C4CD 6d effffffe05 incl _test_index
230: 225 0000C4D3 13 ff7a jbr L411
231: 226 0000C4D6 L410:
232: 227 0000C4D6 # } /* end of test-all-instructions */
233: 228 0000C4D6 L408:
234: 229 0000C4D6 # } /* end of test cycles - done with the test */
235: 230 0000C4D6 L401:
236: 231 0000C4D6 6d effffffdfc incl _cycle
237: 232 0000C4DC 13 fec3 jbr L403
238: 233 0000C4DF L402:
239: 234 0000C4DF # cycle--; /* correct cycle count */
240: 235 0000C4DF 7d effffffdf3 decl _cycle
241: 236 0000C4E5 # if( prt_hdrs ) {
242: 237 0000C4E5 5d effffffded tstl _prt_hdrs
243: 238 0000C4EB 21 03 13 008e jeql L414
244: 239 0000C4F0 # /* if( !error ) /* */
245: 240 0000C4F0 # writec('\n');; /* new line if no current errors */
246: 241 0000C4F0 dd 0a pushl $10
247: 242 0000C4F2 fe 08 effffffddf callf $8,_writec
248: 243 0000C4F9 # if( valid_test ) { /* were any tests actually run? */
249: 244 0000C4F9 5d effffffdd9 tstl _valid_test
250: 245 0000C4FF 31 5a jeql L415
251: 246 0000C501 # writes("Cycles Complete = ");
252: 247 0000C501 .data 1
253: 248 00000349 * L416:
254: 249 00000349 * 4379636C657320436F6D706C6 .ascii "Cycles Complete = \0"
255: 57465203D2000
256: 250 0000035c * .text
257: 251 0000C501 dd 8f00000349 pushl $L416
258: 252 0000C507 fe 08 effffffdca callf $8,_writes
259: 253 0000C50E # writed( cycle );
260: 254 0000C50E dd effffffdc4 pushl _cycle
261: 255 0000C514 fe 08 effffffdbd callf $8,_writed
262: 256 0000C51B # if( errcnt ) {
263: 257 0000C51B 5d effffffdb7 tstl _errcnt
264: 258 0000C521 31 29 jeql L418
265: 259 0000C523 # writes(", Error Count = " );
266: 260 0000C523 .data 1
267: 261 0000035c * L419:
268: 262 0000035c * 2C20204572726F7220436F756 .ascii ", Error Count = \0"
269: E74203D2000
270: 263 0000036e * .text
271: 264 0000C523 dd 8f0000035c pushl $L419
272: 265 0000C529 fe 08 effffffda8 callf $8,_writes
273: 266 0000C530 # writed( errcnt );
274: 267 0000C530 dd effffffda2 pushl _errcnt
275: 268 0000C536 fe 08 effffffd9b callf $8,_writed
276: 269 0000C53D # writes(", Test Complete\n");
277: 270 0000C53D .data 1
278: 271 0000036e * L420:
279: 272 0000036e * 2C20205465737420436F6D706 .ascii ", Test Complete\12\0"
280: C6574650A00
281: 273 00000380 * .text
282: 274 0000C53D dd 8f0000036e pushl $L420
283: 275 0000C543 fe 08 effffffd8e callf $8,_writes
284: 276 0000C54A # } else
285: 277 0000C54A 11 0d jbr L421
286: 278 0000C54C L418:
287: 279 0000C54C # writes(", TEST PASSED -NO ERRORS!!! \n");
288: 280 0000C54C .data 1
289: 281 00000380 * L422:
290: 282 00000380 * 2C20205445535420504153534 .ascii ", TEST PASSED -NO ERRORS!!! \12\0"
291: 544202D4E4F204552524F5253
292: 212121200A00
293: 283 0000039f * .text
294: 284 0000C54C dd 8f00000380 pushl $L422
295: 285 0000C552 fe 08 effffffd7f callf $8,_writes
296: 286 0000C559 L421:
297: 287 0000C559 # } else {
298: 288 0000C559 11 23 jbr L423
299: 289 0000C55B L415:
300: 290 0000C55B # writes("FPEVENT: no tests were run with instruction ");
301: 291 0000C55B .data 1
302: 292 0000039f * L424:
303: 293 0000039f * 46504556454E543A206E6F207 .ascii "FPEVENT: no tests were run with instruction \0"
304: 4657374732077657265207275
305: 6E207769746820696E7374727
306: 56374696F6E2000
307: 294 000003cc * .text
308: 295 0000C55B dd 8f0000039f pushl $L424
309: 296 0000C561 fe 08 effffffd70 callf $8,_writes
310: 297 0000C568 # writeh( evt_inst );
311: 298 0000C568 dd effffffd6a pushl _evt_inst
312: 299 0000C56E fe 08 effffffd63 callf $8,_writeh
313: 300 0000C575 # writec('\n');
314: 301 0000C575 dd 0a pushl $10
315: 302 0000C577 fe 08 effffffd5a callf $8,_writec
316: 303 0000C57E # }
317: 304 0000C57E L423:
318: 305 0000C57E # };
319: 306 0000C57E L414:
320: 307 0000C57E # /*
321: 308 0000C57E # * Set up the registers to halt
322: 309 0000C57E # */
323: 310 0000C57E # asm("movl _errcnt,r0"); /* set error count for halt */
324: 311 0000C57E 0d effffffd54 50 movl _errcnt,r0
325: 312 0000C585 # asm("bneq 1f");
326: 313 0000C585 21 0f bneq 1f
327: 314 0000C587 # asm("tstl _valid_test"); /* were any tests run? */
328: 315 0000C587 5d effffffd4b tstl _valid_test
329: 316 0000C58D # asm("beql 1f"); /* r0 = 0 if no tests run */
330: 317 0000C58D 31 07 beql 1f
331: 318 0000C58F # asm("movl $0xCAFEBABE,r0");; /* set the no-error flag */
332: 319 0000C58F 0d 8fcafebabe 50 movl $0xCAFEBABE,r0
333: 320 0000C596 # asm("1:");
334: 321 0000C596 1:
335: 322 0000C596 # asm("movl _OPTIONS,r1"); /* restore options to r1 */
336: 323 0000C596 0d effffffd3c 51 movl _OPTIONS,r1
337: 324 0000C59D # asm("movl _cycle,r2"); /* move cycle count to r2 */
338: 325 0000C59D 0d effffffd35 52 movl _cycle,r2
339: 326 0000C5A4 # asm("movl _evt_inst,r3"); /* move inst op-code to r3 */
340: 327 0000C5A4 0d effffffd2e 53 movl _evt_inst,r3
341: 328 0000C5AB # asm("halt");;
342: 329 0000C5AB 00 halt
343: 330 0000C5AC # }
344: 331 0000C5AC 40 ret#2
345: 332 0000C5AD .set L382,0x0
346: 333 0000C5AD L384:
347: 334 0000C5AD 3c 3c 5d 5e subl3 $60,fp,sp
348: 335 0000C5B1 13 fd29 jbr L385
349: 336 000002dc * .data
350: 337 000002dc * #
351: 338 000002dc * #
352: 338 000002dc * #
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