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1.1 root 1: 1 00000000 LL0:
2: 2 00000000 .data
3: 3 000001dc * .text
4: 4 00000000 .align 1
5: 5 00000000 .globl _ovfl_test
6: 6 00000000 _ovfl_test:
7: 7 0000DE50 0000 .word L381
8: 8 0000DE52 #
9: 9 0000DE52 # #include "evt_defs.h"
10: 10 0000DE52 #
11: 11 0000DE52 # /*
12: 12 0000DE52 # ********************************************************************
13: 13 0000DE52 # *
14: 14 0000DE52 # * MONITOR FOR THE FPP OVERFLOW EVENT TEST
15: 15 0000DE52 # *
16: 16 0000DE52 # * 25-Mar-85 JJM: written
17: 17 0000DE52 # *
18: 18 0000DE52 # ********************************************************************
19: 19 0000DE52 # */
20: 20 0000DE52 # ovfl_test()
21: 21 0000DE52 # {
22: 22 0000DE52 13 00b2 jbr L383
23: 23 0000DE55 L384:
24: 24 0000DE55 # event_msg = "Overflow";
25: 25 0000DE55 .data 1
26: 26 000001dc * L385:
27: 27 000001dc * 4F766572666C6F7700 .ascii "Overflow\0"
28: 28 000001e5 * .text
29: 29 0000DE55 0d 8f000001dc effffffff0 movl $L385,_event_msg
30: 30 0000DE60 # test_event = ARITH_CODE; /* expect an arithmetic fault */
31: 31 0000DE60 0d 34 efffffffe9 movl $52,_test_event
32: 32 0000DE67 # exp_code = FLT_OVFL_CODE; /* -specificly floating overflow */
33: 33 0000DE67 0d 04 efffffffe2 movl $4,_exp_code
34: 34 0000DE6E # disable_mask = 0; /* don't disable any events */
35: 35 0000DE6E 4b efffffffdc clrw _disable_mask
36: 36 0000DE74 # evt_disabled = FALSE;
37: 37 0000DE74 4d efffffffd6 clrl _evt_disabled
38: 38 0000DE7A # if( evt_inst ) /* was the op-code specified? */
39: 39 0000DE7A 5d efffffffd0 tstl _evt_inst
40: 40 0000DE80 31 62 jeql L386
41: 41 0000DE82 # {
42: 42 0000DE82 # inst_index = get_ovfl_index( evt_inst );
43: 43 0000DE82 dd efffffffc8 pushl _evt_inst
44: 44 0000DE88 fe 08 ef0000015b callf $8,_get_ovfl_index
45: 45 0000DE8F 0d 50 efffffffba movl r0,_inst_index
46: 46 0000DE96 # if( inst_index < 0 ) /* valid instruction for OVFL? */
47: 47 0000DE96 5d efffffffb4 tstl _inst_index
48: 48 0000DE9C 81 3d jgeq L388
49: 49 0000DE9E # {
50: 50 0000DE9E # if( (prt_hdrs) && (cycle == 1) ) /* not a valid instr */
51: 51 0000DE9E 5d efffffffac tstl _prt_hdrs
52: 52 0000DEA4 31 33 jeql L389
53: 53 0000DEA6 1d efffffffa4 01 cmpl _cycle,$1
54: 54 0000DEAD 21 2a jneq L389
55: 55 0000DEAF # {
56: 56 0000DEAF # writes(
57: 57 0000DEAF # "There are no floating OVERFLOW faults with op-code ");
58: 58 0000DEAF .data 1
59: 59 000001e5 * L391:
60: 60 000001e5 * 546865726520617265206E6F2 .ascii "There are no floating OVERFLOW faults with op-code \0"
61: 0666C6F6174696E67204F5645
62: 52464C4F57206661756C74732
63: 077697468206F702D636F6465
64: 2000
65: 61 00000219 * .text
66: 62 0000DEAF dd 8f000001e5 pushl $L391
67: 63 0000DEB5 fe 08 efffffff94 callf $8,_writes
68: 64 0000DEBC # writeh( evt_inst );
69: 65 0000DEBC dd efffffff8e pushl _evt_inst
70: 66 0000DEC2 fe 08 efffffff87 callf $8,_writeh
71: 67 0000DEC9 # writec('\n');
72: 68 0000DEC9 dd 0a pushl $10
73: 69 0000DECB fe 08 efffffff7e callf $8,_writec
74: 70 0000DED2 # error = TRUE; /* needed for line feed control */
75: 71 0000DED2 0d 01 efffffff77 movl $1,_error
76: 72 0000DED9 # }
77: 73 0000DED9 # } else
78: 74 0000DED9 L389:
79: 75 0000DED9 11 07 jbr L394
80: 76 0000DEDB L388:
81: 77 0000DEDB # test_ovfl_inst(); /* test the instruction */
82: 78 0000DEDB fe 04 ef00000028 callf $4,_test_ovfl_inst
83: 79 0000DEE2 L394:
84: 80 0000DEE2 # } else /* the op-code wasn't specfied */
85: 81 0000DEE2 11 22 jbr L396
86: 82 0000DEE4 L386:
87: 83 0000DEE4 # for(inst_index=0; inst_index < size_ovfl_tbl; inst_index++)
88: 84 0000DEE4 4d efffffff66 clrl _inst_index
89: 85 0000DEEA L399:
90: 86 0000DEEA 1d efffffff60 efffffff5b cmpl _inst_index,_size_ovfl_tbl
91: 87 0000DEF5 81 0f jgeq L398
92: 88 0000DEF7 # test_ovfl_inst(); /* test each ovfl instruction */
93: 89 0000DEF7 fe 04 ef0000000c callf $4,_test_ovfl_inst
94: 90 0000DEFE L397:
95: 91 0000DEFE 6d efffffff4c incl _inst_index
96: 92 0000DF04 11 e4 jbr L399
97: 93 0000DF06 L398:
98: 94 0000DF06 L396:
99: 95 0000DF06 # }
100: 96 0000DF06 40 ret#2
101: 97 0000DF07 .set L381,0x0
102: 98 0000DF07 L383:
103: 99 0000DF07 13 ff4b jbr L384
104: 100 0000DF0A .data
105: 101 000001dc * .text
106: 102 0000DF0A .align 1
107: 103 0000DF0A .globl _test_ovfl_inst
108: 104 0000DF0A _test_ovfl_inst:
109: 105 0000DF0A 0000 .word L400
110: 106 0000DF0C #
111: 107 0000DF0C #
112: 108 0000DF0C # /*
113: 109 0000DF0C # ********************************************************************
114: 110 0000DF0C # *
115: 111 0000DF0C # * test the floating overflow event on an instruction
116: 112 0000DF0C # *
117: 113 0000DF0C # ********************************************************************
118: 114 0000DF0C # */
119: 115 0000DF0C # test_ovfl_inst()
120: 116 0000DF0C # {
121: 117 0000DF0C 13 00d7 jbr L402
122: 118 0000DF0F L403:
123: 119 0000DF0F # valid_test = TRUE; /* a test is being run */
124: 120 0000DF0F 0d 01 efffffff3a movl $1,_valid_test
125: 121 0000DF16 # op_code = ovfl_tbl[ inst_index ].inst_code;
126: 122 0000DF16 0d efffffff34 50 movl _inst_index,r0
127: 123 0000DF1D 48 05 50 50 shll $5,r0,r0
128: 124 0000DF21 0d e000000000 efffffff24 movl _ovfl_tbl(r0),_op_code
129: 125 0000DF2C # op_name = ovfl_tbl[ inst_index ].name;
130: 126 0000DF2C 0d efffffff1e 50 movl _inst_index,r0
131: 127 0000DF33 48 05 50 50 shll $5,r0,r0
132: 128 0000DF37 0d e000000004 efffffff0e movl _ovfl_tbl+4(r0),_op_name
133: 129 0000DF42 # no_ops = ovfl_tbl[ inst_index ].no_operands;
134: 130 0000DF42 0d efffffff08 50 movl _inst_index,r0
135: 131 0000DF49 48 05 50 50 shll $5,r0,r0
136: 132 0000DF4D 0d e000000008 effffffef8 movl _ovfl_tbl+8(r0),_no_ops
137: 133 0000DF58 # precision = ovfl_tbl[ inst_index ].precision;
138: 134 0000DF58 0d effffffef2 50 movl _inst_index,r0
139: 135 0000DF5F 48 05 50 50 shll $5,r0,r0
140: 136 0000DF63 0d e00000000c effffffee2 movl _ovfl_tbl+12(r0),_precision
141: 137 0000DF6E # data_ptr = ovfl_tbl[ inst_index ].ovfl_data;
142: 138 0000DF6E 0d effffffedc 50 movl _inst_index,r0
143: 139 0000DF75 48 05 50 50 shll $5,r0,r0
144: 140 0000DF79 0d e000000010 effffffecc movl _ovfl_tbl+16(r0),_data_ptr
145: 141 0000DF84 # max_index = *ovfl_tbl[ inst_index ].ovfl_cnt;
146: 142 0000DF84 0d effffffec6 50 movl _inst_index,r0
147: 143 0000DF8B 48 05 50 50 shll $5,r0,r0
148: 144 0000DF8F 0d f000000014 effffffeb6 movl *_ovfl_tbl+20(r0),_max_index
149: 145 0000DF9A # if( precision == SGL ) {
150: 146 0000DF9A 1d effffffeb0 01 cmpl _precision,$1
151: 147 0000DFA1 21 10 jneq L404
152: 148 0000DFA3 # sgl_op = TRUE;
153: 149 0000DFA3 0d 01 effffffea6 movl $1,_sgl_op
154: 150 0000DFAA # acc_ld_size = SGL; /* use a sgl precision Acc. */
155: 151 0000DFAA 0d 01 effffffe9f movl $1,_acc_ld_size
156: 152 0000DFB1 # } else {
157: 153 0000DFB1 11 0d jbr L405
158: 154 0000DFB3 L404:
159: 155 0000DFB3 # sgl_op = FALSE;
160: 156 0000DFB3 4d effffffe97 clrl _sgl_op
161: 157 0000DFB9 # acc_ld_size = DBL; /* use a dbl precision Acc. */
162: 158 0000DFB9 0d 02 effffffe90 movl $2,_acc_ld_size
163: 159 0000DFC0 # }
164: 160 0000DFC0 L405:
165: 161 0000DFC0 # if( (prt_hdrs) && (cycle == 1) )
166: 162 0000DFC0 5d effffffe8a tstl _prt_hdrs
167: 163 0000DFC6 31 16 jeql L406
168: 164 0000DFC8 1d effffffe82 01 cmpl _cycle,$1
169: 165 0000DFCF 21 0d jneq L406
170: 166 0000DFD1 # writes( op_name );
171: 167 0000DFD1 dd effffffe79 pushl _op_name
172: 168 0000DFD7 fe 08 effffffe72 callf $8,_writes
173: 169 0000DFDE # test_inst();
174: 170 0000DFDE L406:
175: 171 0000DFDE fe 04 effffffe6b callf $4,_test_inst
176: 172 0000DFE5 # }
177: 173 0000DFE5 40 ret#2
178: 174 0000DFE6 .set L400,0x0
179: 175 0000DFE6 L402:
180: 176 0000DFE6 13 ff26 jbr L403
181: 177 0000DFE9 .data
182: 178 000001dc * .text
183: 179 0000DFE9 00 .align 1
184: 180 0000DFEA .globl _get_ovfl_index
185: 181 0000DFEA _get_ovfl_index:
186: 182 0000DFEA 0000 .word L408
187: 183 0000DFEC #
188: 184 0000DFEC #
189: 185 0000DFEC #
190: 186 0000DFEC #
191: 187 0000DFEC # /*
192: 188 0000DFEC # ***************************************************************************
193: 189 0000DFEC # *
194: 190 0000DFEC # * GET THE OVERFLOW / UNDERFLOW INSTRUCTION TABLE INDEX FOR AN OP-CODE
195: 191 0000DFEC # *
196: 192 0000DFEC # * Given the op_code of an instruction, return the instruction's index in
197: 193 0000DFEC # * the overflow / underflow instruction table. Return a negative number
198: 194 0000DFEC # * if the op-code isn't in the table.
199: 195 0000DFEC # *
200: 196 0000DFEC # **************************************************************************
201: 197 0000DFEC # */
202: 198 0000DFEC # get_ovfl_index( op_code )
203: 199 0000DFEC # {
204: 200 0000DFEC 11 38 jbr L410
205: 201 0000DFEE L411:
206: 202 0000DFEE # int x;
207: 203 0000DFEE # x = 0;
208: 204 0000DFEE 4d adc8 clrl -56(fp)
209: 205 0000DFF1 # while( (ovfl_tbl[x].inst_code != op_code) && (x < size_ovfl_tbl) )
210: 206 0000DFF1 L412:
211: 207 0000DFF1 0d adc8 50 movl -56(fp),r0
212: 208 0000DFF5 48 05 50 50 shll $5,r0,r0
213: 209 0000DFF9 1d e000000000 ad04 cmpl _ovfl_tbl(r0),4(fp)
214: 210 0000E001 31 0f jeql L413
215: 211 0000E003 1d adc8 effffffe45 cmpl -56(fp),_size_ovfl_tbl
216: 212 0000E00B 81 05 jgeq L413
217: 213 0000E00D # x++;
218: 214 0000E00D 6d adc8 incl -56(fp)
219: 215 0000E010 11 df jbr L412
220: 216 0000E012 L413:
221: 217 0000E012 # if( x == size_ovfl_tbl )
222: 218 0000E012 1d adc8 effffffe36 cmpl -56(fp),_size_ovfl_tbl
223: 219 0000E01A 21 04 jneq L414
224: 220 0000E01C # x = -1;
225: 221 0000E01C ec 01 adc8 mnegl $1,-56(fp)
226: 222 0000E020 # return( x );
227: 223 0000E020 L414:
228: 224 0000E020 0d adc8 50 movl -56(fp),r0
229: 225 0000E024 40 ret#1
230: 226 0000E025 # }
231: 227 0000E025 40 ret#1
232: 228 0000E026 .set L408,0x0
233: 229 0000E026 L410:
234: 230 0000E026 3c 38 5d 5e subl3 $56,fp,sp
235: 231 0000E02A 11 c2 jbr L411
236: 232 000001dc * .data
237: 233 000001dc * #
238: 234 000001dc * #
239: 234 000001dc * #
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