Return to pipe1.c CVS log

Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / fpevent

Power 6/32 Unix version 1.21

#include "evt_defs.h"

/*
 *********************************************************************
 *	FPP PIPELINED EVENTS TEST #1
 *
 *  This test will execute the following code: "LDD  DIVD  MOVL CVDL"
 * with an alignment fault on the MOVL. We will make sure that:
 * 1. The fault is detected, 
 * 2. the divide operation completes, and
 * 3. the convert double to integer isn't executed.
 *
 * NOTE: pipe14 also uses this tests data patterns
 *********************************************************************
*/
pipe1()
{
	asm("moval (r13),_pre_event_fp");	/* save the frame pointer */
	asm("moval (r14),_pre_event_sp");	/* save the stack pointer */
	precision = DBL;
	test_event = ALIGN_CODE;		/* alignment fault expected */
	exp_event = FALSE;			/* ... but not yet          */
	asm("movab _pipe1_ret,_event_return"); /* post event addr */
	for( index = 0; index < max_pipe1_index; index++ )
	{
	     dbl_value_1 =  pipe1_data[index].op_1;	/* get the data */
	     dbl_value_2 =  pipe1_data[index].op_2;
	     dbl_expected = pipe1_data[index].exp;
	     sgl_value_10 = 0;
	     asm(".globl _pipe1_lp1");		/* start of error loop */
	     asm("_pipe1_lp1:");
	     asm("bispsw $0x60");		/* enable ovfl & undfl */
	     asm("ldd _dbl_value_1");		/* load the Acc.       */
	     exp_event = test_event;		/* expect event soon   */
	     asm("divd _dbl_value_2");		/* start the divide    */
	     asm("movl _sgl_dummy1+1,_sgl_dummy2+2");	/* trigger the fault */
	     asm("cvdl _sgl_value_10");		/* we shouldn't get to here */
/*
 * If we got to here then there was no event
*/
	     if( force_loop )
		  asm("brw _pipe1_lp1");;	/* loop on the error         */
	     exp_event = FALSE;			/* reset event expected flag */
	     asm("bicpsw $0x60");		/* disable ovfl & undfl evts */
	     asm("movl _pre_event_fp,fp");	/* restore the frame pointer */
	     asm("movl _pre_event_sp,sp");	/* restore the stack pointer */
	     no_pipe1_evt();;			/* report the error          */
/*
 * Come here after the event
*/
	     asm(".globl _pipe1_ret");
	     asm("_pipe1_ret:");
	     asm("movl _pre_event_fp,fp");	/* restore the frame pointer */
	     asm("movl _pre_event_sp,sp");	/* restore the stack pointer */
	     if( force_loop )
		  asm("brw _pipe1_lp1");;	/* loop on the error         */
	     asm("bicpsw $0x60");		/* disable ovfl & undfl evts */
	     if( (post_evt_acc.m != dbl_expected.m) ||
		 (post_evt_acc.l != dbl_expected.l) )
		  bad_pipe1_result();		/* incorrect result error    */
	     else if( sgl_value_10 )
		  pipe1_queue_err();		/* queue not cleared error   */
	}
}



/****************************************************************************
*		Report an "EVENT NOT DETECTED" error
*
* Cycle: xx. EVT test xx. subtest xx. index = xx. No alignment fault occurred.
* inst = LDD op1, DIVD op2, MOVL op3,op4; CVDL op5 (alignment fault on the MOVL)
* op1 = xxxxxxxx xxxxxxxx,   op2 = xxxxxxxx xxxxxxxx
* addr. of op3 = xxxxxxxx,   addr. of op4 = xxxxxxxx
****************************************************************************/
no_pipe1_evt()
{
	errcnt++;				/* bump the error count    */
	if ( prt_error ) 
	{
	     print_pipe1_err( ". No alignment fault occurred.");
	     writes("op1 = ");
	     write32h( dbl_value_1.m );
	     writes(" ");
	     write32h( dbl_value_1.l );
	     writes(",   op2 = ");
	     write32h( dbl_value_2.m );
	     writes(" ");
	     write32h( dbl_value_2.l );
	     writes("\naddr. of ad_1 = ");
	     write32h( ( (int)&sgl_dummy1 )+1 );
	     writes(",   addr. of ad_2 = ");
	     write32h( ( (int)&sgl_dummy2 )+2 );
	     writec('\n');
	}
	if ( halt_flg ) 			/* halt on error?           */
	     pipe1_halt( 1 );
	if ( loop_on_err ) 
	{
	     force_loop = TRUE;			/* set the force loop flag */
	     asm("jmp _pipe1_lp1");		/* and loop                */
	};
}




/****************************************************************************
*		Report an "BAD ACCUMULATOR AFTER THE EVENT" error
*
* Cycle: xx. EVT test xx. subtest xx. index = xx. Bad final Accumulator. 
* inst = LDD op1, DIVD op2, MOVL op3,op4; CVDL op5 (alignment fault on the MOVL)
* op1 = xxxxxxxx xxxxxxxx,   final Acc. = xxxxxxxx xxxxxxxx
* op2 = xxxxxxxx xxxxxxxx,   expected   = xxxxxxxx xxxxxxxx
****************************************************************************/
bad_pipe1_result()
{
	errcnt++;				/* bump the error count    */
	if ( prt_error ) 
	{
	     print_pipe1_err( ". bad final accumulator.");
	     writes("op1 = ");
	     write32h( dbl_value_1.m );
	     writes(" ");
	     write32h( dbl_value_1.l );
	     writes(",   final Acc. = ");
	     write32h( post_evt_acc.m );
	     writec(' ');
	     write32h( post_evt_acc.l );
	     writes("\nop2 = ");
	     write32h( dbl_value_2.m );
	     writes(" ");
	     write32h( dbl_value_2.l );
	     writes(",   expected   = ");
	     write32h( dbl_expected.m );
	     writes(" ");
	     write32h( dbl_expected.l );
	     writec('\n');
	}
	if ( halt_flg ) 			/* halt on error?           */
	     pipe1_halt( 2 );
	if ( loop_on_err ) 
	{
	     force_loop = TRUE;			/* set the force loop flag */
	     asm("jmp _pipe1_lp1");		/* and loop                */
	};
}




/****************************************************************************
*		Report an "FPP QUEUE NOT CLEARED BY THE EVENT" error
*
* Cycle: xx. EVT test xx. subtest xx. index = xx. FPP queue not cleared.
* inst = LDD op1, DIVD op2, MOVL op3,op4; CVDL op5 (alignment fault on the MOVL)
* op1 = xxxxxxxx xxxxxxxx,   final Acc. = xxxxxxxx xxxxxxxx
* op2 = xxxxxxxx xxxxxxxx,    final op5 = xxxxxxxx 
****************************************************************************/
pipe1_queue_err()
{
	errcnt++;				/* bump the error count    */
	if ( prt_error ) 
	{
	     print_pipe1_err( ". FPP queue not cleared." );
	     writes("op1 = ");
	     write32h( dbl_value_1.m );
	     writes(" ");
	     write32h( dbl_value_1.l );
	     writes(",   final Acc. = ");
	     write32h( post_evt_acc.m );
	     writec(' ');
	     write32h( post_evt_acc.l );
	     writes("\nop2 = ");
	     write32h( dbl_value_2.m );
	     writes(" ");
	     write32h( dbl_value_2.l );
	     writes(",    final op5 = ");
	     write32h( sgl_value_10 );
	     writec('\n');
	}
	if ( halt_flg ) 			/* halt on error?           */
	     pipe1_halt( 3 );
	if ( loop_on_err ) 
	{
	     force_loop = TRUE;		/* set the force loop flag */
	     asm("jmp _pipe1_lp1");	/* and loop                */
	};
}


/****************************************************************************
*		Print an error message of the form:
*
* Cycle: xx. EVT test xx. subtest xx. <your message here>. index = xx 
* inst = LDD op1, DIVD op2, MOVL op3,op4; CVDL op5 (alignment fault on the MOVL)
****************************************************************************/
print_pipe1_err( msg )
char *msg;					/* pointer to error message */
{
	     if( errcnt == 1 )			/* 1st error?               */
		  writes(" \n");		/* start a new print line   */
	     writes("Cycle: ");
	     writed( cycle );
	     writes("  EVT test ");
	     writed( test_no );
	     writes(". subtest ");
	     writed( subtest );
	     writes(". ");
	     writes( msg );			/* write the message */
	     writes(" index = ");
	     writed( index );
	     writes( "\ninst = LDD op1, DIVD op2, MOVL op3,op4; CVDL op5 " );
	     writes( "(alignment fault on the MOVL)\n" );
}


/****************************************************************************
*		Error Halt Routine
****************************************************************************/
pipe1_halt( code )
int code;					/* halt code to use */
{
	err_code = code;
	sgl_value_1 = dbl_value_1.m;
	sgl_value_2 = dbl_value_1.l;
	sgl_value_3 = dbl_value_2.m;
	sgl_value_4 = dbl_value_2.l;
	asm("movl _test_no,r0");		/* r0  = test number        */
	asm("movl _subtest,r1");		/* r1  = subtest number     */
	asm("movl _err_code,r2");		/* r2  = error code         */
	asm("movl _cycle,r3");			/* r3  = cycle count        */
	asm("movl _sgl_value_1,r4");		/* r4  = MSW of operand 1   */
	asm("movl _sgl_value_2,r5");		/* r5  = LSW of operand 1   */
	asm("movl _sgl_value_3,r6");		/* r6  = MSW of operand 2   */
	asm("movl _sgl_value_4,r7");		/* r7  = LSW of operand 2   */
	if( code == 1 ) {
		asm("movab _sgl_dummy1+1,r8");	/* r8  = 1st movl op addr.  */
		asm("movab _sgl_dummy2+2,r9");	/* r9  = 2nd movl op addr.  */
		asm("movl _index,r10");		/* r10 = data index         */
	} 
	else if( code ==  2 ) {
	     sgl_value_5 = post_evt_acc.m;
	     sgl_value_6 = post_evt_acc.l;
	     sgl_value_7 = dbl_expected.m;
	     sgl_value_8 = dbl_expected.l;
	     asm("movl _sgl_value_5,r8");	/* r8  = MSW of final acc.  */
	     asm("movl _sgl_value_6,r9");	/* r9  = LSW of final acc.  */
	     asm("movl _sgl_value_7,r10");	/* r10 = MSW of expected    */
	     asm("movl _sgl_value_8,r11");	/* r11 = LSW of expected    */
	     asm("movl _index,r12");		/* r12 = data index         */
	}     
	else if( code ==  3 ) {
	     sgl_value_5 = post_evt_acc.m;
	     sgl_value_6 = post_evt_acc.l;
	     sgl_value_7 = sgl_value_10;
	     asm("movl _sgl_value_5,r8");	/* r8  = MSW of final acc.  */
	     asm("movl _sgl_value_6,r9");	/* r9  = LSW of final acc.  */
	     asm("movl _sgl_value_7,r10");	/* r10 = integer stored     */
	     asm("movl _index,r11");		/* r11 = data index         */
	};
	asm("halt");;				/* HALT ...                 */
};

This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.