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1.1 root 1:
2: #include "evt_defs.h"
3:
4: /*
5: *********************************************************************
6: * FPP PIPELINED EVENTS TEST #14
7: *
8: * This test will execute the following code: "LDD DIVD MULL3 NEGD"
9: * with an integer overflow fault on the MULL3. We will make sure that:
10: * 1. The fault is detected, and
11: * 2. the NEGD instruction is not executed.
12: *
13: * NOTE: This instruction uses the same data as pipe1
14: *********************************************************************
15: */
16: pipe14()
17: {
18: asm("moval (r13),_pre_event_fp"); /* save the frame pointer */
19: asm("moval (r14),_pre_event_sp"); /* save the stack pointer */
20: precision = DBL;
21: test_event = ARITH_CODE; /* expect an arithmetic fault */
22: exp_code = INT_OVFL_CODE; /* - specificly underflow */
23: exp_event = FALSE; /* ... but not yet */
24: asm("movab _pipe14_ret,_event_return"); /* set event return address */
25: for( index = 0; index < max_pipe1_index; index++ )
26: {
27: dbl_ld_acc = pipe1_data[index].op_1; /* get operand 1 */
28: dbl_value_1 = pipe1_data[index].op_2; /* get operand 2 */
29: dbl_expected = pipe1_data[index].exp; /* get expected Acc. */
30: asm("bispsw $0x60"); /* enable ovfl,undfl */
31: asm(".globl _pipe14_lp1");
32: asm("_pipe14_lp1:");
33: asm("movl $0x40404040,r0"); /* get the 'mull3' */
34: asm("movl $0x55005500,r2"); /* data patterns */
35: asm("ldd _dbl_ld_acc"); /* load the Acc. */
36: exp_event = test_event; /* expect event soon */
37: asm("divd _dbl_value_1"); /* do the divide */
38: asm("mull3 r0,r2,_dbl_value_3"); /* trigger the fault */
39: asm("nop"); /* shouldn't get here*/
40: asm("negd"); /* shouldn't get here*/
41: /*
42: * If we got to here then there was no event
43: */
44: if( force_loop )
45: asm("brw _pipe14_lp1");; /* loop on the error */
46: exp_event = FALSE; /* reset event expected flag */
47: asm("movl _pre_event_fp,fp"); /* restore the frame pointer */
48: asm("movl _pre_event_sp,sp"); /* restore the stack pointer */
49: asm("bicpsw $0x60"); /* disable ovfl & undfl evts */
50: no_pipe14_evt();; /* report the error */
51: /*
52: * Come here after the event
53: */
54: asm(".globl _pipe14_ret");
55: asm("_pipe14_ret:");
56: asm("movl _pre_event_fp,fp"); /* restore the frame pointer */
57: asm("movl _pre_event_sp,sp"); /* restore the stack pointer */
58: if( force_loop )
59: asm("brw _pipe14_lp1");; /* loop on the error */
60: asm("bicpsw $0x60"); /* disable ovfl & undfl evts */
61: if( (post_evt_acc.m == (dbl_expected.m ^ 0x80000000)) &&
62: (post_evt_acc.l == dbl_expected.l) ) /* was Acc. negated? */
63: pipe14_queue_er(); /* queue not cleared error */
64: else if( (post_evt_acc.m != dbl_expected.m) ||
65: (post_evt_acc.l != dbl_expected.l) ) /* Acc. = exp.? */
66: bad_pipe14_result(); /* incorrect result error */
67:
68: }
69: }
70:
71:
72:
73: /****************************************************************************
74: * Report an "EVENT NOT DETECTED" error
75: *
76: * Cycle: xx. EVT test xx. subtest xx. No overflow fault seen. index = xx
77: * inst = LDD op1; DIVD op2; MULL3,op3,op4,op5; NEGD (integer overflow on MULL3)
78: * op1 = xxxxxxxx xxxxxxxx, op3 = xxxxxxxx
79: * op2 = xxxxxxxx xxxxxxxx, op4 = xxxxxxxx
80: ****************************************************************************/
81: no_pipe14_evt()
82: {
83: errcnt++; /* bump the error count */
84: if ( prt_error )
85: {
86: print_pipe14_er( ". No overflow fault seen." );
87: writes("op1 = ");
88: write32h( dbl_ld_acc.m );
89: writec(' ');
90: write32h( dbl_ld_acc.l );
91: writes(", op3 = ");
92: write32h( 0x40404040 );
93: writes("\nop2 = ");
94: write32h( dbl_value_1.m );
95: writec(' ');
96: write32h( dbl_value_1.l );
97: writes(", op4 = ");
98: write32h( 0x55005500 );
99: writec('\n');
100: }
101: if ( halt_flg ) /* halt on error? */
102: pipe14_halt( 1 ); /* halt with a code of 1 */
103: if ( loop_on_err )
104: {
105: force_loop = TRUE; /* set the force loop flag */
106: asm("jmp _pipe14_lp1"); /* and loop */
107: };
108: }
109:
110:
111:
112:
113: /****************************************************************************
114: * Report an "BAD ACCUMULATOR AFTER THE EVENT" error
115: *
116: * Cycle: xx. EVT test xx. subtest xx. Bad final Accumulator. indexd = xx
117: * inst = LDD op1; DIVD op2; MULL3,op3,op4,op5; NEGD (integer overflow on MULL3)
118: * The NEGD instruction should not be executed.
119: * op1 = xxxxxxxx xxxxxxxx, final Acc. = xxxxxxxx xxxxxxxx, op3 = xxxxxxxx
120: * op2 = xxxxxxxx xxxxxxxx, expected = xxxxxxxx xxxxxxxx, op4 = xxxxxxxx
121: ****************************************************************************/
122: bad_pipe14_result()
123: {
124: errcnt++; /* bump the error count */
125: if ( prt_error )
126: {
127: print_pipe14_er( ". Bad final Accumulator" );
128: writes(
129: "The NEGD INSTRUCTION should not be executed\n");
130: writes("op1 = ");
131: write32h( dbl_ld_acc.m );
132: writec(' ');
133: write32h( dbl_ld_acc.l );
134: writes(", final Acc. = ");
135: write32h( post_evt_acc.m );
136: writec(' ');
137: write32h( post_evt_acc.l );
138: writes(", op3 = ");
139: write32h( 0x40404040 );
140: writes("\nop2 = ");
141: write32h( dbl_value_1.m );
142: writec(' ');
143: write32h( dbl_value_1.l );
144: writes(", expected = ");
145: write32h( dbl_expected.m );
146: writec(' ');
147: write32h( dbl_expected.l );
148: writes(", op4 = ");
149: write32h( 0x55005500 );
150: writec('\n');
151: }
152: if ( halt_flg ) /* halt on error? */
153: pipe14_halt( 2 ); /* halt with a code of 2 */
154: if ( loop_on_err )
155: {
156: force_loop = TRUE; /* set the force loop flag */
157: asm("jmp _pipe14_lp1"); /* and loop */
158: };
159: }
160:
161:
162:
163:
164:
165: /****************************************************************************
166: * Report an "FPP queue not cleared" message
167: *
168: * Cycle: xx. EVT test xx. subtest xx. Fpp queue not cleared. index = xx
169: * inst = LDD op1; DIVD op2; MULL3,op3,op4,op5; NEGD (integer overflow on MULL3)
170: * The NEGD instruction was apparently executed.
171: * op1 = xxxxxxxx xxxxxxxx, final Acc. = xxxxxxxx xxxxxxxx, op3 = xxxxxxxx
172: * op2 = xxxxxxxx xxxxxxxx, expected = xxxxxxxx xxxxxxxx, op4 = xxxxxxxx
173: ****************************************************************************/
174: pipe14_queue_er()
175: {
176: errcnt++; /* bump the error count */
177: if ( prt_error )
178: {
179: print_pipe14_er( ". Fpp queue not cleared" );
180: writes(
181: "The 2nd load double instruction was apparently executed.\n");
182: writes("op1 = ");
183: write32h( dbl_ld_acc.m );
184: writec(' ');
185: write32h( dbl_ld_acc.l );
186: writes(", final Acc. = ");
187: write32h( post_evt_acc.m );
188: writec(' ');
189: write32h( post_evt_acc.l );
190: writes(", op3 = ");
191: write32h( 0x40404040 );
192: writes("\nop2 = ");
193: write32h( dbl_value_1.m );
194: writec(' ');
195: write32h( dbl_value_1.l );
196: writes(", expected = ");
197: write32h( dbl_expected.m );
198: writec(' ');
199: write32h( dbl_expected.l );
200: writes(", op4 = ");
201: write32h( 0x55005500 );
202: writec('\n');
203: }
204: if ( halt_flg ) /* halt on error? */
205: pipe14_halt( 3 ); /* halt with a code of 3 */
206: if ( loop_on_err )
207: {
208: force_loop = TRUE; /* set the force loop flag */
209: asm("jmp _pipe14_lp1"); /* and loop */
210: };
211: }
212:
213:
214:
215:
216: /****************************************************************************
217: * Report an error message of the form:
218: *
219: * Cycle: xx. EVT test xx. subtest xx. <your message here> index = xx
220: * inst = LDD op1; DIVD op2; MULL3,op3,op4,op5; NEGD (integer overflow on MULL3)
221: ****************************************************************************/
222: print_pipe14_er( msg )
223: char *msg; /* error message to print */
224: {
225: if( errcnt == 1 ) /* 1st error? */
226: writes("\n\n"); /* start a new print line */
227: writes("Cycle: ");
228: writed( cycle );
229: writes(" EVT test ");
230: writed( test_no );
231: writes(". subtest ");
232: writed( subtest );
233: writes( msg ); /* print the message */
234: writes(" index = ");
235: writed( index );
236: writes("\ninst = LDD op1; DIVD op2; MULL3,op3,op4,op5; NEGD");
237: writes(" (integer overflow on MULL3)\n");
238: }
239:
240:
241:
242: /****************************************************************************
243: * halt on error routine
244: ****************************************************************************/
245: pipe14_halt( code )
246: int code; /* error code to halt with */
247: {
248: err_code = code;
249: sgl_value_1 = dbl_ld_acc.m;
250: sgl_value_2 = dbl_ld_acc.l;
251: sgl_value_3 = dbl_value_1.m;
252: sgl_value_4 = dbl_value_1.l;
253: sgl_value_5 = post_evt_acc.m;
254: sgl_value_6 = post_evt_acc.l;
255: sgl_value_7 = dbl_expected.m;
256: sgl_value_8 = dbl_expected.l;
257: asm("movl _test_no,r0"); /* r0 = test number */
258: asm("movl _subtest,r1"); /* r1 = subtest number */
259: asm("movl _err_code,r2"); /* r2 = error code */
260: asm("movl _cycle,r3"); /* r3 = cycle count */
261: asm("movl _sgl_value_1,r4"); /* r4 = MSW of 1st load. */
262: asm("movl _sgl_value_2,r5"); /* r5 = LSW of 1st load. */
263: asm("movl _sgl_value_3,r6"); /* r6 = MSW of 2nd load. */
264: asm("movl _sgl_value_4,r7"); /* r7 = LSW of 2nd load. */
265: asm("movl _sgl_value_5,r8"); /* r8 = MSW of final Acc. */
266: asm("movl _sgl_value_6,r9"); /* r9 = LSW of final Acc. */
267: asm("movl _sgl_value_7,r10"); /* r10 = MSW of exp. Acc. */
268: asm("movl _sgl_value_8,r11"); /* r11 = LSW of exp. Acc. */
269: asm("movl _index,r12"); /* r12 = data index */
270: asm("halt"); /* HALT ... */
271: }
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