![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to pipe17.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / fpevent|
Return to pipe17.c CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / fpevent |
Power 6/32 Unix version 1.21
#include "evt_defs.h"
/*
*********************************************************************
* FPP PIPELINED EVENTS TEST #17
*
* This test will execute a large number of ADDF instructions with
* clock events active. It will ensure that:
* 1. A clock event occurrs during the ADDF sequence, and
* 2. the result of the add sequence is correct.
*
* At each clock interrupt the ADDF's should be stopped and the queue
* cleared. If the queue isn't cleared then we'll get too many ADDF
* operations run and end up with the wrong result.
* The ADDFs will be run with cache misses and with cache hits.
* There is a finite chance that the clock event will occur after we
* have reset the RTC_OCCURRED flag but before the ADDFs have started
* or that it will have occurred after the ADDFs were done but before
* we check the flag again. With 128 ADDFs the chance is small but to
* be sure, we'll do it all twice. What the hell.
* This routine uses the special clock event handler found in the
* test initializer.
*********************************************************************
*/
pipe17()
{
precision = SGL;
exp_event = FALSE; /* don't expect fpp events */
sgl_value_1 = 0x40800000; /* add floating +1.0's */
sgl_expected = 0x44000000; /* expect a floating +128 */
i_cache_hit = FALSE; /* run with cache misses */
test_clock_add(); /* test w/ positive Acc. */
test_clock_add(); /* ...run the test twice */
i_cache_hit = TRUE; /* and run with cache hits */
test_clock_add(); /* for 2 more times */
test_clock_add();
sgl_value_1 = 0xc0800000; /* add floating -1.0's */
sgl_expected = 0xc4000000; /* expect a floating -128 */
i_cache_hit = FALSE; /* run with cache misses */
test_clock_add(); /* test w/ negative Acc. */
test_clock_add(); /* ...run the test twice */
i_cache_hit = TRUE; /* and run with cache hits */
test_clock_add(); /* for 2 more times */
test_clock_add();
}
/****************************************************************************
*
* Verify that the results of 128 ADDFs is correct.
*
****************************************************************************/
test_clock_add()
{
asm(".globl test_clock_lp"); /* loop from here on errors */
asm("test_clock_lp:");
clock_add(); /* do 128 addf's */
if( !rtc_occurred )
who_pulled_the_plug(); /* something is wrong here */
else { /* we got a clock event!! */
asm("stf _sgl_st_acc"); /* store the Accumlator */
if( sgl_st_acc != sgl_expected )
{
errcnt++; /* bump the error count */
if( prt_error )
print_clock_er(); /* print the error message */
if( halt_flg )
pipe17_halt( 1 ); /* halt with a code of 1 */
if( loop_on_err ) {
force_loop = TRUE; /* loop on the error */
asm("jmp test_clock_lp");
}
} /* end of store error */
} /* end of clock event found */
}
/****************************************************************************
*
* DO 128 SINGLE PRECISION ADDs
*
* Run a series of 128 ADDF instructions with the clock enabled. Run the
* series untill there was a clock event during the series or we run out
* of patience. -It takes a while to run out of patience!!
* If we are running with instruction cache misses then bump the Code Cache
* Key each time through.
*
****************************************************************************/
clock_add()
{
clock_retrys = 1000000; /* allow 1 million retrys */
asm(".globl clock_add_lp"); /* loop from here till RTC */
asm("clock_add_lp:");
if( !i_cache_hit ) {
if( ++Codek >= 255 ) { /* get next key, key = max? */
Codek = 1; /* reset the cache key */
asm("mtpr $1,$23"); /* and purge the cache */
};
asm("mtpr _Codek,$13"); /* Set the new cache key */
};
asm("clrl r0"); /* get a floating '0.0' */
asm("ldf r0"); /* clear the accumulator */
asm("bispsw $0x60"); /* enable ovfl, undfl evts */
asm("mtpr $1,$8"); /* lower IPL -enable clock */
asm("nop");
asm("movl _sgl_value_1,r6"); /* get the operand */
asm("clrl _rtc_occurred"); /* clear clock event flag */
/*
* Now do 128 ADDF instructions
*/
asm("addf r6"); /* ADDF #001 */
asm("addf r6"); /* ADDF #002 */
asm("addf r6"); /* ADDF #003 */
asm("addf r6"); /* ADDF #004 */
asm("addf r6"); /* ADDF #005 */
asm("addf r6"); /* ADDF #006 */
asm("addf r6"); /* ADDF #007 */
asm("addf r6"); /* ADDF #008 */
asm("addf r6"); /* ADDF #009 */
asm("addf r6"); /* ADDF #010 */
asm("addf r6"); /* ADDF #011 */
asm("addf r6"); /* ADDF #012 */
asm("addf r6"); /* ADDF #013 */
asm("addf r6"); /* ADDF #014 */
asm("addf r6"); /* ADDF #015 */
asm("addf r6"); /* ADDF #016 */
asm("addf r6"); /* ADDF #017 */
asm("addf r6"); /* ADDF #018 */
asm("addf r6"); /* ADDF #019 */
asm("addf r6"); /* ADDF #020 */
asm("addf r6"); /* ADDF #021 */
asm("addf r6"); /* ADDF #022 */
asm("addf r6"); /* ADDF #023 */
asm("addf r6"); /* ADDF #024 */
asm("addf r6"); /* ADDF #025 */
asm("addf r6"); /* ADDF #026 */
asm("addf r6"); /* ADDF #027 */
asm("addf r6"); /* ADDF #028 */
asm("addf r6"); /* ADDF #029 */
asm("addf r6"); /* ADDF #030 */
asm("addf r6"); /* ADDF #031 */
asm("addf r6"); /* ADDF #032 */
asm("addf r6"); /* ADDF #033 */
asm("addf r6"); /* ADDF #034 */
asm("addf r6"); /* ADDF #035 */
asm("addf r6"); /* ADDF #036 */
asm("addf r6"); /* ADDF #037 */
asm("addf r6"); /* ADDF #038 */
asm("addf r6"); /* ADDF #039 */
asm("addf r6"); /* ADDF #040 */
asm("addf r6"); /* ADDF #041 */
asm("addf r6"); /* ADDF #042 */
asm("addf r6"); /* ADDF #043 */
asm("addf r6"); /* ADDF #044 */
asm("addf r6"); /* ADDF #045 */
asm("addf r6"); /* ADDF #046 */
asm("addf r6"); /* ADDF #047 */
asm("addf r6"); /* ADDF #048 */
asm("addf r6"); /* ADDF #049 */
asm("addf r6"); /* ADDF #050 */
asm("addf r6"); /* ADDF #051 */
asm("addf r6"); /* ADDF #052 */
asm("addf r6"); /* ADDF #053 */
asm("addf r6"); /* ADDF #054 */
asm("addf r6"); /* ADDF #055 */
asm("addf r6"); /* ADDF #056 */
asm("addf r6"); /* ADDF #057 */
asm("addf r6"); /* ADDF #058 */
asm("addf r6"); /* ADDF #059 */
asm("addf r6"); /* ADDF #060 */
asm("addf r6"); /* ADDF #061 */
asm("addf r6"); /* ADDF #062 */
asm("addf r6"); /* ADDF #063 */
asm("addf r6"); /* ADDF #064 */
asm("addf r6"); /* ADDF #065 */
asm("addf r6"); /* ADDF #066 */
asm("addf r6"); /* ADDF #067 */
asm("addf r6"); /* ADDF #068 */
asm("addf r6"); /* ADDF #069 */
asm("addf r6"); /* ADDF #070 */
asm("addf r6"); /* ADDF #071 */
asm("addf r6"); /* ADDF #072 */
asm("addf r6"); /* ADDF #073 */
asm("addf r6"); /* ADDF #074 */
asm("addf r6"); /* ADDF #075 */
asm("addf r6"); /* ADDF #076 */
asm("addf r6"); /* ADDF #077 */
asm("addf r6"); /* ADDF #078 */
asm("addf r6"); /* ADDF #079 */
asm("addf r6"); /* ADDF #080 */
asm("addf r6"); /* ADDF #081 */
asm("addf r6"); /* ADDF #082 */
asm("addf r6"); /* ADDF #083 */
asm("addf r6"); /* ADDF #084 */
asm("addf r6"); /* ADDF #085 */
asm("addf r6"); /* ADDF #086 */
asm("addf r6"); /* ADDF #087 */
asm("addf r6"); /* ADDF #088 */
asm("addf r6"); /* ADDF #089 */
asm("addf r6"); /* ADDF #090 */
asm("addf r6"); /* ADDF #091 */
asm("addf r6"); /* ADDF #092 */
asm("addf r6"); /* ADDF #093 */
asm("addf r6"); /* ADDF #094 */
asm("addf r6"); /* ADDF #095 */
asm("addf r6"); /* ADDF #096 */
asm("addf r6"); /* ADDF #097 */
asm("addf r6"); /* ADDF #098 */
asm("addf r6"); /* ADDF #099 */
asm("addf r6"); /* ADDF #100 */
asm("addf r6"); /* ADDF #101 */
asm("addf r6"); /* ADDF #102 */
asm("addf r6"); /* ADDF #103 */
asm("addf r6"); /* ADDF #104 */
asm("addf r6"); /* ADDF #105 */
asm("addf r6"); /* ADDF #106 */
asm("addf r6"); /* ADDF #107 */
asm("addf r6"); /* ADDF #108 */
asm("addf r6"); /* ADDF #109 */
asm("addf r6"); /* ADDF #110 */
asm("addf r6"); /* ADDF #111 */
asm("addf r6"); /* ADDF #112 */
asm("addf r6"); /* ADDF #113 */
asm("addf r6"); /* ADDF #114 */
asm("addf r6"); /* ADDF #115 */
asm("addf r6"); /* ADDF #116 */
asm("addf r6"); /* ADDF #117 */
asm("addf r6"); /* ADDF #118 */
asm("addf r6"); /* ADDF #119 */
asm("addf r6"); /* ADDF #120 */
asm("addf r6"); /* ADDF #121 */
asm("addf r6"); /* ADDF #122 */
asm("addf r6"); /* ADDF #123 */
asm("addf r6"); /* ADDF #124 */
asm("addf r6"); /* ADDF #125 */
asm("addf r6"); /* ADDF #126 */
asm("addf r6"); /* ADDF #127 */
asm("addf r6"); /* ADDF #128 */
/*
* Thank god that's over with!!! now raise the IPL
*/
asm("mtpr $0x1f,$8"); /* disable clock events */
if( ( force_loop ) ||
( (clock_retrys-- ) && /* keep trying to get */
(!rtc_occurred) ) ) /* a clock event */
asm("jmp clock_add_lp");;
asm("bicpsw $0x60"); /* disable ovfl & undfl */
}
/****************************************************************************
* Report an Bad Result Error
*
* Cycle: xx. EVT test xx. subtest xx. wrong ADDF result with Clock Events
* Testing clock event during 128 ADDF's. -instruction cache {hits / misses}
* operand = xxxxxxxx, result = xxxxxxxx, expected = xxxxxxxx
****************************************************************************/
print_clock_er()
{
if( !error ) { /* 1st error? */
writes(" \n"); /* start a new print line */
error = TRUE;
}
writes("Cycle: ");
writed( cycle );
writes(" EVT test ");
writed( test_no );
writes(". subtest ");
writed( subtest );
writes(". wrong ADDF result with Clock Events\n");
writes(
"Testing clock event during 128 ADDF's with instruction cache ");
if( i_cache_hit )
writes("hits\n");
else
writes("misses\n");
writes("operand = ");
write32h( sgl_value_1 ); /* write the operand */
writes(", result = ");
write32h( sgl_st_acc );
writes(", expected = ");
write32h( sgl_expected );
writec('\n');
}
/****************************************************************************
* Report that no clock events were seen
*
* Cycle: xx. EVT test xx. subtest xx. no Clock Events were detected
* Testing clock event during 128 ADDF's. -instruction cache {hits / misses}
****************************************************************************/
who_pulled_the_plug()
{
if( prt_error )
{
if( !error ) { /* 1st error? */
writes(" \n"); /* start a new print line */
error = TRUE;
}
writes("Cycle: ");
writed( cycle );
writes(" EVT test ");
writed( test_no );
writes(". subtest ");
writed( subtest );
writes(". No Clock Events were detected\n");
writes(
"\nTesting clock event during 128 ADDF's with instruction cache ");
if( i_cache_hit )
writes("hits\n");
else
writes("misses\n");
}
if( halt_flg )
pipe17_halt( 2 ); /* halt with code = 2 */
}
/****************************************************************************
* halt on error routine
****************************************************************************/
pipe17_halt( code )
int code; /* error code to halt with */
{
err_code = code;
asm("movl _test_no,r0"); /* r0 = test number */
asm("movl _subtest,r1"); /* r1 = subtest number */
asm("movl _err_code,r2"); /* r2 = error code */
asm("movl _cycle,r3"); /* r3 = cycle count */
asm("movl _sgl_value_1,r4"); /* r4 = operand used */
asm("movl _sgl_st_acc,r5"); /* r5 = final value */
asm("movl _sgl_expected,r6"); /* r6 = expected value */
asm("movl _i_cache_hit,r7"); /* r7 = 1 if cache hits */
asm("halt"); /* HALT ... */
}
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.