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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / fpevent|
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1.1 ! root 1: 1 00000000 LL0: ! 2: 2 00000000 .data ! 3: 3 000004a8 * .text ! 4: 4 00000000 .align 1 ! 5: 5 00000000 .globl _pipe17 ! 6: 6 00000000 _pipe17: ! 7: 7 00014B14 0000 .word L381 ! 8: 8 00014B16 # ! 9: 9 00014B16 # #include "evt_defs.h" ! 10: 10 00014B16 # ! 11: 11 00014B16 # /* ! 12: 12 00014B16 # ********************************************************************* ! 13: 13 00014B16 # * FPP PIPELINED EVENTS TEST #17 ! 14: 14 00014B16 # * ! 15: 15 00014B16 # * This test will execute a large number of ADDF instructions with ! 16: 16 00014B16 # * clock events active. It will ensure that: ! 17: 17 00014B16 # * 1. A clock event occurrs during the ADDF sequence, and ! 18: 18 00014B16 # * 2. the result of the add sequence is correct. ! 19: 19 00014B16 # * ! 20: 20 00014B16 # * At each clock interrupt the ADDF's should be stopped and the queue ! 21: 21 00014B16 # * cleared. If the queue isn't cleared then we'll get too many ADDF ! 22: 22 00014B16 # * operations run and end up with the wrong result. ! 23: 23 00014B16 # * The ADDFs will be run with cache misses and with cache hits. ! 24: 24 00014B16 # * There is a finite chance that the clock event will occur after we ! 25: 25 00014B16 # * have reset the RTC_OCCURRED flag but before the ADDFs have started ! 26: 26 00014B16 # * or that it will have occurred after the ADDFs were done but before ! 27: 27 00014B16 # * we check the flag again. With 128 ADDFs the chance is small but to ! 28: 28 00014B16 # * be sure, we'll do it all twice. What the hell. ! 29: 29 00014B16 # * This routine uses the special clock event handler found in the ! 30: 30 00014B16 # * test initializer. ! 31: 31 00014B16 # ********************************************************************* ! 32: 32 00014B16 # */ ! 33: 33 00014B16 # pipe17() ! 34: 34 00014B16 # { ! 35: 35 00014B16 13 008c jbr L383 ! 36: 36 00014B19 L384: ! 37: 37 00014B19 # precision = SGL; ! 38: 38 00014B19 0d 01 effffffff4 movl $1,_precision ! 39: 39 00014B20 # exp_event = FALSE; /* don't expect fpp events */ ! 40: 40 00014B20 4d efffffffee clrl _exp_event ! 41: 41 00014B26 # sgl_value_1 = 0x40800000; /* add floating +1.0's */ ! 42: 42 00014B26 0d 8f40800000 efffffffe3 movl $1082130432,_sgl_value_1 ! 43: 43 00014B31 # sgl_expected = 0x44000000; /* expect a floating +128 */ ! 44: 44 00014B31 0d 8f44000000 efffffffd8 movl $1140850688,_sgl_expected ! 45: 45 00014B3C # i_cache_hit = FALSE; /* run with cache misses */ ! 46: 46 00014B3C 4d efffffffd2 clrl _i_cache_hit ! 47: 47 00014B42 # test_clock_add(); /* test w/ positive Acc. */ ! 48: 48 00014B42 fe 04 ef0000005f callf $4,_test_clock_add ! 49: 49 00014B49 # test_clock_add(); /* ...run the test twice */ ! 50: 50 00014B49 fe 04 ef00000058 callf $4,_test_clock_add ! 51: 51 00014B50 # i_cache_hit = TRUE; /* and run with cache hits */ ! 52: 52 00014B50 0d 01 efffffffbd movl $1,_i_cache_hit ! 53: 53 00014B57 # test_clock_add(); /* for 2 more times */ ! 54: 54 00014B57 fe 04 ef0000004a callf $4,_test_clock_add ! 55: 55 00014B5E # test_clock_add(); ! 56: 56 00014B5E fe 04 ef00000043 callf $4,_test_clock_add ! 57: 57 00014B65 # sgl_value_1 = 0xc0800000; /* add floating -1.0's */ ! 58: 58 00014B65 0d 8fc0800000 efffffffa4 movl $-1065353216,_sgl_value_1 ! 59: 59 00014B70 # sgl_expected = 0xc4000000; /* expect a floating -128 */ ! 60: 60 00014B70 0d 8fc4000000 efffffff99 movl $-1006632960,_sgl_expected ! 61: 61 00014B7B # i_cache_hit = FALSE; /* run with cache misses */ ! 62: 62 00014B7B 4d efffffff93 clrl _i_cache_hit ! 63: 63 00014B81 # test_clock_add(); /* test w/ negative Acc. */ ! 64: 64 00014B81 fe 04 ef00000020 callf $4,_test_clock_add ! 65: 65 00014B88 # test_clock_add(); /* ...run the test twice */ ! 66: 66 00014B88 fe 04 ef00000019 callf $4,_test_clock_add ! 67: 67 00014B8F # i_cache_hit = TRUE; /* and run with cache hits */ ! 68: 68 00014B8F 0d 01 efffffff7e movl $1,_i_cache_hit ! 69: 69 00014B96 # test_clock_add(); /* for 2 more times */ ! 70: 70 00014B96 fe 04 ef0000000b callf $4,_test_clock_add ! 71: 71 00014B9D # test_clock_add(); ! 72: 72 00014B9D fe 04 ef00000004 callf $4,_test_clock_add ! 73: 73 00014BA4 # } ! 74: 74 00014BA4 40 ret#2 ! 75: 75 00014BA5 .set L381,0x0 ! 76: 76 00014BA5 L383: ! 77: 77 00014BA5 13 ff71 jbr L384 ! 78: 78 00014BA8 .data ! 79: 79 000004a8 * .text ! 80: 80 00014BA8 .align 1 ! 81: 81 00014BA8 .globl _test_clock_add ! 82: 82 00014BA8 _test_clock_add: ! 83: 83 00014BA8 0000 .word L386 ! 84: 84 00014BAA # ! 85: 85 00014BAA # ! 86: 86 00014BAA # ! 87: 87 00014BAA # /**************************************************************************** ! 88: 88 00014BAA # * ! 89: 89 00014BAA # * Verify that the results of 128 ADDFs is correct. ! 90: 90 00014BAA # * ! 91: 91 00014BAA # ****************************************************************************/ ! 92: 92 00014BAA # test_clock_add() ! 93: 93 00014BAA # { ! 94: 94 00014BAA 11 67 jbr L388 ! 95: 95 00014BAC L389: ! 96: 96 00014BAC # asm(".globl test_clock_lp"); /* loop from here on errors */ ! 97: 97 00014BAC .globl test_clock_lp ! 98: 98 00014BAC # asm("test_clock_lp:"); ! 99: 99 00014BAC test_clock_lp: ! 100: 100 00014BAC # clock_add(); /* do 128 addf's */ ! 101: 101 00014BAC fe 04 ef00000063 callf $4,_clock_add ! 102: 102 00014BB3 # if( !rtc_occurred ) ! 103: 103 00014BB3 5d efffffff5b tstl _rtc_occurred ! 104: 104 00014BB9 21 09 jneq L391 ! 105: 105 00014BBB # who_pulled_the_plug(); /* something is wrong here */ ! 106: 106 00014BBB fe 04 ef000002e2 callf $4,_who_pulled_the_plug ! 107: 107 00014BC2 # else { /* we got a clock event!! */ ! 108: 108 00014BC2 11 4e jbr L393 ! 109: 109 00014BC4 L391: ! 110: 110 00014BC4 # asm("stf _sgl_st_acc"); /* store the Accumlator */ ! 111: 111 00014BC4 26 efffffff4a stf _sgl_st_acc ! 112: 112 00014BCA # if( sgl_st_acc != sgl_expected ) ! 113: 113 00014BCA 1d efffffff44 efffffff3f cmpl _sgl_st_acc,_sgl_expected ! 114: 114 00014BD5 31 3b jeql L394 ! 115: 115 00014BD7 # { ! 116: 116 00014BD7 # errcnt++; /* bump the error count */ ! 117: 117 00014BD7 6d efffffff37 incl _errcnt ! 118: 118 00014BDD # if( prt_error ) ! 119: 119 00014BDD 5d efffffff31 tstl _prt_error ! 120: 120 00014BE3 31 07 jeql L395 ! 121: 121 00014BE5 # print_clock_er(); /* print the error message */ ! 122: 122 00014BE5 fe 04 ef000001b0 callf $4,_print_clock_er ! 123: 123 00014BEC # if( halt_flg ) ! 124: 124 00014BEC L395: ! 125: 125 00014BEC 5d efffffff22 tstl _halt_flg ! 126: 126 00014BF2 31 09 jeql L397 ! 127: 127 00014BF4 # pipe17_halt( 1 ); /* halt with a code of 1 */ ! 128: 128 00014BF4 dd 01 pushl $1 ! 129: 129 00014BF6 fe 08 ef00000375 callf $8,_pipe17_halt ! 130: 130 00014BFD # if( loop_on_err ) { ! 131: 131 00014BFD L397: ! 132: 132 00014BFD 5d efffffff11 tstl _loop_on_err ! 133: 133 00014C03 31 0d jeql L399 ! 134: 134 00014C05 # force_loop = TRUE; /* loop on the error */ ! 135: 135 00014C05 0d 01 efffffff08 movl $1,_force_loop ! 136: 136 00014C0C # asm("jmp test_clock_lp"); ! 137: 137 00014C0C 71 efffffff9a jmp test_clock_lp ! 138: 138 00014C12 # } ! 139: 139 00014C12 # } /* end of store error */ ! 140: 140 00014C12 L399: ! 141: 141 00014C12 # } /* end of clock event found */ ! 142: 142 00014C12 L394: ! 143: 143 00014C12 L393: ! 144: 144 00014C12 # } ! 145: 145 00014C12 40 ret#2 ! 146: 146 00014C13 .set L386,0x0 ! 147: 147 00014C13 L388: ! 148: 148 00014C13 11 97 jbr L389 ! 149: 149 00014C15 .data ! 150: 150 000004a8 * .text ! 151: 151 00014C15 00 .align 1 ! 152: 152 00014C16 .globl _clock_add ! 153: 153 00014C16 _clock_add: ! 154: 154 00014C16 0000 .word L400 ! 155: 155 00014C18 # ! 156: 156 00014C18 # ! 157: 157 00014C18 # ! 158: 158 00014C18 # ! 159: 159 00014C18 # ! 160: 160 00014C18 # ! 161: 161 00014C18 # /**************************************************************************** ! 162: 162 00014C18 # * ! 163: 163 00014C18 # * DO 128 SINGLE PRECISION ADDs ! 164: 164 00014C18 # * ! 165: 165 00014C18 # * Run a series of 128 ADDF instructions with the clock enabled. Run the ! 166: 166 00014C18 # * series untill there was a clock event during the series or we run out ! 167: 167 00014C18 # * of patience. -It takes a while to run out of patience!! ! 168: 168 00014C18 # * If we are running with instruction cache misses then bump the Code Cache ! 169: 169 00014C18 # * Key each time through. ! 170: 170 00014C18 # * ! 171: 171 00014C18 # ****************************************************************************/ ! 172: 172 00014C18 # clock_add() ! 173: 173 00014C18 # { ! 174: 174 00014C18 13 017e jbr L402 ! 175: 175 00014C1B L403: ! 176: 176 00014C1B # clock_retrys = 1000000; /* allow 1 million retrys */ ! 177: 177 00014C1B 0d 8f000f4240 effffffeee movl $1000000,_clock_retrys ! 178: 178 00014C26 # asm(".globl clock_add_lp"); /* loop from here till RTC */ ! 179: 179 00014C26 .globl clock_add_lp ! 180: 180 00014C26 # asm("clock_add_lp:"); ! 181: 181 00014C26 clock_add_lp: ! 182: 182 00014C26 # if( !i_cache_hit ) { ! 183: 183 00014C26 5d effffffee8 tstl _i_cache_hit ! 184: 184 00014C2C 21 25 jneq L404 ! 185: 185 00014C2E # if( ++Codek >= 255 ) { /* get next key, key = max? */ ! 186: 186 00014C2E 6d effffffee0 incl _Codek ! 187: 187 00014C34 0d effffffeda 50 movl _Codek,r0 ! 188: 188 00014C3B 1d 50 8900ff cmpl r0,$255 ! 189: 189 00014C40 91 0a jlss L405 ! 190: 190 00014C42 # Codek = 1; /* reset the cache key */ ! 191: 191 00014C42 0d 01 effffffecb movl $1,_Codek ! 192: 192 00014C49 # asm("mtpr $1,$23"); /* and purge the cache */ ! 193: 193 00014C49 ad 01 17 mtpr $1,$23 ! 194: 194 00014C4C # }; ! 195: 195 00014C4C L405: ! 196: 196 00014C4C # asm("mtpr _Codek,$13"); /* Set the new cache key */ ! 197: 197 00014C4C ad effffffec2 0d mtpr _Codek,$13 ! 198: 198 00014C53 # }; ! 199: 199 00014C53 L404: ! 200: 200 00014C53 # asm("clrl r0"); /* get a floating '0.0' */ ! 201: 201 00014C53 4d 50 clrl r0 ! 202: 202 00014C55 # asm("ldf r0"); /* clear the accumulator */ ! 203: 203 00014C55 06 50 ldf r0 ! 204: 204 00014C57 # asm("bispsw $0x60"); /* enable ovfl, undfl evts */ ! 205: 205 00014C57 8b 8860 bispsw $0x60 ! 206: 206 00014C5A # asm("mtpr $1,$8"); /* lower IPL -enable clock */ ! 207: 207 00014C5A ad 01 08 mtpr $1,$8 ! 208: 208 00014C5D # asm("nop"); ! 209: 209 00014C5D 10 nop ! 210: 210 00014C5E # asm("movl _sgl_value_1,r6"); /* get the operand */ ! 211: 211 00014C5E 0d effffffeb0 56 movl _sgl_value_1,r6 ! 212: 212 00014C65 # asm("clrl _rtc_occurred"); /* clear clock event flag */ ! 213: 213 00014C65 4d effffffea9 clrl _rtc_occurred ! 214: 214 00014C6B # ! 215: 215 00014C6B # /* ! 216: 216 00014C6B # * Now do 128 ADDF instructions ! 217: 217 00014C6B # */ ! 218: 218 00014C6B # asm("addf r6"); /* ADDF #001 */ ! 219: 219 00014C6B c6 56 addf r6 ! 220: 220 00014C6D # asm("addf r6"); /* ADDF #002 */ ! 221: 221 00014C6D c6 56 addf r6 ! 222: 222 00014C6F # asm("addf r6"); /* ADDF #003 */ ! 223: 223 00014C6F c6 56 addf r6 ! 224: 224 00014C71 # asm("addf r6"); /* ADDF #004 */ ! 225: 225 00014C71 c6 56 addf r6 ! 226: 226 00014C73 # asm("addf r6"); /* ADDF #005 */ ! 227: 227 00014C73 c6 56 addf r6 ! 228: 228 00014C75 # asm("addf r6"); /* ADDF #006 */ ! 229: 229 00014C75 c6 56 addf r6 ! 230: 230 00014C77 # asm("addf r6"); /* ADDF #007 */ ! 231: 231 00014C77 c6 56 addf r6 ! 232: 232 00014C79 # asm("addf r6"); /* ADDF #008 */ ! 233: 233 00014C79 c6 56 addf r6 ! 234: 234 00014C7B # asm("addf r6"); /* ADDF #009 */ ! 235: 235 00014C7B c6 56 addf r6 ! 236: 236 00014C7D # asm("addf r6"); /* ADDF #010 */ ! 237: 237 00014C7D c6 56 addf r6 ! 238: 238 00014C7F # asm("addf r6"); /* ADDF #011 */ ! 239: 239 00014C7F c6 56 addf r6 ! 240: 240 00014C81 # asm("addf r6"); /* ADDF #012 */ ! 241: 241 00014C81 c6 56 addf r6 ! 242: 242 00014C83 # asm("addf r6"); /* ADDF #013 */ ! 243: 243 00014C83 c6 56 addf r6 ! 244: 244 00014C85 # asm("addf r6"); /* ADDF #014 */ ! 245: 245 00014C85 c6 56 addf r6 ! 246: 246 00014C87 # asm("addf r6"); /* ADDF #015 */ ! 247: 247 00014C87 c6 56 addf r6 ! 248: 248 00014C89 # asm("addf r6"); /* ADDF #016 */ ! 249: 249 00014C89 c6 56 addf r6 ! 250: 250 00014C8B # asm("addf r6"); /* ADDF #017 */ ! 251: 251 00014C8B c6 56 addf r6 ! 252: 252 00014C8D # asm("addf r6"); /* ADDF #018 */ ! 253: 253 00014C8D c6 56 addf r6 ! 254: 254 00014C8F # asm("addf r6"); /* ADDF #019 */ ! 255: 255 00014C8F c6 56 addf r6 ! 256: 256 00014C91 # asm("addf r6"); /* ADDF #020 */ ! 257: 257 00014C91 c6 56 addf r6 ! 258: 258 00014C93 # asm("addf r6"); /* ADDF #021 */ ! 259: 259 00014C93 c6 56 addf r6 ! 260: 260 00014C95 # asm("addf r6"); /* ADDF #022 */ ! 261: 261 00014C95 c6 56 addf r6 ! 262: 262 00014C97 # asm("addf r6"); /* ADDF #023 */ ! 263: 263 00014C97 c6 56 addf r6 ! 264: 264 00014C99 # asm("addf r6"); /* ADDF #024 */ ! 265: 265 00014C99 c6 56 addf r6 ! 266: 266 00014C9B # asm("addf r6"); /* ADDF #025 */ ! 267: 267 00014C9B c6 56 addf r6 ! 268: 268 00014C9D # asm("addf r6"); /* ADDF #026 */ ! 269: 269 00014C9D c6 56 addf r6 ! 270: 270 00014C9F # asm("addf r6"); /* ADDF #027 */ ! 271: 271 00014C9F c6 56 addf r6 ! 272: 272 00014CA1 # asm("addf r6"); /* ADDF #028 */ ! 273: 273 00014CA1 c6 56 addf r6 ! 274: 274 00014CA3 # asm("addf r6"); /* ADDF #029 */ ! 275: 275 00014CA3 c6 56 addf r6 ! 276: 276 00014CA5 # asm("addf r6"); /* ADDF #030 */ ! 277: 277 00014CA5 c6 56 addf r6 ! 278: 278 00014CA7 # asm("addf r6"); /* ADDF #031 */ ! 279: 279 00014CA7 c6 56 addf r6 ! 280: 280 00014CA9 # asm("addf r6"); /* ADDF #032 */ ! 281: 281 00014CA9 c6 56 addf r6 ! 282: 282 00014CAB # asm("addf r6"); /* ADDF #033 */ ! 283: 283 00014CAB c6 56 addf r6 ! 284: 284 00014CAD # asm("addf r6"); /* ADDF #034 */ ! 285: 285 00014CAD c6 56 addf r6 ! 286: 286 00014CAF # asm("addf r6"); /* ADDF #035 */ ! 287: 287 00014CAF c6 56 addf r6 ! 288: 288 00014CB1 # asm("addf r6"); /* ADDF #036 */ ! 289: 289 00014CB1 c6 56 addf r6 ! 290: 290 00014CB3 # asm("addf r6"); /* ADDF #037 */ ! 291: 291 00014CB3 c6 56 addf r6 ! 292: 292 00014CB5 # asm("addf r6"); /* ADDF #038 */ ! 293: 293 00014CB5 c6 56 addf r6 ! 294: 294 00014CB7 # asm("addf r6"); /* ADDF #039 */ ! 295: 295 00014CB7 c6 56 addf r6 ! 296: 296 00014CB9 # asm("addf r6"); /* ADDF #040 */ ! 297: 297 00014CB9 c6 56 addf r6 ! 298: 298 00014CBB # asm("addf r6"); /* ADDF #041 */ ! 299: 299 00014CBB c6 56 addf r6 ! 300: 300 00014CBD # asm("addf r6"); /* ADDF #042 */ ! 301: 301 00014CBD c6 56 addf r6 ! 302: 302 00014CBF # asm("addf r6"); /* ADDF #043 */ ! 303: 303 00014CBF c6 56 addf r6 ! 304: 304 00014CC1 # asm("addf r6"); /* ADDF #044 */ ! 305: 305 00014CC1 c6 56 addf r6 ! 306: 306 00014CC3 # asm("addf r6"); /* ADDF #045 */ ! 307: 307 00014CC3 c6 56 addf r6 ! 308: 308 00014CC5 # asm("addf r6"); /* ADDF #046 */ ! 309: 309 00014CC5 c6 56 addf r6 ! 310: 310 00014CC7 # asm("addf r6"); /* ADDF #047 */ ! 311: 311 00014CC7 c6 56 addf r6 ! 312: 312 00014CC9 # asm("addf r6"); /* ADDF #048 */ ! 313: 313 00014CC9 c6 56 addf r6 ! 314: 314 00014CCB # asm("addf r6"); /* ADDF #049 */ ! 315: 315 00014CCB c6 56 addf r6 ! 316: 316 00014CCD # asm("addf r6"); /* ADDF #050 */ ! 317: 317 00014CCD c6 56 addf r6 ! 318: 318 00014CCF # asm("addf r6"); /* ADDF #051 */ ! 319: 319 00014CCF c6 56 addf r6 ! 320: 320 00014CD1 # asm("addf r6"); /* ADDF #052 */ ! 321: 321 00014CD1 c6 56 addf r6 ! 322: 322 00014CD3 # asm("addf r6"); /* ADDF #053 */ ! 323: 323 00014CD3 c6 56 addf r6 ! 324: 324 00014CD5 # asm("addf r6"); /* ADDF #054 */ ! 325: 325 00014CD5 c6 56 addf r6 ! 326: 326 00014CD7 # asm("addf r6"); /* ADDF #055 */ ! 327: 327 00014CD7 c6 56 addf r6 ! 328: 328 00014CD9 # asm("addf r6"); /* ADDF #056 */ ! 329: 329 00014CD9 c6 56 addf r6 ! 330: 330 00014CDB # asm("addf r6"); /* ADDF #057 */ ! 331: 331 00014CDB c6 56 addf r6 ! 332: 332 00014CDD # asm("addf r6"); /* ADDF #058 */ ! 333: 333 00014CDD c6 56 addf r6 ! 334: 334 00014CDF # asm("addf r6"); /* ADDF #059 */ ! 335: 335 00014CDF c6 56 addf r6 ! 336: 336 00014CE1 # asm("addf r6"); /* ADDF #060 */ ! 337: 337 00014CE1 c6 56 addf r6 ! 338: 338 00014CE3 # asm("addf r6"); /* ADDF #061 */ ! 339: 339 00014CE3 c6 56 addf r6 ! 340: 340 00014CE5 # asm("addf r6"); /* ADDF #062 */ ! 341: 341 00014CE5 c6 56 addf r6 ! 342: 342 00014CE7 # asm("addf r6"); /* ADDF #063 */ ! 343: 343 00014CE7 c6 56 addf r6 ! 344: 344 00014CE9 # asm("addf r6"); /* ADDF #064 */ ! 345: 345 00014CE9 c6 56 addf r6 ! 346: 346 00014CEB # asm("addf r6"); /* ADDF #065 */ ! 347: 347 00014CEB c6 56 addf r6 ! 348: 348 00014CED # asm("addf r6"); /* ADDF #066 */ ! 349: 349 00014CED c6 56 addf r6 ! 350: 350 00014CEF # asm("addf r6"); /* ADDF #067 */ ! 351: 351 00014CEF c6 56 addf r6 ! 352: 352 00014CF1 # asm("addf r6"); /* ADDF #068 */ ! 353: 353 00014CF1 c6 56 addf r6 ! 354: 354 00014CF3 # asm("addf r6"); /* ADDF #069 */ ! 355: 355 00014CF3 c6 56 addf r6 ! 356: 356 00014CF5 # asm("addf r6"); /* ADDF #070 */ ! 357: 357 00014CF5 c6 56 addf r6 ! 358: 358 00014CF7 # asm("addf r6"); /* ADDF #071 */ ! 359: 359 00014CF7 c6 56 addf r6 ! 360: 360 00014CF9 # asm("addf r6"); /* ADDF #072 */ ! 361: 361 00014CF9 c6 56 addf r6 ! 362: 362 00014CFB # asm("addf r6"); /* ADDF #073 */ ! 363: 363 00014CFB c6 56 addf r6 ! 364: 364 00014CFD # asm("addf r6"); /* ADDF #074 */ ! 365: 365 00014CFD c6 56 addf r6 ! 366: 366 00014CFF # asm("addf r6"); /* ADDF #075 */ ! 367: 367 00014CFF c6 56 addf r6 ! 368: 368 00014D01 # asm("addf r6"); /* ADDF #076 */ ! 369: 369 00014D01 c6 56 addf r6 ! 370: 370 00014D03 # asm("addf r6"); /* ADDF #077 */ ! 371: 371 00014D03 c6 56 addf r6 ! 372: 372 00014D05 # asm("addf r6"); /* ADDF #078 */ ! 373: 373 00014D05 c6 56 addf r6 ! 374: 374 00014D07 # asm("addf r6"); /* ADDF #079 */ ! 375: 375 00014D07 c6 56 addf r6 ! 376: 376 00014D09 # asm("addf r6"); /* ADDF #080 */ ! 377: 377 00014D09 c6 56 addf r6 ! 378: 378 00014D0B # asm("addf r6"); /* ADDF #081 */ ! 379: 379 00014D0B c6 56 addf r6 ! 380: 380 00014D0D # asm("addf r6"); /* ADDF #082 */ ! 381: 381 00014D0D c6 56 addf r6 ! 382: 382 00014D0F # asm("addf r6"); /* ADDF #083 */ ! 383: 383 00014D0F c6 56 addf r6 ! 384: 384 00014D11 # asm("addf r6"); /* ADDF #084 */ ! 385: 385 00014D11 c6 56 addf r6 ! 386: 386 00014D13 # asm("addf r6"); /* ADDF #085 */ ! 387: 387 00014D13 c6 56 addf r6 ! 388: 388 00014D15 # asm("addf r6"); /* ADDF #086 */ ! 389: 389 00014D15 c6 56 addf r6 ! 390: 390 00014D17 # asm("addf r6"); /* ADDF #087 */ ! 391: 391 00014D17 c6 56 addf r6 ! 392: 392 00014D19 # asm("addf r6"); /* ADDF #088 */ ! 393: 393 00014D19 c6 56 addf r6 ! 394: 394 00014D1B # asm("addf r6"); /* ADDF #089 */ ! 395: 395 00014D1B c6 56 addf r6 ! 396: 396 00014D1D # asm("addf r6"); /* ADDF #090 */ ! 397: 397 00014D1D c6 56 addf r6 ! 398: 398 00014D1F # asm("addf r6"); /* ADDF #091 */ ! 399: 399 00014D1F c6 56 addf r6 ! 400: 400 00014D21 # asm("addf r6"); /* ADDF #092 */ ! 401: 401 00014D21 c6 56 addf r6 ! 402: 402 00014D23 # asm("addf r6"); /* ADDF #093 */ ! 403: 403 00014D23 c6 56 addf r6 ! 404: 404 00014D25 # asm("addf r6"); /* ADDF #094 */ ! 405: 405 00014D25 c6 56 addf r6 ! 406: 406 00014D27 # asm("addf r6"); /* ADDF #095 */ ! 407: 407 00014D27 c6 56 addf r6 ! 408: 408 00014D29 # asm("addf r6"); /* ADDF #096 */ ! 409: 409 00014D29 c6 56 addf r6 ! 410: 410 00014D2B # asm("addf r6"); /* ADDF #097 */ ! 411: 411 00014D2B c6 56 addf r6 ! 412: 412 00014D2D # asm("addf r6"); /* ADDF #098 */ ! 413: 413 00014D2D c6 56 addf r6 ! 414: 414 00014D2F # asm("addf r6"); /* ADDF #099 */ ! 415: 415 00014D2F c6 56 addf r6 ! 416: 416 00014D31 # asm("addf r6"); /* ADDF #100 */ ! 417: 417 00014D31 c6 56 addf r6 ! 418: 418 00014D33 # asm("addf r6"); /* ADDF #101 */ ! 419: 419 00014D33 c6 56 addf r6 ! 420: 420 00014D35 # asm("addf r6"); /* ADDF #102 */ ! 421: 421 00014D35 c6 56 addf r6 ! 422: 422 00014D37 # asm("addf r6"); /* ADDF #103 */ ! 423: 423 00014D37 c6 56 addf r6 ! 424: 424 00014D39 # asm("addf r6"); /* ADDF #104 */ ! 425: 425 00014D39 c6 56 addf r6 ! 426: 426 00014D3B # asm("addf r6"); /* ADDF #105 */ ! 427: 427 00014D3B c6 56 addf r6 ! 428: 428 00014D3D # asm("addf r6"); /* ADDF #106 */ ! 429: 429 00014D3D c6 56 addf r6 ! 430: 430 00014D3F # asm("addf r6"); /* ADDF #107 */ ! 431: 431 00014D3F c6 56 addf r6 ! 432: 432 00014D41 # asm("addf r6"); /* ADDF #108 */ ! 433: 433 00014D41 c6 56 addf r6 ! 434: 434 00014D43 # asm("addf r6"); /* ADDF #109 */ ! 435: 435 00014D43 c6 56 addf r6 ! 436: 436 00014D45 # asm("addf r6"); /* ADDF #110 */ ! 437: 437 00014D45 c6 56 addf r6 ! 438: 438 00014D47 # asm("addf r6"); /* ADDF #111 */ ! 439: 439 00014D47 c6 56 addf r6 ! 440: 440 00014D49 # asm("addf r6"); /* ADDF #112 */ ! 441: 441 00014D49 c6 56 addf r6 ! 442: 442 00014D4B # asm("addf r6"); /* ADDF #113 */ ! 443: 443 00014D4B c6 56 addf r6 ! 444: 444 00014D4D # asm("addf r6"); /* ADDF #114 */ ! 445: 445 00014D4D c6 56 addf r6 ! 446: 446 00014D4F # asm("addf r6"); /* ADDF #115 */ ! 447: 447 00014D4F c6 56 addf r6 ! 448: 448 00014D51 # asm("addf r6"); /* ADDF #116 */ ! 449: 449 00014D51 c6 56 addf r6 ! 450: 450 00014D53 # asm("addf r6"); /* ADDF #117 */ ! 451: 451 00014D53 c6 56 addf r6 ! 452: 452 00014D55 # asm("addf r6"); /* ADDF #118 */ ! 453: 453 00014D55 c6 56 addf r6 ! 454: 454 00014D57 # asm("addf r6"); /* ADDF #119 */ ! 455: 455 00014D57 c6 56 addf r6 ! 456: 456 00014D59 # asm("addf r6"); /* ADDF #120 */ ! 457: 457 00014D59 c6 56 addf r6 ! 458: 458 00014D5B # asm("addf r6"); /* ADDF #121 */ ! 459: 459 00014D5B c6 56 addf r6 ! 460: 460 00014D5D # asm("addf r6"); /* ADDF #122 */ ! 461: 461 00014D5D c6 56 addf r6 ! 462: 462 00014D5F # asm("addf r6"); /* ADDF #123 */ ! 463: 463 00014D5F c6 56 addf r6 ! 464: 464 00014D61 # asm("addf r6"); /* ADDF #124 */ ! 465: 465 00014D61 c6 56 addf r6 ! 466: 466 00014D63 # asm("addf r6"); /* ADDF #125 */ ! 467: 467 00014D63 c6 56 addf r6 ! 468: 468 00014D65 # asm("addf r6"); /* ADDF #126 */ ! 469: 469 00014D65 c6 56 addf r6 ! 470: 470 00014D67 # asm("addf r6"); /* ADDF #127 */ ! 471: 471 00014D67 c6 56 addf r6 ! 472: 472 00014D69 # asm("addf r6"); /* ADDF #128 */ ! 473: 473 00014D69 c6 56 addf r6 ! 474: 474 00014D6B # /* ! 475: 475 00014D6B # * Thank god that's over with!!! now raise the IPL ! 476: 476 00014D6B # */ ! 477: 477 00014D6B # ! 478: 478 00014D6B # asm("mtpr $0x1f,$8"); /* disable clock events */ ! 479: 479 00014D6B ad 1f 08 mtpr $0x1f,$8 ! 480: 480 00014D6E # if( ( force_loop ) || ! 481: 481 00014D6E # ( (clock_retrys-- ) && /* keep trying to get */ ! 482: 482 00014D6E # (!rtc_occurred) ) ) /* a clock event */ ! 483: 483 00014D6E 5d effffffda0 tstl _force_loop ! 484: 484 00014D74 21 19 jneq L9999 ! 485: 485 00014D76 0d effffffd98 50 movl _clock_retrys,r0 ! 486: 486 00014D7D 7d effffffd91 decl _clock_retrys ! 487: 487 00014D83 5d 50 tstl r0 ! 488: 488 00014D85 31 0e jeql L406 ! 489: 489 00014D87 5d effffffd87 tstl _rtc_occurred ! 490: 490 00014D8D 21 06 jneq L406 ! 491: 491 00014D8F L9999: ! 492: 492 00014D8F # asm("jmp clock_add_lp");; ! 493: 493 00014D8F 71 effffffe91 jmp clock_add_lp ! 494: 494 00014D95 L406: ! 495: 495 00014D95 # asm("bicpsw $0x60"); /* disable ovfl & undfl */ ! 496: 496 00014D95 9b 8860 bicpsw $0x60 ! 497: 497 00014D98 # } ! 498: 498 00014D98 40 ret#2 ! 499: 499 00014D99 .set L400,0x0 ! 500: 500 00014D99 L402: ! 501: 501 00014D99 13 fe7f jbr L403 ! 502: 502 00014D9C .data ! 503: 503 000004a8 * .text ! 504: 504 00014D9C .align 1 ! 505: 505 00014D9C .globl _print_clock_er ! 506: 506 00014D9C _print_clock_er: ! 507: 507 00014D9C 0000 .word L407 ! 508: 508 00014D9E # ! 509: 509 00014D9E # ! 510: 510 00014D9E # ! 511: 511 00014D9E # ! 512: 512 00014D9E # ! 513: 513 00014D9E # /**************************************************************************** ! 514: 514 00014D9E # * Report an Bad Result Error ! 515: 515 00014D9E # * ! 516: 516 00014D9E # * Cycle: xx. EVT test xx. subtest xx. wrong ADDF result with Clock Events ! 517: 517 00014D9E # * Testing clock event during 128 ADDF's. -instruction cache {hits / misses} ! 518: 518 00014D9E # * operand = xxxxxxxx, result = xxxxxxxx, expected = xxxxxxxx ! 519: 519 00014D9E # ****************************************************************************/ ! 520: 520 00014D9E # print_clock_er() ! 521: 521 00014D9E # { ! 522: 522 00014D9E 13 0100 jbr L409 ! 523: 523 00014DA1 L410: ! 524: 524 00014DA1 # if( !error ) { /* 1st error? */ ! 525: 525 00014DA1 5d effffffd6d tstl _error ! 526: 526 00014DA7 21 14 jneq L411 ! 527: 527 00014DA9 # writes(" \n"); /* start a new print line */ ! 528: 528 00014DA9 .data 1 ! 529: 529 000004a8 * L413: ! 530: 530 000004a8 * 200A00 .ascii " \12\0" ! 531: 531 000004ab * .text ! 532: 532 00014DA9 dd 8f000004a8 pushl $L413 ! 533: 533 00014DAF fe 08 effffffd5e callf $8,_writes ! 534: 534 00014DB6 # error = TRUE; ! 535: 535 00014DB6 0d 01 effffffd57 movl $1,_error ! 536: 536 00014DBD # } ! 537: 537 00014DBD # writes("Cycle: "); ! 538: 538 00014DBD L411: ! 539: 539 00014DBD .data 1 ! 540: 540 000004ab * L414: ! 541: 541 000004ab * 4379636C653A2000 .ascii "Cycle: \0" ! 542: 542 000004b3 * .text ! 543: 543 00014DBD dd 8f000004ab pushl $L414 ! 544: 544 00014DC3 fe 08 effffffd4a callf $8,_writes ! 545: 545 00014DCA # writed( cycle ); ! 546: 546 00014DCA dd effffffd44 pushl _cycle ! 547: 547 00014DD0 fe 08 effffffd3d callf $8,_writed ! 548: 548 00014DD7 # writes(" EVT test "); ! 549: 549 00014DD7 .data 1 ! 550: 550 000004b3 * L416: ! 551: 551 000004b3 * 202045565420746573742000 .ascii " EVT test \0" ! 552: 552 000004bf * .text ! 553: 553 00014DD7 dd 8f000004b3 pushl $L416 ! 554: 554 00014DDD fe 08 effffffd30 callf $8,_writes ! 555: 555 00014DE4 # writed( test_no ); ! 556: 556 00014DE4 dd effffffd2a pushl _test_no ! 557: 557 00014DEA fe 08 effffffd23 callf $8,_writed ! 558: 558 00014DF1 # writes(". subtest "); ! 559: 559 00014DF1 .data 1 ! 560: 560 000004bf * L417: ! 561: 561 000004bf * 2E20737562746573742000 .ascii ". subtest \0" ! 562: 562 000004ca * .text ! 563: 563 00014DF1 dd 8f000004bf pushl $L417 ! 564: 564 00014DF7 fe 08 effffffd16 callf $8,_writes ! 565: 565 00014DFE # writed( subtest ); ! 566: 566 00014DFE dd effffffd10 pushl _subtest ! 567: 567 00014E04 fe 08 effffffd09 callf $8,_writed ! 568: 568 00014E0B # writes(". wrong ADDF result with Clock Events\n"); ! 569: 569 00014E0B .data 1 ! 570: 570 000004ca * L418: ! 571: 571 000004ca * 2E202077726F6E67204144444 .ascii ". wrong ADDF result with Clock Events\12\0" ! 572: 620726573756C742077697468 ! 573: 20436C6F636B204576656E747 ! 574: 30A00 ! 575: 572 000004f2 * .text ! 576: 573 00014E0B dd 8f000004ca pushl $L418 ! 577: 574 00014E11 fe 08 effffffcfc callf $8,_writes ! 578: 575 00014E18 # writes( ! 579: 576 00014E18 # "Testing clock event during 128 ADDF's with instruction cache "); ! 580: 577 00014E18 .data 1 ! 581: 578 000004f2 * L419: ! 582: 579 000004f2 * 54657374696E6720636C6F636 .ascii "Testing clock event during 128 ADDF's with instruction cache \0" ! 583: B206576656E7420647572696E ! 584: 6720313238204144444627732 ! 585: 07769746820696E7374727563 ! 586: 74696F6E2063616368652000 ! 587: 580 00000530 * .text ! 588: 581 00014E18 dd 8f000004f2 pushl $L419 ! 589: 582 00014E1E fe 08 effffffcef callf $8,_writes ! 590: 583 00014E25 # if( i_cache_hit ) ! 591: 584 00014E25 5d effffffce9 tstl _i_cache_hit ! 592: 585 00014E2B 31 0f jeql L420 ! 593: 586 00014E2D # writes("hits\n"); ! 594: 587 00014E2D .data 1 ! 595: 588 00000530 * L421: ! 596: 589 00000530 * 686974730A00 .ascii "hits\12\0" ! 597: 590 00000536 * .text ! 598: 591 00014E2D dd 8f00000530 pushl $L421 ! 599: 592 00014E33 fe 08 effffffcda callf $8,_writes ! 600: 593 00014E3A # else ! 601: 594 00014E3A 11 0d jbr L422 ! 602: 595 00014E3C L420: ! 603: 596 00014E3C # writes("misses\n"); ! 604: 597 00014E3C .data 1 ! 605: 598 00000536 * L423: ! 606: 599 00000536 * 6D69737365730A00 .ascii "misses\12\0" ! 607: 600 0000053e * .text ! 608: 601 00014E3C dd 8f00000536 pushl $L423 ! 609: 602 00014E42 fe 08 effffffccb callf $8,_writes ! 610: 603 00014E49 L422: ! 611: 604 00014E49 # writes("operand = "); ! 612: 605 00014E49 .data 1 ! 613: 606 0000053e * L424: ! 614: 607 0000053e * 6F706572616E64203D2000 .ascii "operand = \0" ! 615: 608 00000549 * .text ! 616: 609 00014E49 dd 8f0000053e pushl $L424 ! 617: 610 00014E4F fe 08 effffffcbe callf $8,_writes ! 618: 611 00014E56 # write32h( sgl_value_1 ); /* write the operand */ ! 619: 612 00014E56 dd effffffcb8 pushl _sgl_value_1 ! 620: 613 00014E5C fe 08 effffffcb1 callf $8,_write32h ! 621: 614 00014E63 # writes(", result = "); ! 622: 615 00014E63 .data 1 ! 623: 616 00000549 * L426: ! 624: 617 00000549 * 2C2020726573756C74203D200 .ascii ", result = \0" ! 625: 0 ! 626: 618 00000556 * .text ! 627: 619 00014E63 dd 8f00000549 pushl $L426 ! 628: 620 00014E69 fe 08 effffffca4 callf $8,_writes ! 629: 621 00014E70 # write32h( sgl_st_acc ); ! 630: 622 00014E70 dd effffffc9e pushl _sgl_st_acc ! 631: 623 00014E76 fe 08 effffffc97 callf $8,_write32h ! 632: 624 00014E7D # writes(", expected = "); ! 633: 625 00014E7D .data 1 ! 634: 626 00000556 * L427: ! 635: 627 00000556 * 2C20206578706563746564203 .ascii ", expected = \0" ! 636: D2000 ! 637: 628 00000565 * .text ! 638: 629 00014E7D dd 8f00000556 pushl $L427 ! 639: 630 00014E83 fe 08 effffffc8a callf $8,_writes ! 640: 631 00014E8A # write32h( sgl_expected ); ! 641: 632 00014E8A dd effffffc84 pushl _sgl_expected ! 642: 633 00014E90 fe 08 effffffc7d callf $8,_write32h ! 643: 634 00014E97 # writec('\n'); ! 644: 635 00014E97 dd 0a pushl $10 ! 645: 636 00014E99 fe 08 effffffc74 callf $8,_writec ! 646: 637 00014EA0 # } ! 647: 638 00014EA0 40 ret#2 ! 648: 639 00014EA1 .set L407,0x0 ! 649: 640 00014EA1 L409: ! 650: 641 00014EA1 13 fefd jbr L410 ! 651: 642 00014EA4 .data ! 652: 643 000004a8 * .text ! 653: 644 00014EA4 .align 1 ! 654: 645 00014EA4 .globl _who_pulled_the_plug ! 655: 646 00014EA4 _who_pulled_the_plug: ! 656: 647 00014EA4 0000 .word L429 ! 657: 648 00014EA6 # ! 658: 649 00014EA6 # ! 659: 650 00014EA6 # ! 660: 651 00014EA6 # /**************************************************************************** ! 661: 652 00014EA6 # * Report that no clock events were seen ! 662: 653 00014EA6 # * ! 663: 654 00014EA6 # * Cycle: xx. EVT test xx. subtest xx. no Clock Events were detected ! 664: 655 00014EA6 # * Testing clock event during 128 ADDF's. -instruction cache {hits / misses} ! 665: 656 00014EA6 # ****************************************************************************/ ! 666: 657 00014EA6 # who_pulled_the_plug() ! 667: 658 00014EA6 # { ! 668: 659 00014EA6 13 00c5 jbr L431 ! 669: 660 00014EA9 L432: ! 670: 661 00014EA9 # if( prt_error ) ! 671: 662 00014EA9 5d effffffc65 tstl _prt_error ! 672: 663 00014EAF 21 03 13 00a8 jeql L433 ! 673: 664 00014EB4 # { ! 674: 665 00014EB4 # if( !error ) { /* 1st error? */ ! 675: 666 00014EB4 5d effffffc5a tstl _error ! 676: 667 00014EBA 21 14 jneq L434 ! 677: 668 00014EBC # writes(" \n"); /* start a new print line */ ! 678: 669 00014EBC .data 1 ! 679: 670 00000565 * L435: ! 680: 671 00000565 * 200A00 .ascii " \12\0" ! 681: 672 00000568 * .text ! 682: 673 00014EBC dd 8f00000565 pushl $L435 ! 683: 674 00014EC2 fe 08 effffffc4b callf $8,_writes ! 684: 675 00014EC9 # error = TRUE; ! 685: 676 00014EC9 0d 01 effffffc44 movl $1,_error ! 686: 677 00014ED0 # } ! 687: 678 00014ED0 # writes("Cycle: "); ! 688: 679 00014ED0 L434: ! 689: 680 00014ED0 .data 1 ! 690: 681 00000568 * L436: ! 691: 682 00000568 * 4379636C653A2000 .ascii "Cycle: \0" ! 692: 683 00000570 * .text ! 693: 684 00014ED0 dd 8f00000568 pushl $L436 ! 694: 685 00014ED6 fe 08 effffffc37 callf $8,_writes ! 695: 686 00014EDD # writed( cycle ); ! 696: 687 00014EDD dd effffffc31 pushl _cycle ! 697: 688 00014EE3 fe 08 effffffc2a callf $8,_writed ! 698: 689 00014EEA # writes(" EVT test "); ! 699: 690 00014EEA .data 1 ! 700: 691 00000570 * L437: ! 701: 692 00000570 * 202045565420746573742000 .ascii " EVT test \0" ! 702: 693 0000057c * .text ! 703: 694 00014EEA dd 8f00000570 pushl $L437 ! 704: 695 00014EF0 fe 08 effffffc1d callf $8,_writes ! 705: 696 00014EF7 # writed( test_no ); ! 706: 697 00014EF7 dd effffffc17 pushl _test_no ! 707: 698 00014EFD fe 08 effffffc10 callf $8,_writed ! 708: 699 00014F04 # writes(". subtest "); ! 709: 700 00014F04 .data 1 ! 710: 701 0000057c * L438: ! 711: 702 0000057c * 2E20737562746573742000 .ascii ". subtest \0" ! 712: 703 00000587 * .text ! 713: 704 00014F04 dd 8f0000057c pushl $L438 ! 714: 705 00014F0A fe 08 effffffc03 callf $8,_writes ! 715: 706 00014F11 # writed( subtest ); ! 716: 707 00014F11 dd effffffbfd pushl _subtest ! 717: 708 00014F17 fe 08 effffffbf6 callf $8,_writed ! 718: 709 00014F1E # writes(". No Clock Events were detected\n"); ! 719: 710 00014F1E .data 1 ! 720: 711 00000587 * L439: ! 721: 712 00000587 * 2E20204E6F20436C6F636B204 .ascii ". No Clock Events were detected\12\0" ! 722: 576656E747320776572652064 ! 723: 657465637465640A00 ! 724: 713 000005a9 * .text ! 725: 714 00014F1E dd 8f00000587 pushl $L439 ! 726: 715 00014F24 fe 08 effffffbe9 callf $8,_writes ! 727: 716 00014F2B # writes( ! 728: 717 00014F2B # "\nTesting clock event during 128 ADDF's with instruction cache "); ! 729: 718 00014F2B .data 1 ! 730: 719 000005a9 * L440: ! 731: 720 000005a9 * 0A54657374696E6720636C6F6 .ascii "\12Testing clock event during 128 ADDF's with instruction cache \0" ! 732: 36B206576656E742064757269 ! 733: 6E67203132382041444446277 ! 734: 3207769746820696E73747275 ! 735: 6374696F6E206361636865200 ! 736: 0 ! 737: 721 000005e8 * .text ! 738: 722 00014F2B dd 8f000005a9 pushl $L440 ! 739: 723 00014F31 fe 08 effffffbdc callf $8,_writes ! 740: 724 00014F38 # if( i_cache_hit ) ! 741: 725 00014F38 5d effffffbd6 tstl _i_cache_hit ! 742: 726 00014F3E 31 0f jeql L441 ! 743: 727 00014F40 # writes("hits\n"); ! 744: 728 00014F40 .data 1 ! 745: 729 000005e8 * L442: ! 746: 730 000005e8 * 686974730A00 .ascii "hits\12\0" ! 747: 731 000005ee * .text ! 748: 732 00014F40 dd 8f000005e8 pushl $L442 ! 749: 733 00014F46 fe 08 effffffbc7 callf $8,_writes ! 750: 734 00014F4D # else ! 751: 735 00014F4D 11 0d jbr L443 ! 752: 736 00014F4F L441: ! 753: 737 00014F4F # writes("misses\n"); ! 754: 738 00014F4F .data 1 ! 755: 739 000005ee * L444: ! 756: 740 000005ee * 6D69737365730A00 .ascii "misses\12\0" ! 757: 741 000005f6 * .text ! 758: 742 00014F4F dd 8f000005ee pushl $L444 ! 759: 743 00014F55 fe 08 effffffbb8 callf $8,_writes ! 760: 744 00014F5C L443: ! 761: 745 00014F5C # } ! 762: 746 00014F5C # if( halt_flg ) ! 763: 747 00014F5C L433: ! 764: 748 00014F5C 5d effffffbb2 tstl _halt_flg ! 765: 749 00014F62 31 09 jeql L445 ! 766: 750 00014F64 # pipe17_halt( 2 ); /* halt with code = 2 */ ! 767: 751 00014F64 dd 02 pushl $2 ! 768: 752 00014F66 fe 08 ef00000005 callf $8,_pipe17_halt ! 769: 753 00014F6D # } ! 770: 754 00014F6D L445: ! 771: 755 00014F6D 40 ret#2 ! 772: 756 00014F6E .set L429,0x0 ! 773: 757 00014F6E L431: ! 774: 758 00014F6E 13 ff38 jbr L432 ! 775: 759 00014F71 .data ! 776: 760 000004a8 * .text ! 777: 761 00014F71 00 .align 1 ! 778: 762 00014F72 .globl _pipe17_halt ! 779: 763 00014F72 _pipe17_halt: ! 780: 764 00014F72 0000 .word L446 ! 781: 765 00014F74 # ! 782: 766 00014F74 # ! 783: 767 00014F74 # ! 784: 768 00014F74 # ! 785: 769 00014F74 # ! 786: 770 00014F74 # /**************************************************************************** ! 787: 771 00014F74 # * halt on error routine ! 788: 772 00014F74 # ****************************************************************************/ ! 789: 773 00014F74 # pipe17_halt( code ) ! 790: 774 00014F74 # int code; /* error code to halt with */ ! 791: 775 00014F74 # { ! 792: 776 00014F74 11 42 jbr L448 ! 793: 777 00014F76 L449: ! 794: 778 00014F76 # err_code = code; ! 795: 779 00014F76 0d ad04 effffffb96 movl 4(fp),_err_code ! 796: 780 00014F7E # asm("movl _test_no,r0"); /* r0 = test number */ ! 797: 781 00014F7E 0d effffffb90 50 movl _test_no,r0 ! 798: 782 00014F85 # asm("movl _subtest,r1"); /* r1 = subtest number */ ! 799: 783 00014F85 0d effffffb89 51 movl _subtest,r1 ! 800: 784 00014F8C # asm("movl _err_code,r2"); /* r2 = error code */ ! 801: 785 00014F8C 0d effffffb82 52 movl _err_code,r2 ! 802: 786 00014F93 # asm("movl _cycle,r3"); /* r3 = cycle count */ ! 803: 787 00014F93 0d effffffb7b 53 movl _cycle,r3 ! 804: 788 00014F9A # asm("movl _sgl_value_1,r4"); /* r4 = operand used */ ! 805: 789 00014F9A 0d effffffb74 54 movl _sgl_value_1,r4 ! 806: 790 00014FA1 # asm("movl _sgl_st_acc,r5"); /* r5 = final value */ ! 807: 791 00014FA1 0d effffffb6d 55 movl _sgl_st_acc,r5 ! 808: 792 00014FA8 # asm("movl _sgl_expected,r6"); /* r6 = expected value */ ! 809: 793 00014FA8 0d effffffb66 56 movl _sgl_expected,r6 ! 810: 794 00014FAF # asm("movl _i_cache_hit,r7"); /* r7 = 1 if cache hits */ ! 811: 795 00014FAF 0d effffffb5f 57 movl _i_cache_hit,r7 ! 812: 796 00014FB6 # asm("halt"); /* HALT ... */ ! 813: 797 00014FB6 00 halt ! 814: 798 00014FB7 # } ! 815: 799 00014FB7 40 ret#2 ! 816: 800 00014FB8 .set L446,0x0 ! 817: 801 00014FB8 L448: ! 818: 802 00014FB8 11 bc jbr L449 ! 819: 803 00014FBA .data ! 820: 804 000004a8 * # ! 821: 805 000004a8 * # ! 822: 805 000004a8 * #
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