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1.1 ! root 1: ! 2: #include "evt_defs.h" ! 3: ! 4: /* ! 5: ********************************************************************* ! 6: * FPP PIPELINED EVENTS TEST #2 ! 7: * ! 8: * This test will execute the following code: "LDD MULD MTPR LDD" ! 9: * with a reserved operand fault on the MTPR. We will make sure that: ! 10: * 1. The fault is detected, ! 11: * 2. the multiply operation completes, and ! 12: * 3. the 2nd load instruction is not executed. ! 13: * ! 14: * NOTE: pipe6 also uses this test's data patterns ! 15: ********************************************************************* ! 16: */ ! 17: pipe2() ! 18: { ! 19: asm("moval (r13),_pre_event_fp"); /* save the frame pointer */ ! 20: asm("moval (r14),_pre_event_sp"); /* save the stack pointer */ ! 21: precision = DBL; ! 22: test_event = RESOP_CODE; /* alignment fault expected */ ! 23: exp_event = FALSE; /* ... but not yet */ ! 24: asm("movab _pipe2_ret,_event_return"); /* set post - event return */ ! 25: dbl_value_2.m = 0x12345678; /* data pattern for the */ ! 26: dbl_value_2.l = 0xfedcba98; /* 2nd LDD instruction */ ! 27: for( index = 0; index < max_pipe2_index; index++ ) ! 28: { ! 29: dbl_ld_acc = pipe2_data[index].op_1; /* get the data */ ! 30: dbl_value_1 = pipe2_data[index].op_2; ! 31: dbl_expected = pipe2_data[index].exp; ! 32: asm(".globl _pipe2_lp1"); ! 33: asm("_pipe2_lp1:"); ! 34: asm("bispsw $0x60"); /* enable ovfl & undfl */ ! 35: asm("ldd _dbl_ld_acc"); /* load the Acc. */ ! 36: exp_event = test_event; /* expect event soon */ ! 37: asm("muld _dbl_value_1"); /* start the multiply */ ! 38: asm("mtpr $1,$0x40");; /* trigger the fault */ ! 39: asm("ldd _dbl_value_2"); /* we shouldn't get to here */ ! 40: /* ! 41: * If we got to here then there was no event ! 42: */ ! 43: if( force_loop ) ! 44: asm("brw _pipe2_lp1");; /* loop on the error */ ! 45: exp_event = FALSE; /* reset event expected flag */ ! 46: asm("movl _pre_event_fp,fp"); /* restore the frame pointer */ ! 47: asm("movl _pre_event_sp,sp"); /* restore the stack pointer */ ! 48: asm("bicpsw $0x60"); /* disable ovfl & undfl evts */ ! 49: no_pipe2_evt();; /* report the error */ ! 50: /* ! 51: * Come here after the event ! 52: */ ! 53: asm(".globl _pipe2_ret"); ! 54: asm("_pipe2_ret:"); ! 55: asm("movl _pre_event_fp,fp"); /* restore the frame pointer */ ! 56: asm("movl _pre_event_sp,sp"); /* restore the stack pointer */ ! 57: if( force_loop ) ! 58: asm("brw _pipe2_lp1");; /* loop on the error */ ! 59: asm("bicpsw $0x60"); /* disable ovfl & undfl evts */ ! 60: if( post_evt_acc.l != dbl_expected.l ) ! 61: bad_pipe2_result(); /* incorrect result error */ ! 62: else if( post_evt_acc.m != dbl_expected.m ) ! 63: { ! 64: if( (post_evt_acc.m == dbl_value_2.m) && ! 65: (post_evt_acc.l == dbl_value_2.l) ) ! 66: pipe2_queue_er(); /* queue not cleared error */ ! 67: else ! 68: bad_pipe2_result(); /* incorrect result error */ ! 69: } ! 70: } ! 71: } ! 72: ! 73: ! 74: ! 75: /**************************************************************************** ! 76: * Report an "EVENT NOT DETECTED" error ! 77: * ! 78: * Cycle: xx. EVT test xx. subtest xx. No Reserved Operand fault. index = xx ! 79: * inst = LDD op1, MULD op2, MTPR 1,0x40, LDD op3 (Reserved Op. fault on MTPR) ! 80: * op1 = xxxxxxxx xxxxxxxx, op2 = xxxxxxxx xxxxxxxx ! 81: ****************************************************************************/ ! 82: no_pipe2_evt() ! 83: { ! 84: errcnt++; /* bump the error count */ ! 85: if ( prt_error ) { ! 86: print_pipe2_err( " No Reserved Operand fault." ); ! 87: writes("op1 = "); ! 88: write32h( dbl_ld_acc.m ); ! 89: writes(" "); ! 90: write32h( dbl_ld_acc.l ); ! 91: writes(", op2 = "); ! 92: write32h( dbl_value_1.m ); ! 93: writes(" "); ! 94: write32h( dbl_value_1.l ); ! 95: writec('\n'); ! 96: } ! 97: if ( halt_flg ) /* halt on error? */ ! 98: pipe2_halt( 1 ); /* halt with a code of 1 */ ! 99: if ( loop_on_err ) { ! 100: force_loop = TRUE; /* set the force loop flag */ ! 101: asm("jmp _pipe2_lp1"); /* and loop */ ! 102: }; ! 103: } ! 104: ! 105: ! 106: ! 107: ! 108: /**************************************************************************** ! 109: * Report an "BAD ACCUMULATOR AFTER THE EVENT" error ! 110: * ! 111: * Cycle: xx. EVT test xx. subtest xx. Bad final Accumulator. index = xx ! 112: * inst = LDD op1, MULD op2, MTPR 1,0x40, LDD op3 (Reserved Op. fault on MTPR) ! 113: * The 2nd LDD should not be executed. ! 114: * op1 = xxxxxxxx xxxxxxxx, final Acc. = xxxxxxxx xxxxxxxx ! 115: * op2 = xxxxxxxx xxxxxxxx, expected = xxxxxxxx xxxxxxxx ! 116: * op3 = xxxxxxxx xxxxxxxx ! 117: ****************************************************************************/ ! 118: bad_pipe2_result() ! 119: { ! 120: errcnt++; /* bump the error count */ ! 121: if ( prt_error ) { ! 122: print_pipe2_err( ". Bad final Accumulator." ); ! 123: writes("The 2nd LDD should not be executed\n"); ! 124: writes("op1 = "); ! 125: write32h( dbl_ld_acc.m ); ! 126: writes(" "); ! 127: write32h( dbl_ld_acc.l ); ! 128: writes(", final Acc. = "); ! 129: write32h( post_evt_acc.m ); ! 130: writec(' '); ! 131: write32h( post_evt_acc.l ); ! 132: writes("\nop2 = "); ! 133: write32h( dbl_value_1.m ); ! 134: writes(" "); ! 135: write32h( dbl_value_1.l ); ! 136: writes(", expected = "); ! 137: write32h( dbl_expected.m ); ! 138: writes(" "); ! 139: write32h( dbl_expected.l ); ! 140: writes("\nop3 = "); ! 141: write32h( dbl_value_2.m ); ! 142: writes(" "); ! 143: write32h( dbl_value_2.l ); ! 144: writec('\n'); ! 145: } ! 146: if ( halt_flg ) /* halt on error? */ ! 147: pipe2_halt( 2 ); /* halt with a code of 2 */ ! 148: if ( loop_on_err ) { ! 149: force_loop = TRUE; /* set the force loop flag */ ! 150: asm("jmp _pipe2_lp1"); /* and loop */ ! 151: }; ! 152: } ! 153: ! 154: ! 155: ! 156: ! 157: /**************************************************************************** ! 158: * Report an "FPP Queue not cleared" error ! 159: * ! 160: * Cycle: xx. EVT test xx. subtest xx. FPP queue not cleared. index = xx ! 161: * inst = LDD op1, MULD op2, MTPR 1,0x40, LDD op3 (Reserved Op. fault on MTPR) ! 162: * The 2nd LDD should not have been executed but apparently was. ! 163: * op1 = xxxxxxxx xxxxxxxx, final Acc. = xxxxxxxx xxxxxxxx ! 164: * op2 = xxxxxxxx xxxxxxxx, expected = xxxxxxxx xxxxxxxx ! 165: * op3 = xxxxxxxx xxxxxxxx ! 166: ****************************************************************************/ ! 167: pipe2_queue_er() ! 168: { ! 169: errcnt++; /* bump the error count */ ! 170: if ( prt_error ) { ! 171: print_pipe2_err( ". FPP queue not cleared." ); ! 172: writes( ! 173: "The 2nd LDD should not have been executed but apparently was.\n"); ! 174: writes("op1 = "); ! 175: write32h( dbl_ld_acc.m ); ! 176: writes(" "); ! 177: write32h( dbl_ld_acc.l ); ! 178: writes(", final Acc. = "); ! 179: write32h( post_evt_acc.m ); ! 180: writec(' '); ! 181: write32h( post_evt_acc.l ); ! 182: writes("\nop2 = "); ! 183: write32h( dbl_value_1.m ); ! 184: writes(" "); ! 185: write32h( dbl_value_1.l ); ! 186: writes(", expected = "); ! 187: write32h( dbl_expected.m ); ! 188: writes(" "); ! 189: write32h( dbl_expected.l ); ! 190: writes("\nop3 = "); ! 191: write32h( dbl_value_2.m ); ! 192: writes(" "); ! 193: write32h( dbl_value_2.l ); ! 194: writec('\n'); ! 195: } ! 196: if ( halt_flg ) /* halt on error? */ ! 197: pipe2_halt( 3 ); /* halt with a code of 3 */ ! 198: if ( loop_on_err ) { ! 199: force_loop = TRUE; /* set the force loop flag */ ! 200: asm("jmp _pipe2_lp1"); /* and loop */ ! 201: }; ! 202: } ! 203: ! 204: ! 205: ! 206: ! 207: ! 208: /**************************************************************************** ! 209: * Report an error message of the form ! 210: * ! 211: * Cycle: xx. EVT test xx. subtest xx <your message here> index = xx ! 212: * inst = LDD op1, MULD op2, MTPR 1,0x40, LDD op3 (fault expected on the MTPR) ! 213: ****************************************************************************/ ! 214: print_pipe2_err( msg ) ! 215: char *msg; /* pointer to error message */ ! 216: { ! 217: if( errcnt == 1 ) /* 1st error? */ ! 218: writes(" \n"); /* start a new print line */ ! 219: writes("Cycle: "); ! 220: writed( cycle ); ! 221: writes(" EVT test "); ! 222: writed( test_no ); ! 223: writes(". subtest "); ! 224: writed( subtest ); ! 225: writes( msg ); /* print the error message */ ! 226: writes(" index = "); ! 227: writed( index ); ! 228: writes("\ninst = LDD op1, MULD op2, MTPR 1,0x40, LDD op3"); ! 229: writes(" (Reserved Op. fault on the MTPR)\n"); ! 230: } ! 231: ! 232: ! 233: /**************************************************************************** ! 234: * Error Halt Routine ! 235: ****************************************************************************/ ! 236: pipe2_halt( code ) ! 237: int code; /* halt code to use */ ! 238: { ! 239: err_code = code; ! 240: sgl_value_1 = dbl_ld_acc.m; ! 241: sgl_value_2 = dbl_ld_acc.l; ! 242: sgl_value_3 = dbl_value_1.m; ! 243: sgl_value_4 = dbl_value_1.l; ! 244: asm("movl _test_no,r0"); /* r0 = test number */ ! 245: asm("movl _subtest,r1"); /* r1 = subtest number */ ! 246: asm("movl _err_code,r2"); /* r2 = error code */ ! 247: asm("movl _cycle,r3"); /* r3 = cycle count */ ! 248: asm("movl _sgl_value_1,r4"); /* r4 = MSW of operand 1 */ ! 249: asm("movl _sgl_value_2,r5"); /* r5 = LSW of operand 1 */ ! 250: asm("movl _sgl_value_3,r6"); /* r6 = MSW of operand 2 */ ! 251: asm("movl _sgl_value_4,r7"); /* r7 = LSW of operand 2 */ ! 252: if( code == 1 ) { ! 253: asm("movl _index,r8"); /* r8 = data index */ ! 254: asm("halt"); /* HALT ... */ ! 255: } else { ! 256: sgl_value_1 = post_evt_acc.m; ! 257: sgl_value_2 = post_evt_acc.l; ! 258: sgl_value_3 = dbl_expected.m; ! 259: sgl_value_4 = dbl_expected.l; ! 260: sgl_value_5 = dbl_value_2.m; ! 261: sgl_value_6 = dbl_value_2.l; ! 262: asm("movl _sgl_value_1,r8"); /* r8 = MSW of final acc. */ ! 263: asm("movl _sgl_value_2,r9"); /* r9 = LSW of final acc. */ ! 264: asm("movl _sgl_value_3,r10"); /* r10 = MSW of expected */ ! 265: asm("movl _sgl_value_4,r11"); /* r11 = LSW of expected */ ! 266: asm("movl _sgl_value_5,r12"); /* r12 = MSW of operand 3 */ ! 267: asm("movl _sgl_value_6,r13"); /* r13 = LSW of operand 3 */ ! 268: asm("movl _index,r14"); /* r14 = data index */ ! 269: } ! 270: asm("halt"); /* HALT ... */ ! 271: }
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