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1.1 ! root 1: ! 2: #include "evt_defs.h" ! 3: ! 4: /* ! 5: ********************************************************************* ! 6: * FPP PIPELINED EVENTS TEST #5 ! 7: * ! 8: * This test will execute the following code: "LDD MULD LDF" ! 9: * with an reserved operand fault on the MULD. We will make sure that: ! 10: * 1. The fault is detected, ! 11: * 2. the negate instruction is not executed. ! 12: ********************************************************************* ! 13: */ ! 14: pipe5() ! 15: { ! 16: asm("moval (r13),_pre_event_fp"); /* save the frame pointer */ ! 17: asm("moval (r14),_pre_event_sp"); /* save the stack pointer */ ! 18: precision = DBL; ! 19: test_event = RESOP_CODE; /* reserved op fault expected */ ! 20: exp_event = FALSE; /* ... but not yet */ ! 21: asm("movab _pipe5_ret,_event_return"); /* post event addr */ ! 22: for( index = 0; index < flt_resop_cnt; index++ ) ! 23: { ! 24: dbl_ld_acc = acc_data[ index ]; ! 25: dbl_value_1 = flt_resops[ index ].op_1; ! 26: dbl_value_3.m = 0x12345678; /* get dummy load value */ ! 27: dbl_value_3.l = 0xabcdef01; /* get dummy load value */ ! 28: asm(".globl _pipe5_lp1"); ! 29: asm("_pipe5_lp1:"); ! 30: asm("bispsw $0x60"); /* enable ovfl & undfl */ ! 31: asm("ldd _dbl_ld_acc"); /* load the Acc. */ ! 32: exp_event = test_event; /* expect event soon */ ! 33: asm("muld _dbl_value_1"); /* cause the event */ ! 34: asm("ldd _dbl_value_3"); /* we shouldn't get here */ ! 35: /* ! 36: * If we got to here then there was no event ! 37: */ ! 38: if( force_loop ) ! 39: asm("brw _pipe5_lp1");; /* loop on the error */ ! 40: exp_event = FALSE; /* reset event expected flag */ ! 41: asm("movl _pre_event_fp,fp"); /* restore the frame pointer */ ! 42: asm("movl _pre_event_sp,sp"); /* restore the stack pointer */ ! 43: asm("bicpsw $0x60"); /* disable ovfl & undfl evts */ ! 44: no_pipe5_evt();; /* report the error */ ! 45: /* ! 46: * Come here after the event ! 47: */ ! 48: asm(".globl _pipe5_ret"); ! 49: asm("_pipe5_ret:"); ! 50: asm("movl _pre_event_fp,fp"); /* restore the frame pointer */ ! 51: asm("movl _pre_event_sp,sp"); /* restore the stack pointer */ ! 52: if( force_loop ) ! 53: asm("brw _pipe5_lp1");; /* loop on the error */ ! 54: asm("bicpsw $0x60"); /* disable ovfl & undfl evts */ ! 55: if( post_evt_acc.m == dbl_value_3.m ) ! 56: pipe5_queue(); /* fpp queue not cleared */ ! 57: else if( post_evt_acc.m ) /* was the Acc. cleared? */ ! 58: bad_pipe5_result(); /* incorrect result error */ ! 59: } ! 60: } ! 61: ! 62: ! 63: ! 64: /**************************************************************************** ! 65: * Report an "EVENT NOT DETECTED" error ! 66: * ! 67: * Cycle: xx. EVT test xx. subtest xx. no reserved op fault. index = xx ! 68: * inst = LDD op1, MULD op2, LDF op3 (reserved operand fault on MULL3) ! 69: * op1 = xxxxxxxx xxxxxxxx, op2 = xxxxxxxx xxxxxxxx, op3 = xxxxxxxx ! 70: ****************************************************************************/ ! 71: no_pipe5_evt() ! 72: { ! 73: errcnt++; /* bump the error count */ ! 74: if ( prt_error ) ! 75: { ! 76: print_pipe5_er( ". no reserved op fault."); ! 77: writes("op1 = "); ! 78: write32h( dbl_ld_acc.m ); ! 79: writec(' '); ! 80: write32h( dbl_ld_acc.l ); ! 81: writes(", op2 = "); ! 82: write32h( dbl_value_1.m ); ! 83: writec(' '); ! 84: write32h( dbl_value_1.l ); ! 85: writes(", op3 = "); ! 86: write32h( dbl_value_3.m ); ! 87: writec('\n'); ! 88: } ! 89: if ( halt_flg ) /* halt on error? */ ! 90: pipe5_halt( 1 ); ! 91: if ( loop_on_err ) ! 92: { ! 93: force_loop = TRUE; /* set the force loop flag */ ! 94: asm("jmp _pipe5_lp1"); /* and loop */ ! 95: }; ! 96: } ! 97: ! 98: ! 99: ! 100: ! 101: /**************************************************************************** ! 102: * Report an "BAD ACCUMULATOR AFTER THE EVENT" error ! 103: * ! 104: * Cycle: xx. EVT test xx. subtest xx. Bad final Accumulator. index = xx ! 105: * inst = LDD op1, MULD op2, LDF op3 (reserved operand fault on MULL3) ! 106: * The LDF should not have been executed. ! 107: * op1 = xxxxxxxx xxxxxxxx, final Acc. = xxxxxxxx xxxxxxxx ! 108: * op2 = xxxxxxxx xxxxxxxx, expected = xxxxxxxx xxxxxxxx ! 109: * op3 = xxxxxxxx ! 110: ****************************************************************************/ ! 111: bad_pipe5_result() ! 112: { ! 113: errcnt++; /* bump the error count */ ! 114: if ( prt_error ) ! 115: { ! 116: print_pipe5_er(". Bad final Accumulator."); ! 117: writes("The LDF should not have been executed.\n"); ! 118: writes("op1 = "); ! 119: write32h( dbl_value_1.m ); ! 120: writec(' '); ! 121: write32h( dbl_value_1.l ); ! 122: writes(", final Acc. = "); ! 123: write32h( post_evt_acc.m ); ! 124: writec(' '); ! 125: write32h( post_evt_acc.l ); ! 126: writes("\nop2 = "); ! 127: write32h( dbl_value_2.m ); ! 128: writec(' '); ! 129: write32h( dbl_value_2.l ); ! 130: writes(", expected = "); ! 131: write32h( 0 ); ! 132: writec(' '); ! 133: write32h( 0 ); ! 134: writes("\nop_3 = "); ! 135: write32h( dbl_value_3.m ); ! 136: writec('\n'); ! 137: } ! 138: if ( halt_flg ) /* halt on error? */ ! 139: pipe5_halt( 2 ); ! 140: if ( loop_on_err ) ! 141: { ! 142: force_loop = TRUE; /* set the force loop flag */ ! 143: asm("jmp _pipe5_lp1"); /* and loop */ ! 144: }; ! 145: } ! 146: ! 147: ! 148: ! 149: ! 150: ! 151: /**************************************************************************** ! 152: * Report an "FPP Queue apparently not cleared" error ! 153: * ! 154: * Cycle: xx. EVT test xx. subtest xx. Fpp Queue not cleared. index = xx ! 155: * inst = LDD op1, MULD op2, LDF op3 (reserved operand fault on MULD) ! 156: * The LDF should not have been executed but apparently was. ! 157: * op1 = xxxxxxxx xxxxxxxx, final Acc. = xxxxxxxx xxxxxxxx ! 158: * op2 = xxxxxxxx xxxxxxxx, expected = xxxxxxxx xxxxxxxx ! 159: * op3 = xxxxxxxx ! 160: ****************************************************************************/ ! 161: pipe5_queue() ! 162: { ! 163: errcnt++; /* bump the error count */ ! 164: if ( prt_error ) ! 165: { ! 166: print_pipe5_er(". Fpp Queue not cleared."); ! 167: writes( ! 168: "The NEGF should not have been executed but apparently was.\n"); ! 169: writes("op1 = "); ! 170: write32h( dbl_value_1.m ); ! 171: writec(' '); ! 172: write32h( dbl_value_1.l ); ! 173: writes(", final Acc. = "); ! 174: write32h( post_evt_acc.m ); ! 175: writec(' '); ! 176: write32h( post_evt_acc.l ); ! 177: writes("\nop2 = "); ! 178: write32h( dbl_value_2.m ); ! 179: writec(' '); ! 180: write32h( dbl_value_2.l ); ! 181: writes(", expected = "); ! 182: write32h( 0 ); ! 183: writec(' '); ! 184: write32h( 0 ); ! 185: writes("\nop_3 = "); ! 186: write32h( dbl_value_3.m ); ! 187: writec('\n'); ! 188: } ! 189: if ( halt_flg ) /* halt on error? */ ! 190: pipe5_halt( 3 ); ! 191: if ( loop_on_err ) ! 192: { ! 193: force_loop = TRUE; /* set the force loop flag */ ! 194: asm("jmp _pipe5_lp1"); /* and loop */ ! 195: }; ! 196: } ! 197: ! 198: ! 199: ! 200: /**************************************************************************** ! 201: * print an error message of the form: ! 202: * ! 203: * Cycle: xx. EVT test xx. subtest xx. <your message here> index = xx ! 204: * inst = LDD op1, MULD op2, LDF op3 (reserved operand fault on MULD) ! 205: ****************************************************************************/ ! 206: print_pipe5_er( msg ) ! 207: char *msg; /* error message to print */ ! 208: { ! 209: if( errcnt == 1 ) /* 1st error? */ ! 210: writes(" \n"); /* start a new print line */ ! 211: writes("Cycle: "); ! 212: writed( cycle ); ! 213: writes(" EVT test "); ! 214: writed( test_no ); ! 215: writes(". subtest "); ! 216: writed( subtest ); ! 217: writes( msg ); /* print the error message */ ! 218: writes(" index = "); ! 219: writed( index ); ! 220: writes("\ninst = LDD op1; MULD op2; LDFop3"); ! 221: writes(" (reserved operand fault on MULL3)\n"); ! 222: } ! 223: ! 224: ! 225: ! 226: /**************************************************************************** ! 227: * Halt on Error routine ! 228: ****************************************************************************/ ! 229: pipe5_halt( code ) ! 230: int code; /* error code to halt with */ ! 231: { ! 232: err_code = code; ! 233: sgl_value_4 = dbl_ld_acc.m; ! 234: sgl_value_5 = dbl_ld_acc.l; ! 235: sgl_value_6 = dbl_value_1.m; ! 236: sgl_value_7 = dbl_value_1.l; ! 237: asm("movl _test_no,r0"); /* r0 = test number */ ! 238: asm("movl _subtest,r1"); /* r1 = subtest number */ ! 239: asm("movl _err_code,r2"); /* r2 = error code */ ! 240: asm("movl _cycle,r3"); /* r3 = cycle count */ ! 241: asm("movl _sgl_value_4,r4"); /* r4 = MSW of operand 1 */ ! 242: asm("movl _sgl_value_5,r5"); /* r5 = LSW of operand 1 */ ! 243: asm("movl _sgl_value_6,r6"); /* r6 = MSW of operand 2 */ ! 244: asm("movl _sgl_value_7,r7"); /* r7 = LSW of operand 2 */ ! 245: asm("movl _sgl_value_8,r8"); /* r8 = operand 3 */ ! 246: if( code == 1 ) ! 247: asm("movl _index,r9"); /* r9 = data index */ ! 248: else { ! 249: sgl_value_6 = post_evt_acc.m; ! 250: sgl_value_7 = post_evt_acc.l; ! 251: asm("movl _sgl_value_6,r9"); /* r9 = MSW of final acc. */ ! 252: asm("movl _sgl_value_7,r10"); /* r10 = LSW of final acc. */ ! 253: asm("movl _index,r11"); /* r11 = data index */ ! 254: } ! 255: asm("halt");; /* HALT ... */ ! 256: }
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